Abstract: Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed.

Abstract: A trench semiconductor power device with a termination area structure is disclosed. The termination area structure comprises a wide trench and a trenched field plate formed not only along trench sidewall but also on trench bottom of the wide trench by doing poly-silicon CMP so that the body ion implantation is blocked by the trenched field plate on the trench bottom to prevent the termination area underneath the wide trench from being implanted. Moreover, a contact mask is used to define both trenched contacts and source regions of the device for saving a source mask.

Abstract: In a semiconductor device in which a diode and an IGBT are formed in a main region of a same semiconductor substrate, in order to obtain a sufficiently large sense IGBT current in a stable manner, a sense region is provided with a first region in which a distance from an end of a main cathode region on a side of the sense region in a plan view of the semiconductor substrate is equal to or longer than 615 ?m. Alternatively, in order to obtain a sufficiently large sense diode current in a stable manner, the sense region is provided with a second region in which a distance from the main cathode region in a plan view of the semiconductor substrate is equal to or shorter than 298 ?m. The sense region may be provided with both the first region and the second region.

Abstract: A silicon on insulator integrated high-current N type combined semiconductor device, which can improve the current density, comprises a P type substrate and a buried oxide layer arranged thereon. A P type epitaxial layer divided into a region I and a region II is arranged on the buried oxide layer. The region I comprises an N type drift region, a P type deep well, an N type buffer well, a P type drain region, an N type source region and a P type body contact region; a field oxide layer and agate oxide layer are arranged on a silicon surface, and a polysilicon lattice is arranged on the gate oxide layer. The region II comprises an N type triode drift region, a P type deep well, an N type triode buffer well, a P type emitting region, an N type base region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer are arranged on a silicon surface, and a polysilicon lattice is arranged on the gate oxide layer.

Abstract: A semiconductor component includes a semiconductor body, a first emitter region of a first conductivity type in the semiconductor body, a second emitter region of a second conductivity type arranged distant to the first emitter region in a vertical direction of the semiconductor body, a base region of one of the first and second conductivity types arranged between the first and second emitter regions and having a lower doping concentration than the first second emitter regions, a first field stop zone of the same conductivity type as the base region arranged in the base region, and a second field stop zone of the same conductivity type as the base region arranged in the base region.

Abstract: A semiconductor device includes a transistor having a gate electrode, a first electrode, and a second electrode and first and second protection circuits each having one end commonly connected to the gate electrode and the other end connected to the first and second electrodes, respectively. The first and second protection circuits are formed in first and second polysilicon layers, respectively, formed separately on a single field insulating film.

Abstract: A reverse-conducting semiconductor device includes a freewheeling diode and an insulated gate bipolar transistor (IGBT) on a common wafer. Part of the wafer forms a base layer with a base layer thickness. The IGBT includes a collector side and an emitter side arranged on opposite sides of the wafer. A first layer of a first conductivity type and a second layer of a second conductivity type are alternately arranged on the collector side. The first layer includes at least one first region with a first region width and at least one first pilot region with a first pilot region width. The second layer includes at least one second region with a second region width and at least one second pilot region with a second pilot region width. Each second region width is equal to or larger than the base layer thickness, whereas each first region width is smaller than the base layer thickness. Each second pilot region width is larger than each first pilot region width.

Abstract: The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate. The transistor includes a collector region that is formed in a portion of the substrate. The transistor includes a base region that is surrounded by the collector region. The transistor includes an emitter region that is surrounded by the based region. The transistor includes an isolation structure that is disposed adjacent the emitter region. The transistor includes a gate structure that is disposed over a portion of the emitter region and a portion of the isolation structure.

Abstract: An exemplary power semiconductor device with a wafer having an emitter electrode on an emitter side and a collector electrode on a collector side, an (n-) doped drift layer, an n-doped first region, a p-doped base layer, an n-doped source region, and a gate electrode, all of which being formed between the emitter and collector electrodes. The emitter electrode contacts the base layer and the source region within a contact area. An active semiconductor cell is formed within the wafer, and includes layers that lie in orthogonal projection with respect to the emitter side of the contact area of the emitter electrode. The device also includes a p-doped well, which is arranged in the same plane as the base layer, but outside the active cell. The well is electrically connected to the emitter electrode at least one of directly or via the base layer.

Abstract: In a semiconductor device including an IGBT and a freewheeling diode (FWD), W1, W2, and W3 satisfy predetermined formulas. W1 denotes a distance from a boundary between a cathode region and a collector region to a position, where a peripheral-region-side end of the well layer is projected, on a back side of the drift layer. W2 denotes a distance from a boundary between the IGBT and the FWD in a base region to the peripheral-region-side end of the well layer. W3 denotes a distance from the boundary between the cathode region and the collector region to a position, where a boundary between the base region and the well layer is projected, on the back side.

Abstract: A semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed is provided. The diode region includes a first layer embedded in a diode trench reaching a diode drift layer from an upper surface side of the semiconductor substrate, and a second layer which is buried in the first layer and which has a lower end located deeper than a boundary between a diode body layer and the diode drift layer. The second layer pressures the first layer in a direction from inside to outside of the diode trench. A lifetime control region is formed in the diode drift layer at least at the depth of the lower end of the second layer, and a crystal defect density inside the lifetime control region is higher than a crystal defect density outside the lifetime control region.

Abstract: In a semiconductor device, at least one of the ratio (collector contact area/collector active area) in the High Side IGBT and the ratio (contact area on p+ region/p30 region area) is higher than the ratio in the Low Side IGBT. Thus, it is possible to develop without substantial changes and reduce the development burden.

Abstract: An integrated circuit device includes a semiconductor substrate and a first transistor and a second transistor constructed in the semiconductor substrate. The first transistor has a first operating voltage higher than a second operating voltage of a second transistor. The first transistor includes a first drain structure, a first source structure, an isolation structure and a first gate structure. The first source structure includes a high voltage first-polarity well region, a first-polarity body region, a heavily doped first-polarity region, a second-polarity grade region and a heavily doped second-polarity region. The heavily doped second-polarity region is surrounded by the second-polarity grade region. The second-polarity grade region is surrounded by the first-polarity body region. The second transistor includes a second drain structure, a second source structure, a second gate structure and a first-polarity drift region.

Abstract: A hybrid transistor device is provided. In one example case, the device includes a substrate, an oxide layer formed on the substrate, and a wide-bandgap body material formed between a portion of the oxide layer and a gate dielectric layer. The wide-bandgap body material has an energy bandgap higher than that of silicon. The device includes source-drain/emitter material formed on the oxide layer adjacent to the wide-bandgap body material so as to define a hetero-structure interface where the source-drain/emitter material contacts the wide-bandgap body material. The device includes a gate material formed over the gate dielectric layer, a base material formed over a portion of the source-drain/emitter material, and a collector material formed over a portion of the base material. The source-drain/emitter material is shared so as to electrically combine a drain of a first transistor type portion of the device and an emitter of a second transistor type portion.

Abstract: A structure of power semiconductor device integrated with clamp diodes having separated gate metal pads is disclosed. The separated gate metal pads are wire bonded together on the gate lead frame. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon or gate metal.

Abstract: Provided is a circuit device having a configuration in which thermal interference between built-in elements is suppressed and being miniaturized in total size. A hybrid integrated circuit device of the present invention includes: a circuit substrate, a sealing resin and leads. The circuit substrate in its upper surface is incorporated with a hybrid integrated circuit formed of semiconductor elements and the like respectively fixed to heat spreaders. The sealing resin coats the circuit substrate and thus seals the hybrid integrated circuit. The leads each extend to the outside while being fixed to a pad formed of a conductive pattern. In this hybrid integrated circuit device, the semiconductor elements are mounted on the respective heat spreaders at positions offset from each other, and thereby are arranged to be spaced away from each other.

Abstract: A semiconductor arrangement includes a first and second controllable vertical n-channel semiconductor chip. Each of the controllable vertical n-channel semiconductor chips has a front side, a rear side opposite the front side, a front side main contact arranged on the front side, a rear side main contact arranged on the rear side, and a gate contact arranged on the front side for controlling an electric current between the front side main contact and the rear side main contact. The rear side contacts of the first and second semiconductor chips are electrically connected to one another.

Abstract: The present teachings provide a semiconductor device comprising: an IGBT element region, a diode element region and a boundary region provided between the IGBT element region and the diode element region are formed in one semiconductor substrate. The boundary region comprises a second conductivity type first diffusion region, a first conductivity type second diffusion region, and a second conductivity type third diffusion region. A first drift region of the IGBT element region contiguously contacts the first diffusion region of the boundary region, and a second drift region of the diode element region contiguously contacts the first diffusion region of the boundary region. A first body region of the IGBT element region contiguously contacts the second diffusion region of the boundary region, and a second body region of the diode element region contiguously contacts the second diffusion region of the boundary region.

Abstract: A power semiconductor device is provided in which reliability can be improved when the parallel number of semiconductor devices increases. When a bonding face on collector electrode is on an upper side, and a bonding face on emitter electrode is on a lower side, a collector electrode joint region as a joint region between a collector trace and a collector electrode on a chip mounted substrate and an emitter electrode joint region as a joint region between an emitter trace and an emitter electrode are located at a same position in an up-and-down direction and are adjacent in a right-and-left direction at an interval of 2 mm or more and 4 mm or less.

Abstract: According to an exemplary embodiment, a stacked half-bridge power module includes a high side device having a high side power terminal coupled to a high side substrate and a low side device having a low side power terminal coupled to a low side substrate. The high side and low side devices are stacked on opposite sides of a common conductive interface. The common conductive interface electrically, mechanically, and thermally couples a high side output terminal of the high side device to a low side output terminal of the low side device. The high side device and the low side device can each include an insulated-gate bipolar transistor (IGBT) in parallel with a diode.

Abstract: In a semiconductor device in which a diode and an IGBT are formed in a main region of a same semiconductor substrate, in order to obtain a sufficiently large sense IGBT current in a stable manner, a sense region is provided with a first region in which a distance from an end of a main cathode region on a side of the sense region in a plan view of the semiconductor substrate is equal to or longer than 615 ?m. Alternatively, in order to obtain a sufficiently large sense diode current in a stable manner, the sense region is provided with a second region in which a distance from the main cathode region in a plan view of the semiconductor substrate is equal to or shorter than 298 ?m. The sense region may be provided with both the first region and the second region.

Abstract: A semiconductor device has a first conductivity-type semiconductor substrate, second conductivity-type channel regions, and second conductivity-type thinning-out regions. The channel regions and the thinning-out regions are formed adjacent to a substrate surface of the semiconductor substrate. Further, a hole stopper layer is formed in each of the thinning-out regions to divide the thinning-out region into a first part adjacent to the substrate surface and a second part adjacent to a bottom of the thinning-out region. The hole stopper layer has an area density of equal to or less than 4.0×1012 cm?2 to permit a depletion layer to punch through the hole stopper layer, thereby to restrict breakdown properties from being decreased.

Abstract: A semiconductor device includes a semiconductor substrate in which a diode region and an IGBT region are formed, wherein a lower surface side of the semiconductor substrate comprises a low impurity region provided between a second conductivity type cathode region of the diode region and a first conductivity type collector region of the IGBT region. The low impurity region includes at least one of a first conductivity type first low impurity region which has a lower density of first conductivity type impurities than that in the collector region and a second conductivity type second low impurity region which has a lower density of second conductivity type impurities than that in the cathode region.

Abstract: A semiconductor device includes an IGBT forming region and a diode forming region. The IGBT forming region includes an IGBT operating section that operates as an IGBT and a thinned-out section that does not operate as an IGBT. The IGBT operating section includes a channel region, and the thinned-out section includes a first anode region. The diode forming region includes a second anode region. When an area density is defined as a value calculated by integrating a concentration profile of second conductivity type impurities in each of the channel region, the first anode region, and the second anode region in a depth direction, an area density of the channel region is higher than an area density of the first anode region and an area density of the second anode region.

Abstract: A hybrid IGBT device having a VIGBT and LDMOS structures comprises at least a drain trenched contact filled with a conductive plug penetrating through an epitaxial layer, and extending into a substrate; a vertical drain region surrounding at least sidewalls of the drain trenched contact, extending from top surface of the epitaxial layer to the substrate, wherein the vertical drain region having a higher doping concentration than the epitaxial layer.

Abstract: A semiconductor device, including a semiconductor substrate in which a diode region and an IGBT region are formed, is provided. A lifetime control region is formed within a diode drift region. The diode drift region and the IGBT drift region are a continuous region across a boundary region between the diode region and the IGBT region. A first separation region and a second separation region are formed within the boundary region. The first separation region is formed of a p-type semiconductor, formed in a range extending from an upper surface of the semiconductor substrate to a position deeper than both of a lower end of an anode region and a lower end of a body region, and bordering with the anode region. The second separation region is formed of a p-type semiconductor, formed in a range extending from the upper surface of the semiconductor substrate to a position deeper than both of the lower end of the anode region and the lower end of the body region, and bordering with the body region.

Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.

Abstract: A system and method for digital management and control of power conversion from battery cells. The system utilizes a power management and conversion module that uses a CPU to maintain a high power conversion efficiency over a wide range of loads and to manage charge and discharge operation of the battery cells. The power management and conversion module includes the CPU, a current sense unit, a charge/discharge unit, a DC-to-DC conversion unit, a battery protection unit, a fuel gauge and an internal DC regulation unit. Through intelligent power conversion and charge/discharge operations, a given battery type is given the ability to emulate other battery types by conversion of the output voltage of the battery and adaptation of the charging scheme to suit the battery.

Abstract: In an ultra high voltage lateral DMOS-type device (UHV LDMOS device), a central pad that defines the drain region is surrounded by a racetrack-shaped source region with striations of alternating n-type and p-type material radiating outwardly from the pad to the source to provide for an adjustable snapback voltage.

Abstract: An apparatus includes an electrostatic discharge (ESD) protection device. In one embodiment, the protection device electrically coupled between a first node and a second node of an internal circuit to be protected from transient electrical events. The protection device includes a bipolar device or a silicon-controlled rectifier (SCR). The bipolar device or SCR can have a modified structure or additional circuitry to have a selected holding voltage and/or trigger voltage to provide protection over the internal circuit. The additional circuitry can include one or more resistors, one or more diodes, and/or a timer circuit to adjust the trigger and/or holding voltages of the bipolar device or SCR to a desired level. The protection device can provide protection over a transient voltage that ranges, for example, from about 100 V to 330V.

Abstract: Some exemplary embodiments of high voltage cascaded III-nitride semiconductor package with an etched leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked over a source of the III-nitride transistor, and a leadframe that is etched to form a first leadframe paddle portion coupled to a gate of the III-nitride transistor and the anode of the diode, and a second leadframe paddle portion coupled to a drain of the III-nitride transistor. The leadframe paddle portions enable the package to be surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.

Abstract: A semiconductor device includes: a semiconductor substrate; an IGBT element including a collector region; a FWD element including a cathode region adjacent to the collector region; a base layer on the substrate; multiple trench gate structures including a gate electrode. The base layer is divided by the trench gate structures into multiple first and second regions. Each first region includes an emitter region contacting the gate electrode. Each first region together with the emitter region is electrically coupled with an emitter electrode. The first regions include collector side and cathode side first regions, and the second regions include collector side and cathode side second regions. At least a part of the cathode side second region is electrically coupled with the emitter electrode, and at least a part of the collector side second region has a floating potential.

Abstract: Provided is a semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed. A separation region formed of a p-type semiconductor is formed in a range between the diode region and the IGBT region and extending from an upper surface of the semiconductor substrate to a position deeper than both a lower end of an anode region and a lower end of a body region. A diode lifetime control region is formed within a diode drift region. A carrier lifetime in the diode lifetime control region is shorter than that in the diode drift region outside the diode lifetime control region. An end of the diode lifetime control region on an IGBT region side is located right below the separation region.

Abstract: A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Abstract: It is an object of the present invention to provide a technique in which a high-performance and highly reliable semiconductor device can be manufactured at low cost with high yield. A memory device according to the present invention has a first conductive layer including a plurality of insulators, an organic compound layer over the first conductive layer including the insulators, and a second conductive layer over the organic compound layer.

Abstract: An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on.

Abstract: An internal combustion engine igniter semiconductor device is disclosed which is low cost yet secures energy withstand and reverse surge withstand capability. An IGBT includes a clamping diode between a collector electrode and a gate electrode. The IGBT has two n-type buffer layers of differing impurity concentrations between a p+ substrate and an n-type base layer of the IGBT, wherein the total thickness of the two-layer buffer layer is 50 ?m or less, and the overall impurity amount is 20×1013 cm?2 or less.

Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.

Abstract: A first semiconductor element portion for switching a first current includes a first channel surface having a first plane orientation. A first region of a semiconductor layer includes a first trench having the first channel surface. A first gate insulating film covers the first channel surface with a first thickness. A second semiconductor element portion for switching a second current smaller than the first current includes a second channel surface having a second plane orientation different from the first plane orientation. A second region of the semiconductor layer includes a second trench having the second channel surface. A second gate insulating film covers the second channel surface with a second thickness larger than the first thickness.

Abstract: According to one embodiment, a power semiconductor device includes a first conductor, a second conductor, and a first semiconductor chip. The first conductor includes a first portion and a second portion. The first portion includes a first major surface and a second major surface opposite thereto. The second portion includes a third major surface intersecting at right angles with the first major surface and a fourth major surface opposite to the third major surface. The fourth major surface becomes farther from the third major surface to become continuous with the second major surface with proximity to the first major surface. The second conductor includes a third portion and a fourth portion. The third portion is similar to the first portion. The fourth portion is similar to the second portion. The first semiconductor chip is placed between the second portion and the forth portion.

Abstract: A power semiconductor device comprising a trench IGBT, a trench MOSFET and a fast switching diode for reduction of turn-on loss is disclosed. The inventive semiconductor power device employs a fast switching diode instead of body diode in the prior art. Furthermore, the inventive semiconductor power device further comprises an additional ESD protection diode between emitter metal and gate metal.

Abstract: A bidirectional switch includes a semiconductor element and a substrate potential stabilizer. The semiconductor element includes a first ohmic electrode and a second ohmic electrode, and a first gate electrode and a second gate electrode, which are sequentially formed on the first ohmic electrode between the first ohmic electrode and the second ohmic electrode. The substrate potential stabilizer sets a potential of the substrate lower than higher one of a potential of the first ohmic electrode or a potential of the second ohmic electrode.

Abstract: A lateral insulated gate bipolar transistor (LIGBT) includes a drain-anode adjoining trenched contact penetrating through an insulating layer and extending into an epitaxial layer, directly contacting to a drain region and an anode region, and the drain region vertically contacting to the anode region along sidewall of the drain-anode adjoining trenched contact. The LIGBT further comprises a breakdown voltage enhancement doping region wrapping around the anode region. The LIGBTs in accordance with the invention offer the advantages of high breakdown voltage and low on-resistance as well as high switching speed.

Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface. A main region and a sensing region are formed on the first surface side of the semiconductor substrate. A RC-IGBT is formed in the main region and a sensing element for passing electric currents proportional to electric currents flowing through the RC-IGBT is formed in the sensing region. A collector region and a cathode region of the sensing element are formed on the second surface side of the semiconductor substrate. The collector region is located directly below the sensing region in a thickness direction of the semiconductor substrate. The cathode region is not located directly below the sensing region in the thickness direction.

Abstract: An IGBT with a fast reverse recovery time rectifier includes an N-type drift epitaxial layer, a gate, a gate insulating layer, a P-type doped base region, an N-type doped source region, a P-type doped contact region, and a P-type lightly doped region. The P-type doped base region is disposed in the N-type drift epitaxial layer, and the P-type doped contact region is disposed in the N-type drift epitaxial layer. The P-type lightly doped region is disposed between the P-type contact doped region and the N-type drift epitaxial layer, and is in contact with the N-type drift epitaxial layer.

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

Abstract: This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

Abstract: A semiconductor device includes an output port that has a first lateral double diffused metal oxide semiconductor (LDMOS) device and an electrostatic discharge protection device that has a second LDMOS device and a bipolar transistor and that protects the output port from electrostatic discharge. A breakdown voltage of the second LDMOS device is equal to or lower than a breakdown voltage of the first LDMOS device.

Abstract: It is an object of the present invention to provide a technique to manufacture a highly reliable display device at a low cost with high yield. A display device according to the present invention includes a semiconductor layer including an impurity region of one conductivity type; a gate insulating layer, a gate electrode layer, and a wiring layer in contact with the impurity region of one conductivity type, which are provided over the semiconductor layer; a conductive layer which is formed over the gate insulating layer and in contact with the wiring layer; a first electrode layer in contact with the conductive layer; an electroluminescent layer provided over the first electrode layer; and a second electrode layer, where the wiring layer is electrically connected to the first electrode layer with the conductive layer interposed therebetween.