Abstract: A semiconductor device is configured such that the distance between the trench gate in the IGBT and the trench gate in the diode is reduced or a p-well layer is provided between the trench gate in the IGBT and the trench gate in the diode.

Abstract: A power circuit is described that includes a semiconductor body having a common substrate and a Gallium Nitride (GaN) based substrate. The GaN based substrate includes one or more GaN devices adjacent to a front side of the common substrate. The common substrate is electrically coupled to a node of the power circuit. The node of the power circuit is at a particular potential that is equal to, or more negative than, a potential at one or more load terminals of the one or more GaN devices.

Abstract: In a back surface hole injection type diode, by more effectively securing the effect of hole injection from the back surface of a semiconductor substrate, the performance of a semiconductor device is improved. In the semiconductor device, in a diode formed of a P-N junction including an anode P-type layer formed in the main surface of a semiconductor substrate and a back surface N+-type layer formed in the back surface of the semiconductor substrate, a back surface P+-type layer is formed in the back surface, and a surface P+-type layer is formed in the main surface right above the back surface P+-type layer to thereby promote the effect of hole injection from the back surface.

Abstract: A semiconductor device includes a pn junction between a drift zone and a charge-carrier transfer region in a semiconductor body. An access channel provides a permanent charge carrier path connecting the drift zone with a recombination region through a separation region between the drift zone and the recombination region. The access channel adjusts a plasma density in the drift zone and the recombination region.

Abstract: A semiconductor device includes first electrode, first semiconductor layer of first conductivity type on the first electrode, second semiconductor layer of second conductivity type on the first semiconductor layer, third semiconductor layer of the first conductivity type on second semiconductor layer, fourth semiconductor layer of the second conductivity type selectively located on the third semiconductor layer, gate electrode through the third and fourth semiconductor layers and into the second semiconductor layer and insulated therefrom, second electrode on the fourth semiconductor layer, fifth semiconductor layer of the second conductivity type between the first electrode and the second semiconductor layer, sixth semiconductor layer of the first conductivity type on the second semiconductor layer contacting the second electrode, and seventh semiconductor layer of the first conductivity type in the second and sixth semiconductor layers, such that the bottom thereof is closer to the first electrode than the

Abstract: An external battery includes an input end, an output end, a bare cell between the input end and the output end, a charging unit configured to deliver power from a charger to the bare cell via the input end, a first switch between the charging unit and the input end, a DC-DC converter configured to convert an output voltage from the bare cell into a converted voltage of a magnitude that is different from that of the output voltage, and configured to deliver the converted voltage to the output end, a second switch between the bare cell and the DC-DC converter, and a main controller unit (MCU) configured to sense at least one of overcharging, over-discharging, or an over-discharge current of the bare cell using the output voltage or an output current from the bare cell, and configured to control the first switch and the second switch.

Abstract: The present disclosure relates to an electrostatic discharge (ESD) protection device. The electrostatic discharge protection device, may comprise: a semiconductor controlled rectifier; and a p-n diode. The semiconductor controlled rectifier and the diode may be integrally disposed laterally at a major surface of a semiconductor substrate; and a current path for the semiconductor controlled rectifier may be separate from a current path for the diode.

Abstract: In a semiconductor device including an IGBT and a freewheeling diode W?2×L1/K1/2, where K?2.5, W denotes a distance between the divided first regions, L1 denotes a thickness of the drift layer, k1 denotes a parameter that depends on structures of the insulated gate bipolar transistor and the freewheeling diode, and K denotes a value calculated by multiplying the parameter k1 by a ratio of a snapback voltage to a built-in potential between the deep well layer and the drift layer.

Abstract: In a high voltage JFET, a p-floating region is provided in the surface layer of an n-drift region, thereby increasing the resistance R of the n-drift region and minimizing the voltage divided at a pn junction. This makes it possible to improve ESD capacity without increasing device size and without making the cutoff current smaller.

Abstract: A semiconductor device includes a transistor region and diode region. A plurality of transistors is in the transistor region and at least one diode is in the diode region. The transistors include first and second body regions of a first conductivity type. The dopant concentration in the second body region is greater than the dopant concentration in the first body region. The diode includes first and second anode regions of the first conductivity type. The dopant concentration in the second anode region is greater than the dopant concentration in the first anode region. A total dopant amount in the second body region within a first block portion of the semiconductor substrate is greater than a total dopant amount in the second anode layer within a second block portion of the semiconductor substrate of the same size as the first block portion.

Abstract: When a semiconductor substrate of a semiconductor device is viewed from above, an isolation region, an IGBT region, and a diode region are all formed adjacent to each other. A deep region that is connected to a body region and an anode region is formed in the isolation region. A drift region is formed extending across the isolation region, the IGBT region, and the diode region, inside the semiconductor substrate. A collector region that extends across the isolation region, the IGBT region and the diode region, and a cathode region positioned in the diode region, are formed in a region exposed on a lower surface of the semiconductor substrate. A boundary between the collector region and the cathode region is in the diode region, in a cross-section that cuts across a boundary between the isolation region and the diode region, and divides the isolation region and the diode region.

Abstract: A semiconductor device includes a front surface electrode, a back surface electrode and a semiconductor substrate in which an IGBT and a diode are formed. An outer peripheral back surface p-type region, an outer peripheral back surface n-type region, and an outer peripheral low concentration n-type region are formed in an outer peripheral region. The outer peripheral back surface n-type region is formed on an end surface side of the semiconductor substrate with respect to the outer peripheral back surface p-type region. The outer peripheral low concentration n-type region separates the outer peripheral back surface p-type region and the outer peripheral back surface n-type region from a contact outer peripheral edge p-type region. A p-type impurity concentration in the outer peripheral back surface p-type region decreases toward the end surface. An n-type impurity concentration in the outer peripheral back surface n-type region increases toward the end surface.

Abstract: A semiconductor device with a super-junction structure is provided, including: a semiconductor substrate having a first conductivity type; an epitaxial layer having the first conductivity type formed over the semiconductor substrate; a first doping region having the first conductive type formed in a portion of the epitaxial layer; a second doping region having a second conductivity type formed in a portion of the of the epitaxial layer; a third doping region having the second conductivity type formed in a portion of the of the epitaxial layer, wherein the doping region partially comprises doped polysilicon materials having the second conductivity type; a gate dielectric layer formed over the epitaxial layer, partially overlying the well region; and a gate electrode formed over a portion of the gate dielectric layer.

Abstract: A semiconductor device includes: an insulating substrate; a first electrode pattern and a second electrode pattern provided apart from each other on a major surface of the insulating substrate; a semiconductor element connected to the first electrode pattern; an electrode terminal connected to the second electrode pattern; and a connection wiring. The connection wiring electrically connects the first electrode pattern and the second electrode pattern with each other and has a thermal resistance larger than that of the first electrode pattern.

Abstract: When a semiconductor substrate of a semiconductor device is viewed from above, an isolation region, an IGBT region, and a diode region are all formed adjacent to each other. A deep region that is connected to a body region and an anode region is formed in the isolation region. A drift region is formed extending across the isolation region, the IGBT region, and the diode region, inside the semiconductor substrate. A collector region that extends across the isolation region, the IGBT region and the diode region, and a cathode region positioned in the diode region, are formed in a region exposed on a lower surface of the semiconductor substrate. A boundary between the collector region and the cathode region is in the diode region, in a cross-section that cuts across a boundary between the isolation region and the diode region, and divides the isolation region and the diode region.

Abstract: A transistor device comprises: at least one individual transistor cell arranged in a transistor cell field on a semiconductor body, each individual transistor cell comprising a gate electrode; a gate contact, electrically coupled to the gate electrodes of the transistor cells and configured to switch on the at least one transistor cell by providing a gate current in a first direction and configured to switch off the at least one transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction; at least one gate-resistor structure monolithically integrated in the transistor device, the gate-resistor structure providing a first resistance for the gate current when the gate current flows in the first direction, and providing a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.

Abstract: A semiconductor device is provided that includes a composite semiconductor body including a high voltage depletion-mode transistor and a low voltage enhancement-mode transistor. The high voltage depletion-mode transistor is stacked on the low voltage enhancement-mode transistor so that an interface is formed between the high voltage depletion-mode transistor and the low voltage enhancement-mode transistor. The low voltage enhancement-mode transistor includes a current path coupled in series with a current path of the high voltage depletion-mode transistor, and a control electrode is arranged at the interface.

Abstract: A semiconductor device includes: a drift layer having a first conduction type; a base layer having a second conduction type and formed on the drift layer; an emitter layer having the first conduction type and formed in a surface layer portion of the base layer; a buffer layer having the first conduction type and formed in the drift layer separated from the base layer; a collector layer having the second conduction type and formed selectively in the buffer layer; a gate insulation film in contact with a channel region of the base layer between the drift layer and the emitter layer; a gate electrode formed on the gate insulation film; a first electrode electrically connected to the base layer and the emitter layer; and a second electrode electrically connected to the buffer layer and the collector layer. The buffer layer has a carrier density smaller than a space charge density.

Abstract: A three terminal high voltage Darlington bipolar transistor power switching device includes two high voltage bipolar transistors, with collectors connected together serving as the collector terminal. The base of the first high voltage bipolar transistor serves as the base terminal. The emitter of the first high voltage bipolar transistor connects to the base of the second high voltage bipolar transistor (inner base), and the emitter of the second high voltage bipolar transistor serves as the emitter terminal. A diode has its anode connected to the inner base (emitter of the first high voltage bipolar transistor, or base of the second high voltage bipolar transistor), and its cathode connected to the base terminal. Similarly, a three terminal hybrid MOSFET/bipolar high voltage switching device can be formed by replacing the first high voltage bipolar transistor of the previous switching device by a high voltage MOSFET.

Abstract: A semiconductor device and method of manufacturing the same are provided. A device can include an LDMOS region and a high side region on a semiconductor substrate. The device can further include an insulating region separating the LDMOS region from the high side region and the insulating region can include a plurality of second conductive type wells, a plurality of second conductive type buried layer patterns, or both.

Abstract: A press pack module includes a collector module terminal, an emitter module terminal, a gate module terminal, and an auxiliary module terminal. Each IGBT cassette within the module includes a set of shims, two contact pins, and an IGBT die. The first contact pin provides part of a first electrical connection between the gate module terminal and the IGBT gate pad. The second contact pin provides part of a second electrical connection between the auxiliary module terminal and a shim that in turn contacts the IGBT emitter pad. The electrical connection between the auxiliary emitter terminal and each emitter pad of the many IGBTs is a balanced impedance network. The balanced network is not part of the high current path through the module. By supplying a gate drive signal between the gate and auxiliary emitter terminals, simultaneous IGBT turn off in high speed and high current switching conditions is facilitated.

Abstract: Apparatus and methods for monolithic data conversion interface protection are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power high supply node, a second SCR and a second diode for providing protection between the signal node and a power low supply node, and a third SCR and a third diode for providing protection between the power high supply node and the power low supply node. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. Configuring the protection device in this manner enables in-suit input/output interface protection using a single cell. The protection device is suitable for monolithic data conversion interface protection in sub 3V operation.

Abstract: In a semiconductor substrate of a semiconductor device, a drift layer, a body layer, an emitter layer, and a trench gate electrode are formed. When the semiconductor substrate is viewed in a plane manner, the semiconductor substrate is divided into a first region covered with a heat dissipation member, and a second region not covered with the heat dissipation member. A density of trench gate electrodes in the first region is equal to a density of trench gate electrodes in the second region. A value obtained by dividing an effective carrier amount of channel parts formed in the first region by an area of the first region is larger than a value obtained by dividing an effective carrier amount of channel parts formed in the second region by an area of the second region.

Abstract: A power semiconductor module includes: a circuit body having a power semiconductor element and a conductor member connected to the power semiconductor element; a case in which the circuit body is housed; and a connecting member which connects the circuit body and the case. The case includes: a first heat dissipating member and a second heat dissipating member which are disposed in opposed relation to each other while interposing the circuit body in between; a side wall which joins the first heat dissipating member and the second heat dissipating member; and an intermediate member which is formed on the periphery of the first heat dissipating member and connected to the side wall, the intermediate member including a curvature that is projected toward a housing space of the case.

Abstract: A reverse-conducting semiconductor device (RC-IGBT) including a freewheeling diode and an insulated gate bipolar transistor (IGBT), and a method for making the RC-IGBT are provided. A first layer of a first conductivity type is created on a collector side before a second layer of a second conductivity type is created on the collector side. An electrical contact in direct electrical contact with the first and second layers is created on the collector side. A shadow mask is applied on the collector side, and a third layer of the first conductivity type is created through the shadow mask. At least one electrically conductive island, which is part of a second electrical contact in the finalized RC-IGBT, is created through the shadow mask. The island is used as a mask for creating the second layer, and those parts of the third layer which are covered by the island form the second layer.

Abstract: An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

Abstract: According to an exemplary embodiment, a stacked half-bridge power module includes a high side device having a high side power terminal coupled to a high side substrate and a low side device having a low side power terminal coupled to a low side substrate. The high side and low side devices are stacked on opposite sides of a common conductive interface. The common conductive interface electrically, mechanically, and thermally couples a high side output terminal of the high side device to a low side output terminal of the low side device. The high side device and the low side device can each include an insulated-gate bipolar transistor (IGBT) in parallel with a diode.

Abstract: A semiconductor device includes a transistor having a gate electrode, a first electrode, and a second electrode and first and second protection circuits each having one end commonly connected to the gate electrode and the other end connected to the first and second electrodes, respectively. The first and second protection circuits are formed in first and second polysilicon layers, respectively, formed separately on a single field insulating film.

Abstract: There is provided a semiconductor device such that it is possible to average the temperatures of a plurality of semiconductor chips simply by providing gate resistors. The semiconductor device includes a semiconductor module wherein a plurality of circuit substrates on which are mounted one or more semiconductor chips having a gate terminal and a gate resistor connected to the gate terminal are disposed in parallel, wherein the disposition distance of the gate resistor from the semiconductor chip is set based on the temperature of the semiconductor chip.

Abstract: An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.

Abstract: An improvement is achieved in the performance of an electronic device. A first semiconductor device and a second semiconductor device are mounted over the upper surface of a wiring board such that, e.g., in plan view, the orientation of the second semiconductor device intersects the orientation of the first semiconductor device. That is, the first semiconductor device is mounted over the upper surface of the wiring board such that a first emitter terminal and a first signal terminal are arranged along an x-direction in which the pair of shorter sides of the wiring board extend. On the other hand, the second semiconductor device is mounted over the upper surface of the wiring board such that a second emitter terminal and a second signal terminal are arranged along a y-direction in which the pair of longer sides of the wiring board extend.

Abstract: In a general aspect, an apparatus can include an insulated-gate bipolar transistor device (IGBT), a gate driver circuit (driver) coupled with a gate terminal of the IGBT and a low-resistance switch device coupled between an emitter terminal of the IGBT and an electrical ground terminal, the low-resistance switch device being coupled with the electrical ground terminal via a resistor. The apparatus can also include a current sensing circuit coupled with the driver and a current sense signal line coupled with the current sensing circuit and a current sense node, the current sense node being disposed between the low-resistance switch device and the resistor. The apparatus can further include a control circuit configured, when the driver is off, to detect, based on a voltage on the current sense node, when a current through the resistor is above a threshold value and disable the IGBT in response to the detection.

Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes a channel stop region near a peripheral of the semiconductor substrate wherein the channel stop region further includes a peripheral terminal of a diode corresponding with another terminal of the diode laterally opposite from the peripheral terminal disposed on an active area of the semiconductor power device. In an embodiment of this invention, the semiconductor power device is an insulated gate bipolar transistor (IGBT).

Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

Abstract: A transistor device comprises: at least one individual transistor cell arranged in a transistor cell field on a semiconductor body, each individual transistor cell comprising a gate electrode; a gate contact, electrically coupled to the gate electrodes of the transistor cells and configured to switch on the at least one transistor cell by providing a gate current in a first direction and configured to switch off the at least one transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction; at least one gate-resistor structure monolithically integrated in the transistor device, the gate-resistor structure providing a first resistance for the gate current when the gate current flows in the first direction, and providing a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.

Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

Abstract: A semiconductor device includes an emitter electrode and a first field plate disposed on one surface of a substrate and spaced apart from each other, a collector electrode disposed on the other surface of the substrate, a trench gate disposed in the substrate, a field diffusion junction disposed in the substrate, and a first contact connecting the trench gate and the first field plate. The first field plate has a first part extending toward the emitter electrode with respect to the first contact and having a first width, and a second part extending toward the field diffusion junction with respect to the first contact and having a second width. The second width is greater than the first width.

Abstract: An IGBT includes a semiconductor portion with IGBT cells. Each IGBT cell includes a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, and a drift zone of the first conductivity type separated from the source zone by the body zone. An emitter electrode includes a main layer and an interface layer. The interface layer directly adjoins at least one of the body zone and a supplementary zone of the second conductivity type. A contact resistance between the semiconductor portion and the interface layer is higher than between the semiconductor portion and a material of the main layer. For example, the interface layer may reduce diode emitter efficiency and reverse recovery losses in IGBTs.

Abstract: This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

Abstract: The invention generally relates to a lateral power semiconductor transistor for example in integrated circuits. In particular the invention relates to Lateral Insulated Gate Bipolar Transistors or other lateral bipolar devices such as PIN diodes. The invention also generally relates to a method of increasing switching speed of a lateral bipolar power semiconductor transistor. There is provided a lateral bipolar power semiconductor transistor comprising a first floating semiconductor region of the first conductivity type located laterally spaced to an anode/drain region and a second floating semiconductor region of the second conductivity type located laterally adjacent the first floating semiconductor region, and a floating electrode placed above and in direct contact to the first and second floating semiconductor regions.

Abstract: An A-NPC circuit is configured so that the intermediate potential of two connected IGBTs is clamped by a bidirectional switch including two RB-IGBTs. Control is applied to the turn-on di/dt of the IGBTs during the reverse recovery of the RB-IGBTs. The carrier life time of an n? drift region in each RB-IGBT constituting the bidirectional switch is comparatively longer than that in a typical NPT structure device. A low life time region is also provided in the interface between the n? drift region and a p collector region, and extends between the n? drift region and the p collector region. Thus, it is possible to provide a low-loss semiconductor device, a method for manufacturing the semiconductor device and a method for controlling the semiconductor device, in which the reverse recovery loss is reduced while the reverse recovery current peak and the jump voltage peak during reverse recovery are suppressed.

Abstract: A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode.

Abstract: A semiconductor device includes a semiconductor substrate on which a diode region and an IGBT region are formed. The diode region of the semiconductor substrate includes a first conductive type specific semiconductor region that is formed in a portion of an area facing a front surface of the semiconductor substrate, a second conductive type anode region that is formed in another portion of the area facing the front surface of the semiconductor substrate and is formed along a lower side of the specific semiconductor region, and a first conductive type diode drift region that is formed on a lower side of the anode region. The specific semiconductor region is separated from the diode drift region by the anode region, and is electrically connected to the trench gate electrode.

Abstract: A semiconductor system for a current sensor in a power semiconductor includes: on a substrate, a multiple arrangement of transistor cells having an insulated gate electrode, whose emitter terminals are connected in a first region via a first conductive layer to at least one output terminal and whose emitter terminals are connected in a second region via a second conductive layer to at least one sensor terminal, which is situated outside of a first cell region boundary, which encloses the transistor cells of the first region and the second region, a trench structure belonging to the first cell region boundary being developed between the transistor cells of the second region and the sensor terminal.

Abstract: When a semiconductor substrate of a semiconductor device is viewed from above, an isolation region, an IGBT region, and a diode region are all formed adjacent to each other. A deep region that is connected to a body region and an anode region is formed in the isolation region. A drift region is formed extending across the isolation region, the IGBT region, and the diode region, inside the semiconductor substrate. A collector region that extends across the isolation region, the IGBT region and the diode region, and a cathode region positioned in the diode region, are formed in a region exposed on a lower surface of the semiconductor substrate. A boundary between the collector region and the cathode region is in the diode region, in a cross-section that cuts across a boundary between the isolation region and the diode region, and divides the isolation region and the diode region.

Abstract: In a semiconductor device including an IGBT and a freewheeling diode W?2×L1/K1/2, where K?2.5, W denotes a distance between the divided first regions, L1 denotes a thickness of the drift layer, k1 denotes a parameter that depends on structures of the insulated gate bipolar transistor and the freewheeling diode, and K denotes a value calculated by multiplying the parameter k1 by a ratio of a snapback voltage to a built-in potential between the deep well layer and the drift layer.

Abstract: A protection circuit for metal-oxide-semiconductor field-effect transistors (MOSFETs) that are used as active bypass diodes in photovoltaic solar power systems is disclosed. The protection circuit comprises, a detection circuit for detecting the start of a surge event, a switch disposed to connect the MOSFET's drain to it's gate in response to the start of the surge, a diode in series with the switch, a bistable circuit for keeping the switch closed during the surge, and a means of resetting the bistable circuit after the surge.

Abstract: In some aspects of the invention, a power semiconductor module is applied to a multi-level converter circuit with three or more levels of voltage waveform. A first IGBT, a diode whose cathode is connected to the emitter of the first IGBT, and a second IGBT having reverse blocking voltage whose emitter is connected to the emitter of the first IGBT, are housed in one package, and each of the collector of the first IGBT, the collector of the second IGBT, the connection point of the emitter of the first IGBT and the emitter of the second IGBT, and the anode of the diode, is an external terminal.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.