Abstract: A lateral insulated gate bipolar transistor (LIGBT) includes a drain-anode adjoining trenched contact penetrating through an insulating layer and extending into an epitaxial layer, directly contacting to a drain region and an anode region, and the drain region vertically contacting to the anode region along sidewall of the drain-anode adjoining trenched contact. The LIGBT further comprises a breakdown voltage enhancement doping region wrapping around the anode region. The LIGBTs in accordance with the invention offer the advantages of high breakdown voltage and low on-resistance as well as high switching speed.

Abstract: Provided is a semiconductor device including: a first gate wiring line connected to a gate electrode through an upper surface of the gate electrode that is not covered with a first interlayer insulating film; a second interlayer insulating film formed on the first interlayer insulating film so as to cover a region other than part of an upper surface of the first gate wiring line; and a second gate wiring line connected to the first gate wiring line through the upper surface of the first gate wiring line that is not covered with the second interlayer insulating film, the second gate wiring line having a width larger than a width of the first gate wiring line in plan view.

Abstract: A semiconductor component having a semiconductor body is disclosed. In one embodiment, the semiconductor component includes a drift zone of a first conductivity type, a drift control zone composed of a semiconductor material which is arranged adjacent to the drift zone at least in places, a dielectric which is arranged between the drift zone and the drift control zone at least in places. A quotient of the net dopant charge of the drift control zone, in an area adjacent to the accumulation dielectric and the drift zone, divided by the area of the dielectric arranged between the drift control zone and the drift zone is less than the breakdown charge of the semiconductor material in the drift control zone.

Abstract: A diode region and an IGBT region are formed in a semiconductor layer of a semiconductor device. A lifetime controlled region is formed in the semiconductor layer. In a plan view, the lifetime controlled region has a first lifetime controlled region located in the diode region and a second lifetime controlled region located in a part of the IGBT region. The second lifetime controlled region extends from a boundary of the diode region and the IGBT region toward the IGBT region. In the plan view, a tip of the second lifetime controlled region is located in a forming area of the body region in the IGBT region.

Abstract: A semiconductor device includes a semiconductor substrate with a first surface and a second surface. The semiconductor substrate has an element region including an IGBT region and a diode region located adjacent to the IGBT region. An IGBT element is formed in the IGBT region. A diode element is formed in the diode region. A heavily doped region of first conductivity type is located on the first surface side around the element region. An absorption region of first conductivity type is located on the second surface side around the element region. A third semiconductor region of second conductivity type is located on the second surface side around the element region.

Abstract: In a semiconductor module according to certain aspects the invention, a U-terminal and an M-terminal overlap each other in a manner to reduce inductance and to further to reduce the size of snubber capacitor. In certain aspects of the invention, a P-terminal, M-terminal, N-terminal, and U-terminal are arranged such that the U-terminal, through which currents flow in and out, is arranged farthest away from control electrodes to reduce the noises superposed to control electrodes, and the P-terminal, M-terminal, N-terminal, and U-terminal are aligned to facilitate attaching external connection bars thereto. A power semiconductor module according to aspects of the invention can facilitate reducing the wiring inductance inside and outside the module, reducing the electromagnetic noises introduced into the control terminals, and attaching the external wirings to the terminals thereof simply and easily.

Abstract: A structurally robust power switching assembly, that has a first rigid structural unit, defining a first unit major surface that is patterned to define a plurality of mutually electrically isolated, electrically conductive paths. Also, a similar, second rigid structural unit is spaced apart from the first unit major surface. Finally, a transistor is interposed between and electrically connected to the first unit major surface and the second unit major surface.

Abstract: The present invention discloses a high-voltage ESD protection device including a silicon controlled rectifier and a first PNP transistor. The silicon controlled rectifier includes a high-voltage P-well and N-well; a first N+ and P+ diffusion region are formed in the high-voltage P-well; a second N+ and P+ diffusion region are formed in the high-voltage N-well. The first PNP transistor comprises an N-type buried layer; a low-voltage N-well formed in the N-type buried layer; and a base, emitter and collector formed in the low-voltage N-well. The base and emitter are shorted together; the collector is shorted to the second N+ diffusion region and the second P+ diffusion region; the first N+ diffusion region is shorted to the first P+ diffusion region to act as a ground terminal. The high-voltage ESD protection device can effectively adjust the ESD trigger voltage and improve the snapback sustaining voltage after the device is switched on.

Abstract: The present teachings provide a semiconductor device comprising: an IGBT element region, a diode element region and a boundary region provided between the IGBT element region and the diode element region are formed in one semiconductor substrate. The boundary region comprises a second conductivity type first diffusion region, a first conductivity type second diffusion region, and a second conductivity type third diffusion region. A first drift region of the IGBT element region contiguously contacts the first diffusion region of the boundary region, and a second drift region of the diode element region contiguously contacts the first diffusion region of the boundary region. A first body region of the IGBT element region contiguously contacts the second diffusion region of the boundary region, and a second body region of the diode element region contiguously contacts the second diffusion region of the boundary region.

Abstract: A structure of power semiconductor device integrated with clamp diodes having separated gate metal pad is disclosed. The separated gate metal pads are wire bonded together on the gate lead frame. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon or gate metal.

Abstract: A semiconductor device includes a vertical IGBT and a vertical free-wheeling diode in a semiconductor substrate. A plurality of base regions is disposed at a first-surface side portion of the semiconductor substrate, and a plurality of collector regions and a plurality of cathode regions are alternately disposed in a second-surface side portion of the semiconductor substrate. The base regions include a plurality of regions where channels are provided when the vertical IGBT is in an operating state. The first-side portion of the semiconductor substrate include a plurality of IGBT regions each located between adjacent two of the channels, including one of the base regions electrically coupled with an emitter electrode, and being opposed to one of the cathode regions. The IGBT regions include a plurality of narrow regions and a plurality of wide regions.

Abstract: A semiconductor device includes a semiconductor substrate, an insulated gate transistor formed to the semiconductor substrate, a diode formed to the semiconductor substrate, and a control transistor formed to the semiconductor substrate. A first current terminal of the insulated gate transistor is coupled to a cathode of the diode at a high potential side. A second current terminal of the insulated gate transistor is coupled to an anode of the diode at a low potential side. The control transistor is configured to turn off the insulated gate transistor by reducing a potential of a gate terminal of the insulated gate transistor when the diode conducts an electric current.

Abstract: There is known a semiconductor device in which an IGBT structure is provided in an IGBT area and a diode structure is provided in a diode area, the IGBT area and the diode area are both located within a same substrate, and the IGBT area is adjacent to the diode area. In this type of semiconductor device, a phenomenon that carriers accumulated within the IGBT area flow into the diode area when the IGBT structure is turned off. In order to prevent this phenomenon, a region of shortening lifetime of carriers is provided at least in a sub-area that is within said IGBT area and adjacent to said diode area. In the sub-area, emitter of IGBT structure is omitted.

Abstract: In a semiconductor device, an IGBT cell includes a trench passing through a base layer of a semiconductor substrate to a drift layer of the semiconductor substrate, a gate insulating film on an inner surface of the trench, a gate electrode on the gate insulating film, a first conductivity-type emitter region in a surface portion of the base layer, and a second conductivity-type first contact region in the surface portion of the base layer. The IGBT cell further includes a first conductivity-type floating layer disposed within the base layer to separate the base layer into a first portion including the emitter region and the first contact region and a second portion adjacent to the drift layer, and an interlayer insulating film disposed to cover an end of the gate electrode. A diode cell includes a second conductivity-type second contact region in the surface portion of the base layer.

Abstract: A transistor component includes in a semiconductor body a source zone and a drift zone of a first conduction type, and a body zone of a second conduction type complementary to the first conduction type, the body zone arranged between the drift zone and the source zone. The transistor component further includes a source electrode in contact with the source zone and the body zone, a gate electrode adjacent the body zone and dielectrically insulated from the body zone by a gate dielectric layer, and a diode structure connected between the drift zone and the source electrode. The diode structure includes a first emitter zone adjoining the drift zone in the semiconductor body, and a second emitter zone of the first conduction type adjoining the first emitter zone. The second emitter zone is connected to the source electrode and has an emitter efficiency ? of less than 0.7.

Abstract: A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode.

Abstract: Aspects of the invention are directed to a three-level power converter that has, as one phase, a bidirectional switching element connected to the series connection point of a series circuit of a first insulated gate bi-polar transistor (“IGBT”) and second IGBT and an intermediate electrode of a direct current power supply. Also included is a fuse connected between the bidirectional switching element and the intermediate electrode of the direct current power supply, and an overcurrent shutdown unit provided in each gate drive circuit of the first and second IGBTs, are provided as protection from a power supply short circuit phenomenon occurring in the event of a short circuit failure of any of the IGBTs or diodes.

Abstract: In an NLDMOS array, the source fingers are terminated by p+ Pbody diffusions or Pbody diffusions. The drain-source spacing is reduced by arranging p+ Pbody regions for contacting the Pbody, in line with n+ source regions to define source fingers with interdigitated p+ Pbody regions.

Abstract: A semiconductor device, including a semiconductor substrate in which a diode region and an IGBT region are formed, is provided. A lifetime control region is formed within a diode drift region. The diode drift region and the IGBT drift region are a continuous region across a boundary region between the diode region and the IGBT region. A first separation region and a second separation region are formed within the boundary region. The first separation region is formed of a p-type semiconductor, formed in a range extending from an upper surface of the semiconductor substrate to a position deeper than both of a lower end of an anode region and a lower end of a body region, and bordering with the anode region. The second separation region is formed of a p-type semiconductor, formed in a range extending from the upper surface of the semiconductor substrate to a position deeper than both of the lower end of the anode region and the lower end of the body region, and bordering with the body region.

Abstract: Provided is a semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed. A separation region formed of a p-type semiconductor is formed in a range between the diode region and the IGBT region and extending from an upper surface of the semiconductor substrate to a position deeper than both a lower end of an anode region and a lower end of a body region. A diode lifetime control region is formed within a diode drift region. A carrier lifetime in the diode lifetime control region is shorter than that in the diode drift region outside the diode lifetime control region. An end of the diode lifetime control region on an IGBT region side is located right below the separation region.

Abstract: A power semiconductor module includes a plurality of sets of semiconductor switching elements, a molded resin casing containing the semiconductor switching elements, screw holders for receiving mounting screws formed at bottom regions of four corners of the molded resin casing, first terminal blocks having main circuit terminals, and arranged on a central region of a top surface of the molded resin casing, and second terminal blocks having control terminals arranged at a side edge of the molded resin casing apart. Insulating separation walls having a configuration of a rib erect from a surface of the second terminal blocks, and are interposed between groups of the control terminals corresponding to the sets of semiconductor switching elements, and between the screw holder including the mounting screw therein on the molded resin casing and the control terminal at a high voltage side adjacent to the screw holder.

Abstract: A semiconductor device provided with: an island and an island which are separated from each other; leads which approach the islands at one end; a control element which is attached to the island and is connected to a lead through a thin metal wire; and a switching element which is attached to the island and is connected to the lead through a metal wire. Further, the thin metal wire and the thin metal wire are arranged so as to the intersect.

Abstract: A method of fabricating a MOS transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming at least a gate on the semiconductor substrate; forming a protective layer on the semiconductor substrate, and the protective layer covering the surface of the gate; forming at least a recess within the semiconductor substrate adjacent to the gate; forming an epitaxial layer in the recess, wherein the top surface of the epitaxial layer is above the surface of the semiconductor substrate; and forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer, wherein a contact surface of the epitaxial layer and the spacer is above the surface of the semiconductor substrate.

Abstract: A semiconductor device includes: an insulating substrate; a first electrode pattern and a second electrode pattern provided apart from each other on a major surface of the insulating substrate; a semiconductor element connected to the first electrode pattern; an electrode terminal connected to the second electrode pattern; and a connection wiring. The connection wiring electrically connects the first electrode pattern and the second electrode pattern with each other and has a thermal resistance larger than that of the first electrode pattern.

Abstract: A semiconductor device includes a power semiconductor array including a first power semiconductor located on one end of the power semiconductor array, a second power semiconductor located on the other end and a third power semiconductor located between the first and second power semiconductors and a diode array including a first diode located on one end of the diode array, a second diode located on the other end and a third diode located between the first and second diodes. A resistance value between an emitter electrode and a collector electrode in ON state is higher at the third power semiconductor than at the first and second power semiconductors. Upon application of a voltage of not less than a rising voltage, the third diode has a higher resistance value than resistance values of the first diode and the second diode upon application of a voltage not less than a rising voltage.

Abstract: A semiconductor unit of certain aspects of the invention includes electrically conductive plates in the shape of the letter L, each consisting of a horizontally disposed leg portion and a vertically disposed flat body portion that is perpendicular to a cooling plate adhered to the bottom of the semiconductor unit. A pair of the vertically disposed flat body portions sandwiches a semiconductor chip. Owing to this construction, the heat generated in the semiconductor chip can be conducted away through the both surfaces of the chip, thus improving cooling performance. Since the heat is conducted away through the leg portions of the L-shaped electrically conductive plates a projected planar area occupied by the cooling plate required for cooling the semiconductor unit is reduced. Therefore, the size of the semiconductor unit can be reduced.

Abstract: An insulated gate bipolar transistor (IGBT) is provided comprising a semiconductor substrate having the following regions in sequence: (i) a first region of a first conductive type having opposing surfaces, a column region of a second conductive type within the first region extending from a first of said opposing surfaces; (ii) a drift region of the second conductive type; (iii) a second region of the first conductive type, and (iv) a third region of the second conductive type. There is provided a gate electrode disposed to form a channel between the third region and the drift region, a first electrode operatively connected to the second region and the third region, a second electrode operatively connected to the first region and the column region.

Abstract: A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.

Abstract: In an ultra high voltage lateral DMOS-type device (UHV LDMOS device), a central pad that defines the drain region is surrounded by a racetrack-shaped source region with striations of alternating n-type and p-type material radiating outwardly from the pad to the source to provide for an adjustable snapback voltage.

Abstract: A semiconductor power module includes at least two sub modules. The sub modules include at least one respective transistor having a collector, an emitter, and a gate. The module includes a connection arrangement having a collector terminal unit for connecting the collectors of the at least two sub modules collectively to external circuit components, at least two emitter terminal units for connecting the respective emitters of the at least two sub modules individually to external circuit components, and at least two gate terminal units for connecting the respective gates of the at least two sub modules individually to external circuit components.

Abstract: The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate. The transistor includes a collector region that is formed in a portion of the substrate. The transistor includes a base region that is surrounded by the collector region. The transistor includes an emitter region that is surrounded by the based region. The transistor includes an isolation structure that is disposed adjacent the emitter region. The transistor includes a gate structure that is disposed over a portion of the emitter region and a portion of the isolation structure.

Abstract: A reverse-conducting semiconductor device includes a freewheeling diode and an insulated gate bipolar transistor (IGBT) on a common wafer. Part of the wafer forms a base layer with a base layer thickness. The IGBT includes a collector side and an emitter side arranged on opposite sides of the wafer. A first layer of a first conductivity type and a second layer of a second conductivity type are alternately arranged on the collector side. The first layer includes at least one first region with a first region width and at least one first pilot region with a first pilot region width. The second layer includes at least one second region with a second region width and at least one second pilot region with a second pilot region width. Each second region width is equal to or larger than the base layer thickness, whereas each first region width is smaller than the base layer thickness. Each second pilot region width is larger than each first pilot region width.

Abstract: A structure of power semiconductor device integrated with clamp diodes having separated gate metal pads is disclosed. The separated gate metal pads are wire bonded together on the gate lead frame. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon or gate metal.

Abstract: A structure of power semiconductor device integrated with clamp diodes having separated gate metal pad is disclosed. The separated gate metal pads are wire bonded together on the gate lead frame. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon or gate metal.

Abstract: An internal combustion engine igniter semiconductor device is disclosed which is low cost yet secures energy withstand and reverse surge withstand capability. An IGBT includes a clamping diode between a collector electrode and a gate electrode. The IGBT has two n-type buffer layers of differing impurity concentrations between a p+ substrate and an n-type base layer of the IGBT, wherein the total thickness of the two-layer buffer layer is 50 ?m or less, and the overall impurity amount is 20×1013 cm?2 or less.

Abstract: A semiconductor device and a power converter using it wherein a switching power device and a flywheel diode are connected in series, the flywheel diode includes a region having a Schottky junction to operate as a Schottky diode and a region having a pn junction to operate as a pn diode and control operation is performed such that when current flows forwardly through the flywheel diode, the pn diode operates and when the flywheel diode recovers backwardly, the Schottky diode operates mainly.

Abstract: A MOS-gate power semiconductor device includes: a main device area including an active area and an edge termination area; and an auxiliary device area horizontally formed outside the main device area so as to include one or more diodes. Accordingly, it is possible to protect a circuit from an overcurrent and thus to prevent deterioration and/or destruction of a device due to the overcurrent.

Abstract: An improved power device with a self-aligned suicide and a method for fabricating the device are disclosed. An example power device is a vertical power device that includes contacts formed on gate and body contact regions by an at least substantially self-aligned silicidation (e.g., salicide) process. The example device may also include one or more sidewall spacers that are each at least substantially aligned between edges of the gate region and the body contact region. The body contact region may also be implanted into the device in at least substantial self-alignment to the sidewall spacer. The method may also include an at least substantially self-aligned silicon etch.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.

Abstract: A semiconductor apparatus includes a first stacked body including a first radiator plate, a first insulating layer, a first conductive layer and a first semiconductor element in this order; a second stacked body including a second radiator plate, a second insulating layer, a second conductive layer and a second semiconductor element in this order and configured to be made of a semiconductor material different from that of the first semiconductor element; and a connecting part configured to electrically connect the first conductive layer and the second conductive layer, wherein the first stacked body and the second stacked body are thermally insulated.

Abstract: A MOS-gate power semiconductor device is provided which includes: one or more P-type wells formed under one or more of a gate metal electrode and a gate bus line and electrically connected to an emitter metal electrode; and one or more N-type wells formed in the P-type well and electrically connected to one or more of the gate metal electrode and the gate bus line. According to this configuration, it is possible to suppress deterioration and/or destruction of a device due to an overcurrent.

Abstract: An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on.

Abstract: An ESD protection device structure includes a well having a first conductive type, a first doped region having a second conductive type disposed in the well, a second doped region having the first conductive type, and a third doped region having the second conductive type disposed in the well. The second doped region is disposed within the first doped region so as to form a vertical BJT, and the first doped region, the well and the third doped region forms a lateral BJT, so that pulse voltage that the ESD protection structure can tolerate can be raised.

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

Abstract: It is an object of the present invention to provide a technique to manufacture a highly reliable display device at a low cost with high yield. A display device according to the present invention includes a semiconductor layer including an impurity region of one conductivity type; a gate insulating layer, a gate electrode layer, and a wiring layer in contact with the impurity region of one conductivity type, which are provided over the semiconductor layer; a conductive layer which is formed over the gate insulating layer and in contact with the wiring layer; a first electrode layer in contact with the conductive layer; an electroluminescent layer provided over the first electrode layer; and a second electrode layer, where the wiring layer is electrically connected to the first electrode layer with the conductive layer interposed therebetween.

Abstract: A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Abstract: An integrated switching device has a switching IGFET connected between a pair of main terminals, a protector IGFET connected between the drain and gate electrodes of the switching IGFET, and a gate resistor connected between a main control terminal and the gate electrode of the switching IGFET. The protector IGFET has its gate electrode connected to the source electrode of the switching IGFET. The protector IGFET turns on in response to an application of a verse voltage to the switching IGFET thereby protecting the same from a reverse current flow.

Abstract: An IGBT is disclosed which separated into two groups (first and second IGBT portioZenerns). First and second Zener diodes each composed of series-connected Zener diode parts are disposed so as to correspond to the groups respectively. Each of the first and second Zener diodes has an anode side connected to a corresponding one of first and second polysilicon gate wirings, and a cathode side connected to an emitter electrode. Temperature dependence of a forward voltage drop of each of first and second Zener diodes is used for reducing a gate voltage of a group rising in temperature to throttle a current flowing in the group and reduce the temperature of the group to thereby attain equalization of the temperature distribution in a surface of a chip. In this manner, it is possible to provide an MOS type semiconductor device in which equalization of the temperature distribution in a surface of a chip or among chips can be attained.

Abstract: An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.

Abstract: A semiconductor system is described, which is made up of a highly n-doped silicon substrate and a first n-silicon epitaxial layer, which is directly contiguous to the highly n-doped silicon substrate, and having a p-doped SiGe layer, which is contiguous to a second n-doped silicon epitaxial layer and forms a heterojunction diode, which is situated above the first n-doped silicon epitaxial layer and in which the pn-junction is situated within the p-doped SiGe layer. The first n-silicon epitaxial layer has a higher doping concentration than the second n-silicon epitaxial layer. Situated between the two n-doped epitaxial layers is at least one p-doped emitter trough, which forms a buried emitter, a pn-junction both to the first n-doped silicon epitaxial layer and also to the second n-doped silicon epitaxial layer being formed, and the at least one emitter trough being completely enclosed by the two epitaxial layers.