Abstract: A dynamic random access memory (DRAM) and its manufacturing method are provided. The DRAM includes bit line contact structures, bit line structures, first insulating structures, a capacitor contact structure, a first connecting pad, a second insulating structure, and a capacitor structure. The bit line structure extends along a first direction. The first insulating structure extends along a second direction that intersects the first direction. The capacitor contact structure is located between two of the bit lines and two of the first insulating structures. The first connecting pad is formed on the capacitor contact structure. The second insulating structure surrounds the first connecting pad, in which the top width of the second insulating structure is greater than the bottom width thereof.

Abstract: Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.

Abstract: A method of forming cut conductive lines is provided. The method includes forming a trough in a dielectric cover layer over a plurality of electrical contacts. The method further includes filling the trough with a planarization layer, and forming a plurality of vias in the planarization layer and the dielectric cover layer, wherein each of the plurality of vias is aligned with one of the plurality of electrical contacts. The method further includes removing the planarization layer, and forming a sacrificial via plug in each of the plurality of vias in the dielectric cover layer. The method further includes forming a fill layer in the trough, and forming a planarization layer opening through the fill layer, wherein the planarization layer opening is positioned between two adjacent sacrificial via plugs. The method further includes forming a separator in the planarization layer opening.

Abstract: Embodiments are disclosed for routing a cell of a semiconductor chip, the cell being represented by a matrix, encoding first tracks of the cell as columns of the matrix and second tracks of the cell as rows of the matrix, respectively. The method includes performing a sweep operation on the matrix, the sweep operation including generating an index structure indexed by columns of the matrix, the index structure including information on candidate cut shapes that can be placed in a particular column of the matrix. Additionally, the method includes recursively placing cut shapes into the cell based on the index structure, one recursion of the placing including finding a possible cut shape and recursively placing the remaining cut shapes.

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode disposed over the semiconductor substrate and extending in a first direction, a dummy gate electrode disposed over the semiconductor substrate away from the gate electrode and extending in the first direction, a first semiconductor area of a first conductive type disposed in a surface layer portion of the semiconductor substrate between the gate electrode and the dummy gate electrode, and a conductor electrically connecting the first semiconductor area with the dummy gate electrode.

Abstract: A semiconductor structure includes a first conductive layer and a second conductive layer, and a memory device between the first conductive layer and the second conductive layer. The memory device includes a top electrode, a bottom electrode adjacent to the first conductive layer, and a phase change material between the top electrode and the bottom electrode. The bottom electrode includes a first portion and a second portion between the first portion and the first conductive layer.

Abstract: A die seal is broken in at least one place for a conductor strip formed on each conductor layer. Accordingly, no current can flow in a circular pattern around the entire perimeter of the chip. In some embodiments, an angled slot is provided in the original die seal. The angled slots may be vertically aligned. Alternatively, the slots may be vertically staggered or straight. When vertically staggered, the slots on each conductor layer are vertically offset.

Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

Abstract: A manufacturing and packaging method for a semiconductor die is provided. The method prepares a wafer which has a seal-ring region, forms a first interlayer insulating film on the wafer, forms a metal wiring in the first interlayer insulating film, forms a second interlayer insulating film on the first interlayer insulating film, forms metal pads on the second interlayer insulating film, forms a passivation layer on the metal pads, removes a portion of the passivation layer in a region adjacent to the seal-ring region to expose the second interlayer insulating film, etches a portion of the second interlayer insulating film, forms a bump on the metal pads, removes the first interlayer insulating film and the second interlayer insulating film in the region adjacent to the seal-ring region by a laser grooving process, and dices the wafer into a first semiconductor die and a second semiconductor die.

Abstract: A semiconductor integrated optical device includes: a supporting base including semi-insulating semiconductor; a first photoelectric convertor having first photodiode mesas; a second photoelectric convertor having second photodiode mesas; a first 90° optical hybrid having at least one first multimode waveguide mesa; a second 90° optical hybrid having at least one second multimode waveguide mesa; an optical divider mesa; first and second input waveguide mesas coupling the first and second 90° optical hybrids with the optical divider mesa, respectively; a conductive semiconductor region disposed on the supporting base, the conductive semiconductor region mounting the first photodiode mesas, the second photodiode mesas, the first multimode waveguide mesas, the second multimode waveguide mesas, and the optical divider mesa; a first island semiconductor mesa extending between the first and second multimode waveguide mesas; and a first groove extending through the first island semiconductor mesa and the conductive

Abstract: A pad structure with a contact via array for high bond structure is provided. In some embodiments, a semiconductor substrate comprises a pad opening. An interconnect structure is under the semiconductor substrate, and comprises an interlayer dielectric (ILD) layer, a wiring layer, and the contact via array. The wiring layer and the contact via array are in the ILD layer. Further, the contact via array borders the wiring layer and is between the wiring layer and the semiconductor substrate. A pad covers the contact via array in the pad opening, and protrudes into the ILD layer to contact the wiring layer on opposite sides of the contact via array. A method for manufacturing the pad structure, as well as an image sensor with the pad structure, are also provided.

Abstract: A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.

Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source.

Abstract: An electrostatic discharge protection device includes: a semiconductor substrate; an N-type doped well on the substrate, the N-type doped well including a first N+ region and a first P+ region; a P-type doped well on the substrate, the P-type doped well including a second N+ region, a third N+ region, and a second P+ region between the second N+ region and the third N+ region; and a first contact positioned above a surface of the N-type doped well between the first N+ region and the first P+ region.

Abstract: A semiconductor device includes an integrated circuit and a guard ring. The integrated circuit includes a first circuit and a second circuit separated from the first circuit. The guard ring is disposed around the first circuit and between the first circuit and the second circuit. The guard ring includes an outer ring, an inner ring, and two connectors. The outer ring is disposed around the first circuit and has a first gap. The inner ring is disposed between the outer ring and the first circuit and has a second gap. The two connectors connect the outer ring and the inner ring. The outer ring, the inner ring, and the two connectors form a closed loop.

Abstract: A method for fabricating self-aligned contacts includes forming a liner over a gate structure having a gate conductor and one sidewall spacer and etching an exposed gate conductor to form a recess extending less than a width of the gate conductor. A dielectric layer is conformally deposited to fill the recess between the liner and the one sidewall spacer to form a partial dielectric cap formed on the gate conductor. A self-aligned contact is formed adjacent to the one sidewall spacer of the gate structure that is electrically isolated from the gate conductor by the partial dielectric cap and the at least one sidewall spacer.

Abstract: Thermal extraction architectures for heat-generating electronic devices such as digital cameras or lights are disclosed.

Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a second substrate over a first substrate, and a cavity is formed between the first substrate and the second substrate. The method includes forming a hole through the second substrate using an etching process, and the hole is connected to the cavity. The etching process includes a plurality of etching cycles, and each of the etching cycles includes an etching step, and the etching step has a first stage and a second stage. The etching time of each of the etching steps during the second stage is gradually increased as the number of etching cycles is increased.

Abstract: A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.

Abstract: A semiconductor device includes a gate structure having a gate conductor and a sidewall spacer. A partial dielectric cap is formed on the gate conductor and extends less than a width of the gate conductor. A self-aligned contact is formed adjacent to the sidewall spacer of the gate structure and is electrically isolated from the gate conductor by the partial dielectric cap and the sidewall spacer.

Abstract: An integrated circuit device may include a front-side contact coupled to a front-side metallization. The integrated circuit device may further include a backside contact coupled to a backside metallization. The front-side contact may be directly coupled to the backside contact.

Abstract: A semiconductor module includes a plurality of semiconductor chips that include gate electrodes on front surfaces, a gate terminal that receives a control signal from outside, and a print substrate. The print substrate includes a gate wiring layer that separates the control signal that is input into the gate terminal and passes the control signal to the gate electrodes of the semiconductor chips, and a cross-sectional area of the gate wiring layer becomes larger as the gate wiring layer gets closer to the gate terminal from the gate electrodes.

Abstract: A passive tunable integrated circuit (PTIC) includes a semiconductor die (die) having a plurality of barium strontium titanate (BST) tunable capacitors. The plurality of BST tunable capacitors collectively define a capacitative area of the die. At least one electrical contact is electrically coupled with the plurality of BST tunable capacitors. A redistribution layer electrically couples the at least one electrical contact with at least one electrically conductive contact pad (contact pad). The at least one contact pad is located over the capacitative area. A bump electrically couples with the at least one contact pad and is located over the capacitative area. An electrically insulative layer couples between each contact pad of the PTIC and the plurality of BST tunable capacitors.

Abstract: A method of manufacturing a semiconductor device includes removing a first gate among a plurality of gates over a substrate. Removing the first gate exposes a first portion of an active area region under the first gate. The method further includes forming a first dielectric dummy gate over the exposed first portion of the active area region. The method further includes removing a second gate among the plurality of gates, wherein removing the second gate exposes a second portion of the active area region. The method further includes depositing a first gate electrode over the exposed second portion of the active area region.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first metal layers; and forming a plurality of second metal layers to fill the openings.

Abstract: A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.

Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

Abstract: An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact, a first polysilicon contact bridging the polysilicon and the first contact within an active region, and an output structure electrically coupled to the first polysilicon contact.

Abstract: A device uses donor circuit blocks in a donor integrated circuit to replace defective circuit blocks in a recipient integrated circuit and create a functional integrated circuit. The recipient integrated circuit has a first number of cores, the first number including a recipient core, and the recipient core having a recipient circuit block, a switching element, and a recipient communication point, the first number of cores connected by a data bus. The recipient core has an intended function. The donor integrated circuit has a second number of cores, the second number smaller than the first number. The second number includes a donor core having a donor communication point electrically connected to a donor circuit block, the donor circuit block having the intended function. The recipient connection point is electrically connected to the donor connection point and the switching element switched to disable the recipient circuit block in the recipient core.

Abstract: A nanoparticle which includes a multi-armed core and surface decoration which is attached to the core is prepared. A multi-armed core is provided by any of a number of possible routes, exemplary preferred routes being living anionic polymerization that is initiated by a reactive, functionalized anionic initiator and ?-caprolactone polymerization of a bis-MPA dendrimer. The multi-armed core is preferably functionalized on some or all arms. A coupling reaction is then employed to bond surface decoration to one or more arms of the multi-armed core. The surface decoration is a small molecule or oligomer with a degree of polymerization less than 50, a preferred decoration being a PEG oligomer with degree of polymerization between 2 and 24. The nanoparticles (particle size ?10 nm) are employed as sacrificial templating porogens to form porous dielectrics. The porogens are mixed with matrix precursors (e.g., methyl silsesquioxane resin), the matrix vitrifies, and the porogens are removed via burnout.

Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face (63) of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance.

Abstract: The present disclosure is related to a microchip apparatus, where the microchip apparatus comprises a plurality of metallic layers. Each of the metallic layers may have a respective layer thickness. The microchip apparatus also comprises electronic components integrated within the metallic layers. The electronic components may be configured to communicate data. Further, the electronic components include an antenna feed. The microchip apparatus includes an antenna coupled to the antenna feed. The antenna includes multiple loops, each loop being formed by at least one layer of the metallic layers.

Abstract: A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.

Abstract: Integration of active devices with passive components and MEMS devices is disclosed. An integrated semiconductor structure includes an active device having a device top electrode connected to a conductive jumper by a device-side via/interconnect metal stack. The integrated semiconductor structure also includes a passive component having a component bottom plate connected to the conductive jumper by a component-side via/interconnect metal stack. The component bottom plate is situated at an intermediate metal level higher than the device top electrode, and the conductive jumper is situated at a connecting metal level higher than the component bottom plate. The conductive jumper reduces undesirable charge flow into the active device during fabrication of the passive component. The passive component can be, for example, a MEMS device.

Abstract: [Problem] A TFT is manufactured using at least five photomasks in a conventional liquid crystal display device, and therefore the manufacturing cost is high. [Solving Means] By performing the formation of the pixel electrode 127, the source region 123 and the drain region 124 by using three photomasks in three photolithography steps, a liquid crystal display device prepared with a pixel TFT portion, having a reverse stagger type n-channel TFT, and a storage capacitor can be realized.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches.

Abstract: To provide a semiconductor device and a manufacturing method thereof achieving both reduction in ON resistance and increase in breakdown voltage and suppressing a short circuit. The semiconductor device has, in its semiconductor substrate having a main surface, a p? type epitaxial region, n? type epitaxial region, n type offset region, and p type body region configuring a pn junction therewith; and further has a p+ type buried region between the p? type and n? type epitaxial regions, isolation trench extending from the main surface to the p+ type buried region, and trench sidewall n type region formed on at least a portion of the sidewall of the isolation trench. The n type impurity concentration in the trench sidewall n type region is higher than that in the n? type epitaxial region. The trench sidewall n type region extends along the sidewall to reach the p+ type buried region.

Abstract: A pattern structure for a semiconductor device includes a plurality of first patterns, each of the first patterns extending in a first direction in the shape of a line, neighboring first patterns being spaced apart from each other by a gap distance, the plurality of first patterns including a plurality of trenches in parallel with the line shapes, respective trenches being between neighboring first patterns, the plurality of trenches including long trenches and short trenches alternately arranged in a second direction substantially perpendicular to the first direction, and at least a second pattern, the second pattern being coplanar with the first pattern, end portions of the first patterns being connected to the second pattern.

Abstract: An integrated circuit assembly is formed with an insulating layer, a semiconductor layer, an active device, first, second, and third electrically conductive interconnect layers, and a plurality of electrically conductive vias. The insulating layer has a first surface and a second surface. The second surface is below the first surface. A substrate layer has been removed from the second surface. The semiconductor layer has a first surface and a second surface. The first surface of the semiconductor layer contacts the first surface of the insulating layer. The active device is formed in a region of the semiconductor layer. The first electrically conductive interconnect layer forms an electrically conductive ring. The second electrically conductive interconnect layer forms a first electrically conductive plate above the electrically conductive ring and the region of the semiconductor layer.

Abstract: A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer.

Abstract: There is provided a semiconductor device. The semiconductor device may include multiple contacts plugs, an insulation layer pattern, a metal oxide layer pattern, a metal pattern and a metal line. The contact plugs contact a substrate. The insulation layer pattern is formed between the contact plugs and has a top surface lower than those of the contact plugs. The metal oxide layer pattern is formed on the insulation layer pattern, and has a dielectric constant higher than that of silicon oxide. The metal pattern is formed on the metal oxide layer pattern and contacts sidewalls of the contact plugs. The metal line contacts top surfaces of the contact plugs and the metal pattern and extends thereon.

Abstract: A monitoring testkey for a wafer is provided. The monitoring testkey includes a first metal oxide semiconductor (MOS) transistor having a channel extending in a first direction, a second MOS transistor having a channel extending in a second direction, a common gate pad electrically connected to gate electrodes of the first MOS transistor and the second MOS transistor, a first source pad electrically connected to source electrodes of the first MOS transistor and the second MOS transistor, a first drain pad electrically connected to a drain electrode of the first MOS transistor, and a second drain pad electrically connected to a drain electrode of the second MOS transistor. The monitoring testkey helps to improve the critical dimension uniformity and electrical characteristics uniformity of elements in a wafer.

Abstract: A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers.

Abstract: An iridium interfacial stack (“IrIS”) and a method for producing the same are provided. The IrIS may include ordered layers of TaSi2, platinum, iridium, and platinum, and may be placed on top of a titanium layer and a silicon carbide layer. The IrIS may prevent, reduce, or mitigate against diffusion of elements such as oxygen, platinum, and gold through at least some of its layers.

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Abstract: Techniques are described to simultaneously form an isolation trench and a handle wafer contact without additional mask steps. In one or more implementations, an isolation trench and a handle wafer contact trench are simultaneously formed in a substrate. The substrate includes an insulating layer that defines a trench bottom of the handle wafer contact trench. A handle wafer is bonded to a bottom surface of the substrate. An oxide insulating layer is deposited in the isolation trench and the handle wafer contact trench. The oxide insulating layer is then etched so that the oxide insulating layer covering the trench bottom is at least partially removed. The trench bottom is then etched so that a top surface of the handle wafer is at least partially exposed. The handle wafer contact trench may then be at least partially filled with an electrical conductive material.

Abstract: A semiconductor device includes an active layer, at least one source electrode, at least one drain electrode, at least one gate electrode, a first insulating layer, a first source pad, a first drain pad, at least one source plug, and at least one drain plug. The source electrode and the drain electrode are both disposed on the active layer. Projections of the source electrode and the drain electrode on the active layer form a source region and a drain region, respectively. The first source pad and the first drain pad are both disposed on the first insulating layer. A projection of the first source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain region is smaller than or equal to 40% of an area of the drain region.

Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

Abstract: An integrated circuit chip including a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type, and a device of protection against attacks including: between the wells, trenches with insulated walls filled with a conductive material, said trenches extending from the upper surface of the wells to the substrate; and a circuit capable of detecting a modification of the stray capacitance formed between said conductive material and a region of the chip.