Abstract: A semiconductor device includes a first insulation film having a plurality of openings which exposes predetermined regions of a semiconductor substrate, a plurality of first conductive patterns partially filling the openings and a plurality of second conductive patterns disposed on the first conductive patterns within the openings and separated from inner walls of the openings.

Abstract: One embodiment of the present invention provides a system that facilitates reducing the power needed for proximity communication. This system includes an integrated circuit with an array of transmission pads that transmit a signal using proximity communication. A layer of fill metal is located in proximity to this array of transmission pads, wherein the layer of fill metal is “floating” (e.g., not connected to any signal). Leaving this layer of fill metal floating reduces the parasitic capacitance for the array of transmission pads, which can reduce the amount of power needed to transmit the signal.

Abstract: Functionalized nanoparticles are deposited on metal lines inlaid in dielectric to form a metal cap layer that reduces electromigration in the metal line. The functionalized nanoparticles are deposited onto activated metal surfaces, then sintered and annealed to remove the functional agents leaving behind a continuous capping layer. The resulting cap layer is about 1 to 10 nm thick with 30-100% atomic of the nanoparticle material. Various semiconductor processing tools may be adapted for this deposition process without adding footprint in the semiconductor fabrication plant.

Abstract: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively. The first source region is arranged between first sides of the first and second drain regions and the second and third source regions are arranged adjacent to second sides of the first and second drain regions. A fourth source region is arranged adjacent to third sides of the first and second drain regions and a fifth source region is arranged adjacent to fourth sides of the first and second drain regions. First and second drain contacts are arranged in the first and second drain regions, respectively. At least two of the first, second, third, fourth and fifth source regions and the first and second drain regions communicate with at least two of the N plane-like metal layers.

Abstract: A semiconductor apparatus comprises a semiconductor substrate; a group of PMOS transistors formed on a predetermined portion of the semiconductor substrate; a group of NMOS transistors disposed adjacent to the group of PMOS transistors on the semiconductor substrate; a guard ring region formed between the group of PMOS transistors and the group of NMOS transistors; and a current detouring unit formed in the guard ring region and configured to discharge current produced by plasma ions towards the semiconductor substrate.

Abstract: A semiconductor chip includes: a semiconductor substrate having a plurality of electronic elements therein; a metal circuit pattern formed on the semiconductor substrate and allowing the plurality of electronic elements to be electrically connected to one another; and dummy metal patterns formed on the semiconductor substrate and the metal circuit pattern to suppress a predetermined specific frequency ranges.

Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.

Abstract: The method for producing a field effect transistor on a substrate comprising a support layer, a sacrificial layer and a semi-conducting layer comprises forming an active area in the semi-conducting layer. The active area is delineated by a closed peripheral insulation pattern and comprises an additional pattern made from insulating material. The method also comprises etching the insulating material of the additional pattern to access the sacrificial layer, etching the sacrificial layer resulting in formation of a first cavity, forming a dielectric layer on a top wall of the first cavity, and depositing an electrically conducting layer in the first cavity. The closed peripheral insulation pattern is formed through the semi-conducting layer and the sacrificial layer.

Abstract: A circuit under pad structure includes a substrate, a pad electrode, wiring layers interlayer insulation layers alternately disposed between the pad electrode and the substrate, and at least one circuit pattern integral with the substrate, disposed beneath the lowermost wiring layer and spanned by the pad electrode. The width of each wiring layer is smaller than the width of the wiring layer beneath it, i.e., closer to the substrate. The structure is fabricated such that it resists cracking, which maximizes its production yield, and possesses a minimal footprint.

Abstract: The disclosed invention provides a structure and method for providing a high lateral voltage resistance between the electrical networks, sharing a lateral plane, of conductive elements (e.g., having different high voltage potentials) comprising a coupler. In one embodiment, an integrated coupler providing a high lateral voltage resistance comprises a primary conductive element and a secondary conductive element. An isolating material is laterally configured between the electrical network of the primary conductive element and an electrical network of the secondary conductive element. The isolating material may comprise a low-k dielectric layer and prevents any lateral barrier layers (e.g., etch stop layers, diffusion barrier layers, etc.) from extending between the first conductive element and the electrical network of the second conductive element. The structure therefore provides a galvanically isolated integrated coupler which avoids electrical shorting between circuits (e.g.

Abstract: A semiconductor device capable of restricting a void growth in a copper wiring. The semiconductor device comprises a semiconductor substrate, an insulation layer formed above the semiconductor substrate, a barrier metal layer that is a first damascene wiring buried in the insulation layer, defines the bottom face and the side faces, and also defines a first hollow part at the inner side, a copper wiring layer disposed in the first hollow part and defining a second hollow part at the inner side, a first damascene wiring disposed in the second hollow part and containing an auxiliary barrier metal layer separated from the barrier metal layer, and an insulating copper diffusion preventing film disposed on the first damascene wiring and the insulation layer.

Abstract: A microelectromechanical system (MEMS) device and a method for fabricating the same are described. The MEMS device includes a first electrode and a second electrode. The first electrode is disposed on a substrate, and includes at least two metal layers, a first protection ring and a dielectric layer. The first protection ring connects two adjacent metal layers, so as to define an enclosed space between two adjacent metal layers. The dielectric layer is disposed in the enclosed space and connects two adjacent metal layers. The second electrode is disposed on the first electrode, wherein a cavity is formed between the first electrode and the second electrode.

Abstract: An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a substrate of the integrated circuit. Capacitive isolation circuitry located in conductive layers of the integrated circuit provides a high voltage isolation link between the first group of functional circuitry and a second group of functional circuitry connected to the integrated circuit through the capacitive isolation circuitry. The capacitive isolation circuitry includes a differential transmitter for transmitting data in a differential signal to the second group of functional circuitry via the capacitive isolation circuitry. A differential receiver receives data within the differential signal from the second group of functional circuitry via the capacitive isolation circuitry.

Abstract: A semiconductor component has a semiconductor body zone, a first electrically conductive layer adjacent to the semiconductor body zone, a first dielectric layer with first dielectric properties and a second dielectric layer with second dielectric properties. The first dielectric properties differ from the second dielectric properties. The first dielectric layer and the second dielectric layer are arranged between the semiconductor body zone and the first electrically conductive layer. A second electrically conductive layer is applied between the first dielectric layer and the second dielectric layer. A first voltage divider is switched between the first electrically conductive layer and the semiconductor body zone. The second electrically conductive layer is electrically conductively connected only to the voltage divider.

Abstract: Disclosed is a seal-ring architecture that can minimize noise injection from noisy digital circuits to sensitive analog and/or radio frequency (RF) circuits in system-on-a-chip (SoC) applications. In order to improve the isolation, the seal-ring structure contains cuts and ground connections to the segment which is close to the analog circuits. The cuts are such that the architecture is fully compatible with standard design rules and that the mechanical strength of the seal rings is not significantly sacrificed. Some embodiments also include a grounded p-tap ring between the analog circuits and the inner seal ring in order to improve isolation. Some embodiments also include a guard strip between the analog circuits and the digital circuits to minimize the noise injection through the substrate.

Abstract: Embodiments in accordance with the present invention provide methods of forming a metal interconnect structure which avoid defects arising from copper migration. In accordance with particular embodiments, an electroplated copper feature is subjected to a brief thermal anneal prior to chemical mechanical polishing and subsequent formation of an overlying barrier layer. This thermal anneal intentionally provokes migration of the copper and resulting formation of hillocks or voids, which are then removed by a CMP step. The barrier layer may thus subsequently be formed over a defect-free surface, which has already experienced stress release along grain boundaries as a result of the thermal treatment.

Abstract: A method for generating a layout, use of a transistor layout, and semiconductor circuit is provided that includes a matching structure, which has a number of transistors, whose structure is similar to one another, metallization levels with geometrically formed traces, which are formed directly above the transistors, and vias (in via levels), which are formed between two of the metallization levels. Whereby, within one and the same metallization level, the geometry of the traces above each transistor is formed the same.

Abstract: Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the thermally conductive substrate. Meanwhile, a semi-insulating buffer layer is interposed between the thermally conductive substrate and the light emitting cells. For example, the semi-insulating buffer layer may be formed of AlN or semi-insulating GaN. Since the thermally conductive substrate having a thermal conductivity higher than that of a sapphire substrate is employed, heat-dissipating performance can be enhanced as compared with a conventional sapphire substrate, thereby increasing the maximum light output of a light emitting device that is driven under a high voltage AC power source.

Abstract: An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk.

Abstract: A bonding pad structure in a semiconductor device includes a contact pad connected to an interconnect, a bonding pad overlying the contact pad with an intervention of an insulating film and exposed from an opening of a passivation film, and an annular contact disposed between the contact pad and the bonding pad for electric connection therebetween. The annular contact encircles the opening as viewed normal to the substrate surface.

Abstract: An integrated circuit pad structure includes a ground strip (206) positioned below a pad (101). In one example a conductive element (102) is coupled to the pad (101), and at least two tiled layers, positioned below the first conductive element (102) and positioned above the ground strip (206) are included. A conductor (203), may run beneath the ground strip (206). In a second example, a pad (101) is seated on a ground shield cage having a bottom conductive ground element (302) including several ground strips where at least one ground strip (116) is along a signal routing path. The ground shield cage further includes a set of stacked conductive ground elements, stacked to form sidewalls (209, 210) of the cage. The top conductive ground element (301) of the stacked elements has an inner perimeter and an outer perimeter, such that the inner perimeter surrounds the pad (101) and the top conductive ground element (301) is in the plane of the conductive element (102) coupled to the pad (101).

Abstract: A seal ring structure for an integrated circuit includes a seal ring being disposed along a periphery of the integrated circuit and being divided into at least a first portion and a second portion, wherein the second portion is positioned facing an analog and/or RF circuit block and is different from the first portion in structure. A P+ region is provided in a P substrate and positioned under the second portion. A shallow trench isolation (STI) structure surrounds the P+ region and laterally extends underneath a conductive rampart of the second portion.

Abstract: A structure included in a semiconductor device can include a fuse box guard ring that defines an interior region of the fuse box inside the fuse box guard ring and that defines an exterior region of the fuse box outside the fuse box guard ring. The fuse box guard ring can include protruding support members that protruding from an interior sidewall or from an exterior sidewall of the fuse box guard ring.

Abstract: A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high Ohmic region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high Ohmic region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided.

Abstract: A wafer processing method having a step of reducing the thickness of a wafer in only a device forming area where semiconductor chips are formed by grinding and etching the back side of the wafer to thereby form a recess on the back side of the wafer. At the same time, an annular projection is formed around the recess to thereby ensure the rigidity of the wafer. Accordingly, handling in shifting the wafer from the back side recess forming step to a subsequent step of forming a back side rewiring layer can be performed safely and easily.

Abstract: A monolithic substrate contains an integrated circuit comprising an amplifier having input and output, a mixer and a hybrid coupler for coupling the amplifier to the mixer. Metallic pads on the substrate are connected to each of two ports of the coupler and separate metallic pads are also connected to each of the input and output of the amplifier. The metallic pads allow the amplifier and mixer to be separately tested by a probe and the input or the output of the amplifier to be selectively connected to the mixer to enable the circuit to operate either as a receiver or transmitter. Alternatively, connections between the mixer and both input and output of the amplifier may be preformed and one of the connections subsequently severed depending on whether the circuit is to operate in receive or transmit mode.

Abstract: A semiconductor device (2) includes: a FLR (65) that is disposed on a semiconductor substrate so as to divide the semiconductor substrate into an inner region and an outer region; a first bonding pad (24a to 24d) that is disposed in the inner region and is connected to an external circuit by a wire (14a to 14d) whose one end is connected to the external circuit; and a second bonding pad (26a to 26d) that is disposed in the outer region and on which the other end of the wire is bonded.

Abstract: A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.

Abstract: Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the thermally conductive substrate. Meanwhile, a semi-insulating buffer layer is interposed between the thermally conductive substrate and the light emitting cells. For example, the semi-insulating buffer layer may be formed of AlN or semi-insulating GaN. Since the thermally conductive substrate having a thermal conductivity higher than that of a sapphire substrate is employed, heat-dissipating performance can be enhanced as compared with a conventional sapphire substrate, thereby increasing the maximum light output of a light emitting device that is driven under a high voltage AC power source.

Abstract: Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the thermally conductive substrate. Meanwhile, a semi-insulating buffer layer is interposed between the thermally conductive substrate and the light emitting cells. For example, the semi-insulating buffer layer may be formed of AlN or semi-insulating GaN. Since the thermally conductive substrate having a thermal conductivity higher than that of a sapphire substrate is employed, heat-dissipating performance can be enhanced as compared with a conventional sapphire substrate, thereby increasing the maximum light output of a light emitting device that is driven under a high voltage AC power source.

Abstract: In a semiconductor device including a semiconductor substrate and an electrode pad formed over the semiconductor substrate, at least one of test element is formed in a region of the semiconductor substrate beneath the electrode pad. The test element is electrically isolated from upper conductive layers outside of the region and the electrode pad.

Abstract: A semiconductor memory device includes a semiconductor substrate. An inter-layer dielectric is disposed on the semiconductor substrate. A bit line is disposed on the inter-layer dielectric. A bit line spacer is fabricated of a nitride layer containing boron and/or carbon and covers sidewalls of the bit line. A method of fabricating the semiconductor memory device is also provided.

Abstract: Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits include a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate layer situated over the first gate layer. The contact line includes a height that is less than a combined height of the first gate layer and the subsequent gate layer(s). The MOSFET circuits further include gate spacers situated proximate the gate layers and a single contact line spacer situated proximate the contact line. The gate spacers are taller and thicker than the contact line spacer.

Abstract: A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.

Abstract: A semiconductor device is provided that comprises a semiconductor substrate comprising an active area and a peripheral region adjacent the active area and structure positioned in the peripheral region for hindering the diffusion of mobile ions from the peripheral region into the active area.

Abstract: A low profile, 1 or 2 die design, surface mount high power microelectronic package with coefficient of expansion (CTE) matched materials such as Silicon die to Molybdenum conductor (bond pads). The CTE matching of the materials in the package enables the device to withstand repeated, extreme temperature range cycling without failing or cracking. The package can be used for transient voltage suppression (TVS), Schottky diode, rectifier diode, or high voltage diodes, among other uses. The use of a heat sink metal conductor that has a very high modulus of elasticity allows for a very thin wall plastic locking to be utilized in order to minimize the footprint of the package.

Abstract: An electronic device, including a substrate, a functional structure constituting a functional element formed on the substrate, and a cover structure forming a cavity portion in which the functional structure is disposed, is disclosed. In the electronic device, the cover structure includes a laminated structure of an interlayer insulating film and a wiring layer, the laminated structure being formed on the substrate in such a way that it surrounds the cavity portion, and the cover structure has an upside cover portion covering the cavity portion from above, the upside cover portion being formed with part of the wiring layer that is disposed above the functional structure.

Abstract: A semiconductor device comprises an integrated circuit formed on a substrate with a signal interface and at least one isolator capacitor. The integrated circuit comprises a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate, a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics, and a thick metal layer formed on the thick passivation layer. The thick passivation layer has a thickness selected to be greater than the isolation thickness whereby testing for defects is eliminated. The one or more isolator capacitors comprise the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator.

Abstract: A semiconductor device includes a layered region (104) formed in a semiconductor substrate (101) of a first conductivity type, and an electrode pad (106) formed on the semiconductor substrate with an interlayer insulating film (105) interposed therebetween and placed above the layered region. The layered region includes a first impurity diffusion region (102), a second impurity diffusion region (103) formed on the first impurity diffusion region, and a third impurity diffusion region (102x) formed on the first impurity diffusion region and surrounding a periphery of the second impurity diffusion region. a conductivity type of the first impurity diffusion region and a conductivity type of the third impurity diffusion region are a second conductivity type, and a conductivity type of the second impurity diffusion region is the first conductivity type.

Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.

Abstract: A method for forming a contact to a substrate is disclosed. The method includes providing a substrate, the substrate being doped with a first dopant; and diffusing a second dopant into at least a first side of the substrate to form a second dopant region, the first side further including a first side surface area. The method also includes forming a dielectric layer on the first side of the substrate. The method further includes forming a set of composite layer regions on the dielectric layer, wherein each composite layer region of the set of composite layer regions further includes a set of Group IV semiconductor nanoparticles and a set of metal particles. The method also includes heating the set of composite layer regions to a first temperature, wherein at least some composite layer regions of the set of composite layer regions etch through the dielectric layer and form a set of contacts with the second dopant region.

Abstract: A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.

Abstract: A method for reducing an effective lateral resistance of a buried layer in an IC includes forming first and second circuit sections in a common substrate, the second circuit section being spaced laterally from the first circuit section. The method further includes forming an isolation buried layer in the substrate under at least a portion of the first circuit section and forming a conductive layer on a surface of the substrate, the conductive layer overlaying at least a portion of the first circuit section. A plurality of conductive plugs are formed in the substrate for operatively connecting the isolation buried layer to the conductive layer, whereby an effective lateral resistance of the isolation buried layer is reduced.

Abstract: A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC.

Abstract: According to one aspect of the present invention, at least one or more of patterns required for manufacturing a display device, such as a conductive layer which forms a wiring or an electrode and a mask, is formed by a droplet discharging method. At that time, a portion of the gate insulating film where is not located under the semiconductor layer is removed during manufacturing steps of the present invention.

Abstract: A structure for preventing leakage of a semiconductor device is provided. The structure comprises a conductive layer, for shielding the features beneath thereof, located under a conductive line which crosses over a region having high voltage device. The conductive layer is wider than the conductive line.

Abstract: A shielded through-via that reduces the effect of parasitic capacitance between the through-via and surrounding wafer while providing high isolation from neighboring signals. A shield electrode is formed in the insulating region and spaced apart from the through-via. A coupling element couples at least the time-varying portion of the signal carried on the through-via to the shield electrode. This reduces the effect of any parasitic capacitance between the through-via and the shield electrode, hence the surrounding wafer.

Abstract: Nonvolatile memory devices, and methods of forming the same are disclosed. A memory device includes a substrate having a cell region, a low voltage region and a high voltage region. A ground selection transistor, a string selection transistor and a cell transistor are in the cell region, a low voltage transistor is in the low voltage region, and a high voltage transistor is in the high voltage region. A common source contact is on the ground selection transistor and a low voltage contact is on the low voltage transistor. A bit line contact is on the string selection transistor, a high voltage contact is on the high voltage transistor, and a bit line is on the bit line contact. A first insulating layer is on the substrate, and a second insulating layer is on the first insulating layer. The common source contact and the first low voltage contact extend to a height of the first insulating layer, and the bit line contact and the first high voltage contact extend to a height of the second insulating layer.

Abstract: One embodiment of the present invention provides a system that facilitates reducing the power needed for proximity communication. This system includes an integrated circuit with an array of transmission pads that transmit a signal using proximity communication. A layer of fill metal is located in proximity to this array of transmission pads, wherein the layer of fill metal is “floating” (e.g., not connected to any signal). Leaving this layer of fill metal floating reduces the parasitic capacitance for the array of transmission pads, which can reduce the amount of power needed to transmit the signal.

Abstract: A semiconductor device including: a semiconductor section in which an element is formed; an insulating layer formed on the semiconductor section; an electrode pad formed on the insulating layer; a contact section formed of a conductive material provided in a contact hole in the insulating layer and electrically connected with the electrode pad; a passivation film formed to have an opening on a first section of the electrode pad and to be positioned on a second section of the electrode pad; a bump formed to be larger than the opening in the passivation film and to be partially positioned on the passivation film; and a barrier layer which lies between the electrode pad and the bump. The contact section is connected with the second section at a position within a range in which the contact section overlaps the bump while avoiding the first section of the electrode pad.