Abstract: A method of manufacturing a crystalline silicon solar cell, subsequently including: providing a crystalline silicon substrate having a first side and a second side opposite the first side; pre-diffusing Phosphorus into a first side of the substrate to render a Phosphorus diffused layer having an initial depth; blocking the first side of the substrate; exposing a second side of the substrate to a Boron diffusion source; heating the substrate for a certain period of time and to a certain temperature so as to diffuse Boron into the second side of the substrate and to simultaneously diffuse the Phosphorus further into the substrate.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming an underlayer film that contains atoms selected from the group consisting of aluminum, boron and alkaline earth metal; and forming a silicon oxide film on the underlayer film by a CVD method or an ALD method by use of a silicon source containing at least one of an ethoxy group, a halogen group, an alkyl group and an amino group, or a silicon source of a siloxane system.

Abstract: A method of manufacturing a semiconductor device, the method including: forming a plurality of first trenches extending in one direction in at least a part of a substrate; forming a plurality of first filling layers for filling the plurality of first trenches and having protrusion portions extended from the substrate from the plurality of first trenches; forming spacers on side walls of the protrusion portions of the plurality of first filling layers so that a part of the substrate is exposed between the plurality of first filling layers; and forming a plurality of second trenches extending in parallel to the plurality of first trenches by etching the substrate exposed through the spacers.

Abstract: A semiconductor device including a buried gate is disclosed. In the semiconductor device, a bit line contact contacts a top surface and lateral surfaces of an active region, such that a contact area between a bit line contact and the active region is increased and a high-resistivity failure is prevented from occurring in a bit line contact.

Abstract: A method for amorphizing a layer on a substrate is described. In one embodiment, the method includes treating the substrate with a first gas cluster ion beam (GCIB) using a first beam energy selected to yield an amorphous sub-layer within the substrate of a desired thickness, which produces a first interfacial roughness of an amorphous-crystal interface between the amorphous sub-layer and a crystalline sub-layer of the substrate. The method further includes treating the substrate with a second GCIB using a second beam energy, less than the first beam energy, to reduce the first interfacial roughness of the amorphous-crystal interface to a second interfacial roughness.

Abstract: Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions.

Abstract: Various implementations of through silicon vias with pinched off regions are disclosed. A semiconductor substrate includes a plurality of the through silicon vias disposed in the substrate and extending from a top surface of the substrate to a bottom surface of the substrate. A conductive filler is disposed within each of the plurality of through silicon vias, each of the plurality of through silicon vias having a hollow center which reduces thermal stress in the semiconductor substrate. The plurality of through silicon vias also have pinched off regions at the bottom and/or the top portions of the through silicon vias, which prevent contamination during processing of the semiconductor substrate.

Abstract: A manufacturing method of a package carrier is provided. A substrate having an upper and lower surface is provided. A first opening communicating the upper and lower surface of the substrate is formed. A heat conducting element is disposed inside the first opening, wherein the heat conducting element is fixed in the first opening via an insulating material. At least a through hole passing through the substrate is formed. A metal layer is formed on the upper and lower surface of the substrate and inside the through hole. The metal layer covers the upper and lower surface of the substrate, the heat conducting element and the insulating material. A portion of the metal layer is removed. A solder mask is formed on the metal layer. A surface passivation layer is formed and covers the metal layer exposed by the solder mask and the metal layer located inside the through hole.

Abstract: Programmable nanotube interconnect is disclosed. In one embodiment, a method includes forming a interconnect layer using a plurality of nanotube structures, and automatically altering a route of an integrated circuit based on an electrical current applied to at least one of the plurality of nanotube structures in the interconnect layer. Neighboring interconnect layers separated by planar vias may include communication lines that are perpendicularly oriented with respect to each of the neighboring interconnect layers. The nanotube structure may be chosen from a group comprising a polymer, carbon, and a composite material. A carbon nanotube film may be patterned in a metal layer to form the plurality of nanotube structures. A sputtered planar process may be performed across a trench of electrodes to create the carbon nanotube structures.

Abstract: A passivation film is formed on a compound semiconductor layered structure, an electrode formation scheduled position for the passivation film is thinned by dry etching, a thinned portion of the passivation film is penetrated by wet etching to form an opening, and a gate electrode is formed on the passivation film so as to embed this opening by an electrode material.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: a source trace, a drain trace, and a gate trace placed on a substrate; a transistor which is placed on the drain trace and includes a source pad and a gate pad; insulating films placed between the drain and source traces and between the drain and gate traces on the substrate so as to cover sidewall surfaces of the transistor; a source spray electrode which is placed on the insulating film between the source and drain traces and connects the source pad of the transistor and the source trace; and a gate spray electrode placed on the insulating film between the gate and drain traces and connects the gate pad of the transistor and the gate trace.

Abstract: Disclosed is a manufacture method of a double layer gate electrode by patterning the photoresist layer with a half tone mask to make thicknesses of two sides of the photoresist layer are smaller than a thickness of middle of the photoresist layer and twice wet etchings thereafter to realize the manufacture of the double layer gate electrode. The present invention also relates to a manufacture method of a thin film transistor. The manufacture methods of a double layer gate electrode and a relevant thin film transistor according to the present invention employs half tone mask and twice wet etchings thereafter for manufacturing the gate electrode to solve technical problems of high manufacture cost and great manufacture difficulty of double layer gate electrodes according to prior arts.

Abstract: An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers.

Abstract: A thin film transistor array panel includes: an substrate; a gate line and a gate pad portion disposed on the substrate; a gate insulating layer disposed on the gate line and the gate pad portion; a data line and a data pad portion disposed on the gate insulating layer; a gate assistance pad portion disposed at a position corresponding to the gate pad portion; a first insulating layer disposed on the data line and removed at the gate pad portion and the data pad portion; a first field generating electrode disposed on the first insulating layer; a second insulating layer disposed on the first field generating electrode and removed at the gate pad portion and the data pad portion; and a second field generating electrode disposed on the second insulating layer. The assistance gate pad portion and the gate insulating layer include a contact hole exposing the gate pad portion.

Abstract: Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in a pad film and an underlying substrate. The method further includes protecting at least one of the plurality of isolation structures in order to preserve its height. The method further includes removing portions of unprotected isolation structures such that the unprotected isolation structures are of a different height than the at least one of the plurality isolation structures. The method further includes removing the pad film and protection over the at least one of the plurality isolation structures, wherein the at least one of the plurality of isolation structures extends above the underlying substrate. The method further includes forming at least one gate electrode on the substrate, over the remaining isolation structures and abutting sides of the at least one of the plurality of isolation structures.

Abstract: A display device includes a metal conductive layer formed on a substrate, a transparent electrode film formed on the substrate and joined to the metal conductive layer and an interlayer insulating film isolating the metal conductive layer and the transparent conductive film. The metal conductive layer has a lower aluminum layer made of aluminum or aluminum alloy, an intermediate impurity containing layer made of aluminum or aluminum alloy containing impurities and formed on a substantially entire upper surface of the lower aluminum layer and an upper aluminum layer made of aluminum or aluminum alloy and formed on the intermediate impurity containing layer. In the interlayer insulating film and the upper aluminum layer, a contact hole penetrates therethrough and locally exposes the intermediate impurity containing layer, and the transparent electrode film is joined to the metal conductive layer in the intermediate impurity containing layer exposed from the contact hole.

Abstract: Provided is a method for manufacturing a silicon carbide semiconductor device which is capable of obtaining the silicon carbide semiconductor device having a high forward current and a low reverse leakage current by a simple method. The method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a film made of a first electrode material on one surface of a silicon carbide substrate, and forming an ohmic electrode by performing heat treatment at a temperature range of 930 to 950° C.; and forming a film made of a second electrode material on the other surface of the silicon carbide substrate, and forming a Schottky electrode by performing heat treatment.

Abstract: Disclosed is a method for making a nickel film for use as an electrode of an n-p diode or solar cell. A light source is used to irradiate an n-type surface of the n-p diode or solar cell, thus producing electron-hole pairs in the n-p diode or solar cell. For the electric field effect at an n-p interface, electrons drift to and therefore accumulate on the n-type surface. With a plating agent, the diode voltage is added to the chemical potential for electroless plating of nickel on the n-type surface. The nickel film can be used as a buffer layer between a contact electrode and the diode or solar cell. The nickel film reduces the contact resistance to prevent a reduced efficiency of the diode or solar cell that would otherwise be caused by diffusion of the atoms of the electrode in following electroplating.

Abstract: A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by a monolayer or partial monolayer sequencing process such as using atomic layer deposition.

Abstract: In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.

Abstract: In high frequency circuits, the switching speed of devices is often limited by the series resistance and capacitance across the input terminals. To reduce the resistance and capacitance, the cross-section of input electrodes is made into a T-shape or inverted L-shape through lithography. The prior art method for the formation of cavities for T-gate or inverted L-gate is achieved through several steps using multiple photomasks. Often, two or even three different photoresists with different sensitivity are required. In one embodiment of the present invention, an optical lithography method for the formation of T-gate or inverted L-gate structures using only one photomask is disclosed. In another embodiment, the structure for the T-gate or inverted L-gate is formed using the same type of photoresist material.

Abstract: A method includes forming an etch stop layer over and contacting a gate electrode of a transistor, forming a sacrificial layer over the etch stop layer, and etching the sacrificial layer, the etch stop layer, and an inter-layer dielectric layer to form an opening. The opening is then filled with a metallic material. The sacrificial layer and excess portions of the metallic material over a top surface of the etch stop layer are removed using a removal step including a CMP process. The remaining portion of the metallic material forms a contact plug.

Abstract: A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate.

Abstract: A diode includes a substrate characterized by a first dislocation density and a first conductivity type, a first contact coupled to the substrate, and a masking layer having a predetermined thickness and coupled to the semiconductor substrate. The masking layer comprises a plurality of continuous sections and a plurality of openings exposing the substrate and disposed between the continuous sections. The diode also includes an epitaxial layer greater than 5 ?m thick coupled to the substrate and the masking layer. The epitaxial layer comprises a first set of regions overlying the plurality of openings and characterized by a second dislocation density and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density. The diode further includes a second contact coupled to the epitaxial layer.

Abstract: The present invention provides a composite electrode and method of manufacturing such a composite electrode, the method comprising the steps of: providing a first substrate layer with an electrically conducting surface; providing a non-conducting curable material; providing a second substrate layer which has a surface relief pattern defining at least one retaining feature corresponding to a desired metal track pattern; forming a line of contact between the conducting carrier layer and at least a part of the surface relief pattern; depositing curable material onto at least part of the surface relief pattern or the electrically conducting surface along the line of contact; advancing the line of contact and curing the curable material through the second substrate layer; releasing the cured material from the surface relief pattern feature so as to leave behind a surface relief pattern on the conducting carrier layer; depositing a first metal layer onto the exposed regions of the electrically conducting surface of

Abstract: A method of manufacturing a solar cell electrode comprising steps of: applying onto a semiconductor substrate a conductive paste comprising (i) a conductive powder, (ii) a glass frit, (iii) an organic polymer and (iv) an organic solvent comprising 30 to 85 weight percent (wt %) of 1-phenoxy-2-propanol based on the weight of the organic solvent; and firing the conductive paste.

Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes depositing a layer of a first metallic material on a semiconductor chip. The first layer has a first physical quantity. A layer of a second metallic material is deposited on the layer of the first metallic material. The second layer has a second physical quantity. The first and second layers are reflowed to form a solder structure with a desired ratio of the first metallic material to the second metallic material.

Abstract: A semiconductor device with a buried electrode is manufactured by forming a cavity within a semiconductor substrate, forming an active device region in an epitaxial layer disposed on the semiconductor substrate and forming the buried electrode below the active device region in the cavity. The buried electrode is formed from an electrically conductive material different than the material of the semiconductor substrate.

Abstract: A metal gate structure comprises a metal layer partially filling a trench of the metal gate structure. The metal layer comprises a first metal sidewall, a second metal sidewall and a metal bottom layer. By employing an uneven protection layer during an etching back process, the thickness of the first metal sidewall is less than the thickness of the metal bottom layer and the thickness of the second metal sidewall is less than the thickness of the metal bottom layer. The thin sidewalls allow extra space for subsequent metal-fill processes.

Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Abstract: A method of forming an array of recessed access device gate constructions includes using the width of an anisotropically etched sidewall spacer in forming mask openings in an etch mask for forming all recessed access device trenches within semiconductor material within all of the array. The etch mask is used while etching all of the recessed access device trenches into the semiconductor material within all of the array through the mask openings. Individual recessed access gate constructions are formed in the individual recessed access device trenches. Other methods are contemplated, including arrays of recessed access devices independent of method of manufacture.

Abstract: A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device. Each contact level comprises conductive and insulation layers. A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level. A set of N masks is used to etch the contact openings up to and including 2N contact levels. Each mask is used to etch effectively half of the contact openings. When N is 3, a first mask etches one contact level, a second mask etches two contact levels, and a third mask etches four contact levels. A dielectric layer may be formed on the sidewalls of the contact openings. Electrical conductors may be formed through the contact openings with the dielectric layers electrically insulating the electrical conductors from the sidewalls.

Abstract: A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

Abstract: The method for processing a metal layer including the following steps is illustrated. First, a semiconductor substrate is provided. Then, a metal layer is formed over the semiconductor substrate. Furthermore, a microwave energy is used to selectively heat the metal layer without affecting the underlying semiconductor substrate and other formed structures, in which the microwave energy has a predetermined frequency in accordance with a material of the metal layer, and the predetermined frequency ranges between 1 KHz to 1 MHz.

Abstract: An image sensor device includes a semiconductor substrate having a front side and a backside. A first dielectric layer is on the front side of the semiconductor substrate. A metal pad is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and on the front side of the semiconductor substrate. An opening penetrates through the semiconductor substrate from the backside of the semiconductor substrate, wherein the opening includes a first portion extending to expose a portion of the metal pad and a second portion extending to expose a portion of the second dielectric layer. A metal layer is formed in the first portion and the second portion of the opening.

Abstract: A system for forming self-aligned contacts includes electroplating a first metal contact onto a Group III-V semiconductor substrate, the first metal contact having a greater height than width and having a straight sidewall profile, etching back the semiconductor substrate down to a base layer to expose an emitter semiconductor layer under the first metal contact, conformally depositing a dielectric layer on a vertical side of the first metal contact, a vertical side of the emitter semiconductor layer and on the base layer, anisotropically etching the dielectric layer off of the semiconductor substrate to form a dielectric sidewall spacer on the vertical side of the first metal contact and providing a second metal contact immediately adjacent the dielectric sidewall spacer.

Abstract: Methods of forming a metal silicide region in an integrated circuit are provided herein. In some embodiments, a method of forming a metal silicide region in an integrated circuit includes forming a silicide-resistive region in a first region of a substrate, the substrate having the first region and a second region, wherein a mask layer is deposited atop the substrate and patterned to expose the first region; removing the mask layer after the silicide-resistive region is formed in the first region of the substrate; depositing a metal-containing layer on a first surface of the first region and a second surface of the second region; and annealing the deposited metal-containing layer to form a first metal silicide region in the second region.

Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.

Abstract: A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buri

Abstract: In one aspect of this invention, a pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode having a first portion and a second portion extending from the first portion, and formed over the scan line, the data line and the switch, where the first portion is overlapped with the switch and the second portion is overlapped with the data line, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode in the pixel area, where the first portion is overlapped with the first portion of the shielding electrode so as to define a storage capacitor therebetween and the second portion has no overlapping with the second portion of the shielding electrode.

Abstract: Embodiments disclosed herein generally relate to a process of depositing a transparent conductive oxide layer over a substrate. The transparent oxide layer is sometimes deposited onto a substrate for later use in a solar cell device. The transparent conductive oxide layer may be deposited by a “cold” sputtering process. In other words, during the sputtering process, a plasma is ignited in the processing chamber which naturally heats the substrate. No additional heat is provided to the substrate during deposition such as from the susceptor. After the transparent conductive oxide layer is deposited, the substrate may be annealed and etched, in either order, to texture the transparent conductive oxide layer. In order to tailor the shape of the texturing, different wet etch chemistries may be utilized. The different etch chemistries may be used to shape the surface of the transparent conductive oxide and the etch rate.

Abstract: A method for depositing at least one thin-film electrode onto a transparent conductive oxide film is provided. At first, the transparent conductive oxide film is deposited onto a substrate to be processed. Then, the substrate and the transparent conductive oxide film are subjected to a processing environment containing a processing gas acting as a donor material or an acceptor material with respect to the transparent conductive oxide film. The at least one thin-film electrode is deposited onto at least portions of the transparent conductive oxide film. A partial pressure of the processing gas acting as the donor material or the acceptor material with respect to the transparent conductive oxide film is varied while depositing the at least one thin-film electrode onto at least portions of the transparent conductive oxide film. Thus, a modified transparent conductive oxide film having reduced interface resistance and bulk resistance can be obtained.

Abstract: A method of manufacturing a semiconductor device includes: preparing a wafer member, the wafer member including a wafer, a conductive layer formed on a surface of the wafer and a negative photoresist formed on the conductive layer; applying a light blocking material so as to cover at least a part of an outer edge of the wafer member from an upper surface of the negative photoresist to a side surface of the negative photoresist; exposing the negative photoresist to exposure light; removing the light blocking material; and developing the negative photoresist.

Abstract: The present invention provides: a display panel substrate that has an excellent boundary surface adhesion between an insulating film and electrodes formed on the substrate, that particularly requires a configuration in which the lower electrode, the insulating film, and an upper electrode are layered on the substrate in this order from the substrate side, and that includes an auxiliary metal wiring for reducing the wiring resistance, where detachment between the lower electrode and the insulating film is sufficiently suppressed when the lower electrode must be made of ITO; a method for manufacturing such a display panel substrate; and a display panel and a display device including such a display panel substrate. A display panel substrate of the present invention has a lower electrode, an insulating film, and an upper electrode layered thereon in this order from the substrate side.

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate, an N-metal gate electrode, and a P-metal gate electrode. The substrate comprises an isolation region surrounding a P-active region and an N-active region. The N-metal gate electrode comprises a first metal composition over the N-active region. The P-metal gate electrode comprises a bulk portion over the P-active region and an endcap portion over the isolation region. The endcap portion comprises the first metal composition and the bulk portion comprises a second metal composition different from the first metal composition.

Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

Abstract: In one embodiment, a method of opening a passageway to a cavity includes providing a donor portion, forming a heating element adjacent to the donor portion, forming a first sacrificial slab abutting the donor portion, wherein the donor portion and the sacrificial slab are a shrinkable pair, forming a first cavity, a portion of the first cavity bounded by the first sacrificial slab, generating heat with the heating element, forming a first reduced volume slab from the first sacrificial slab using the generated heat and the donor portion, and forming a passageway to the first cavity by forming the first reduced volume slab.

Abstract: A semiconductor junction barrier Schottky (JBS-SKY) diode with enforced upper contact structure (EUCS) is disclosed. Referencing an X-Y-Z coordinate, the JBS-SKY diode has semiconductor substrate (SCST) parallel to X-Y plane. Active device zone (ACDZ) atop SCST and having a JBS-SKY diode with Z-direction current flow. Peripheral guarding zone (PRGZ) atop SCST and surrounding the ACDZ. The ACDZ has active lower semiconductor structure (ALSS) and enforced active upper contact structure (EUCS) atop ALSS. The EUC has top contact metal (TPCM) extending downwards and in electrical conduction with bottom of EUCS; and embedded bottom supporting structure (EBSS) inside TPCM and made of a hard material, the EBSS extending downwards till bottom of the EUCS. Upon encountering bonding force onto TPCM during packaging of the JBS-SKY diode, the EBSS enforces the EUCS against an otherwise potential micro cracking of the TPCM degrading the leakage current of the JBS-SKY diode.