Abstract: A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads.

Abstract: There are provided an evaporation mask with which an evaporated film is allowed to be formed with a fine pattern, a method of manufacturing the same, and a method of manufacturing an electronic device using such an evaporation mask. Further, there is provided an electronic device having a film-formation pattern that is precisely formed with a fine pattern. The evaporation mask including: a substrate including one or a plurality of first opening sections; and a polymer film provided on a first main surface side of the substrate, the polymer film including one or a plurality of second opening sections communicated with the respective first opening sections.

Abstract: A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILI) layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.

Abstract: A structure of the plasma treatment apparatus is employed in which an upper electrode has projected portions provided with first introduction holes and recessed portions provided with second introduction holes, the first introduction hole of the upper electrode is connected to a first cylinder filled with a gas which is not likely to be dissociated, the second introduction hole is connected to a second cylinder filled with a gas which is likely to be dissociated, the gas which is not likely to be dissociated is introduced into a reaction chamber from an introduction port of the first introduction hole provided on a surface of the projected portion of the upper electrode, and the gas which is likely to be dissociated is introduced into the reaction chamber from an introduction port of the second introduction hole provided on a surface of the recessed portion.

Abstract: In one implementation, an apparatus includes a semiconductor die, a lead, a non-conductive epoxy, and a conductive epoxy. The semiconductor die includes an upper surface and a lower surface opposite the upper surface. The lead is electrically coupled to the upper surface of the semiconductor die. The non-conductive epoxy is disposed on a first portion of the lower surface of the semiconductor die. The conductive epoxy is disposed on a second portion of the lower surface of the semiconductor die. In some implementations, a conductive wire extends from the lead to the upper surface of the semiconductor die to electrically couple the lead to the upper surface of the semiconductor die.

Abstract: A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern.

Abstract: A nonvolatile semiconductor memory includes a memory cell string having a plurality of memory cell transistors connected in series, a selection gate transistor connected in series with one end of the memory cell string, and having a gate electrode provided on a gate insulating film on a semiconductor substrate, and an element isolation insulating layer which is provided in the semiconductor substrate. The gate electrode includes a first gate electrode provided on the gate insulating film, a first and second insulating films provided on the first gate electrode, and a second gate electrode provided on the second insulating film and the element isolation insulating layer, and electrically connected to the first gate electrode. An first upper surface portion of the element isolation insulating layer below the second gate electrode is leveled with an upper surface of the first gate electrode.

Abstract: Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.

Abstract: A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate; a first metal ring surrounding the semiconductor element; an insulation film formed to cover the semiconductor element and having the first metal ring disposed therein; and a groove formed in the insulation film; wherein: the first metal ring is formed by laminating multiple metal layers in such a manner that respective outside lateral faces of the multiple metal layers are flush with each other, or that outside lateral face of each of the multiple metal layers which is positioned above an underlying metal layer is positioned more inside than outside lateral face of the underlying metal layer; and the groove has first bottom which is disposed inside the first metal ring and extending to a depth of upper surface of an uppermost metal layer of the first metal ring.

Abstract: Certain examples relate to improved methods for making patterned substantially transparent contact films, and contact films made by such methods. In certain cases, the contact films may be patterned and substantially planar. Thus, the contact films may be patterned without intentionally removing any material from the layers and/or film, such as may be required by photolithography. In certain example embodiments, an oxygen exchanging system comprising at least two layers may be deposited on a substrate, and the layers may be selectively exposed to heat and/or energy to facilitate the transfer of oxygen ions or atoms from the layer with a higher enthalpy of formation to a layer with a lower enthalpy of formation. In certain cases, the oxygen transfer may permit the conductivity of selective portions of the film to be changed. This advantageously may result in a planar contact film that is patterned with respect to conductivity and/or resistivity.

Abstract: A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins.

Abstract: A quantitative sensor and manufacture method thereof are disclosed. This quantitative sensor has a dual-mode film bulk acoustic resonator structure to achieve desirable performances in sensitivity, accuracy and efficiency. Furthermore, this quantitative sensor serves as a fluid sensor when a fluid detection metal layer is formed in a sample-receiving chamber; and this quantitative sensor may also serve as a bio sensor when biocompatible metal layer and a bio-sensing layer are formed in the sample-receiving chamber instead of the fluid detection metal layer.

Abstract: Provided is a method and apparatus for forming a silicon film, which are capable of suppressing generation of a void or seam. The method includes performing a first film-forming process, performing an etching process, performing a doping process, and performing a second film-forming process. In the first film-forming process, a non-doped silicon film that is not doped with an impurity is formed so as to embed a groove of an object. In the etching process, the non-doped silicon film formed via the first film-forming process is etched. In the doping process, the non-doped silicon film etched via the etching process is doped with an impurity. In the second film-forming process, an impurity-doped silicon film is formed so as to embed the silicon film doped via the doping process.

Abstract: An object of this invention is to provide a Schottky diode structure to increase the contact area at a Schottky junction between the Schottky Barrier metal and a semiconductor substrate. The larger contact area of the Schottky junction is, the lower of the forward voltage drop across the Schottky diode will be, thereby improving the performance and efficiency of the Schottky diode. The present invention also discloses that a plurality of trenches with adjacent top mesas can be used to form a Schottky diode with even larger contact area, wherein the trenches are built using the isolation area between two cells of MOSFET with minimum extra overhead by shrinking the dimension of pitch between two trenches.

Abstract: A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.

Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

Abstract: An anode for an organic light emitting device which introduces a metal oxide to improve flows of charges, and an organic light emitting device using the anode. The anode for the organic light emitting device has excellent charge injection characteristics, thereby improving power consumption of the organic light emitting device.

Abstract: A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer.

Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

Abstract: A method for forming small dimension openings in the organic masking layer of tri-layer lithography. The method includes forming an organic polymer layer over a semiconductor substrate; forming a silicon containing antireflective coating on the organic polymer layer; forming a patterned photoresist layer on the antireflective coating, the patterned photoresist layer having an opening therein; performing a first reactive ion etch to transfer the pattern of the opening into the antireflective coating to form a trench in the antireflective coating, the organic polymer layer exposed in a bottom of the trench; and performing a second reactive ion etch to extend the trench into the organic polymer layer, the second reactive ion etch forming a polymer layer on sidewalls of the trench, the second reactive ion etch containing a species derived from a gaseous hydrocarbon.

Abstract: A system and method for forming conductive connections is disclosed. An embodiment comprises forming conductive material on to contacts of a semiconductor substrate. The semiconductor substrate is then inverter such that the conductive material is beneath the semiconductor substrate, and the conductive material is reflowed to form a conductive bump. The reflow is performed using gravity in order to form a more uniform shape for the conductive bump.

Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium.

Abstract: The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.

Abstract: A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor.

Abstract: A method of manufacturing a semiconductor device of the present invention includes a first step of forming a metal oxide film containing at least one or more kinds of elements selected from the group consisting of hafnium, yttrium, lanthanum, aluminium, zirconium, strontium, titanium, barium, tantalum, niobium, on a substrate having a metal thin film formed on the surface, at a first temperature allowing no oxidization of the metal thin film to occur, and allowing the metal oxide film to be set in an amorphous state; and a second step of forming a metal oxide film containing at least one or more kinds of elements selected from the group consisting of hafnium, yttrium, lanthanum, aluminium, zirconium, strontium, titanium, barium, tantalum, niobium on the metal oxide film formed in the first step, up to a target film thickness, at a second temperature exceeding the first temperature.

Abstract: Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.

Abstract: A method includes forming a cavity in a substrate, depositing a layer of conductive material in the cavity and over exposed portions of the substrate, removing portions of the conductive material to expose portions of the substrate using a planarizing process, and removing residual portions of the conductive material disposed on the substrate using a reactive ion etch (RIE) process.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a gate structure, a source region, and a drain region formed thereon, and the gate structure includes a gate insulating layer and a gate electrode. The method also includes forming a first stress layer on the substrate, removing the first stress layer, and forming a second stress layer on the substrate.

Abstract: A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal.

Abstract: A semiconductor device fabrication process includes forming insulating mandrels over one or more replacement metal gates on a semiconductor substrate. The mandrels include a first insulating material. Each mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate. Mandrel spacers are formed around each insulating mandrel. The mandrel spacers include the first insulating material. Each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top. A second insulating layer of the second insulating material is formed over the transistor. Trenches to the sources and drains of the gates are formed by removing the second insulating material from portions of the transistor between the mandrels. Trench contacts to the sources and drains of the gates are formed by depositing conductive material in the first trenches.

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a semiconductor apparatus with a metallic alloy. An exemplary structure for an apparatus comprises a first silicon substrate; a second silicon substrate; and a contact connecting each of the first and second substrates, wherein the contact comprises a Ge layer adjacent to the first silicon substrate, a Cu layer adjacent to the second silicon substrate, and a metallic alloy between the Ge layer and Cu layer.

Abstract: A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.

Abstract: A lead-free paste composition contains an electrically conductive silver powder, one or more glass frits or fluxes, and a lithium compound dispersed in an organic medium. The paste is useful in forming an electrical contact on the front side of a solar cell device having an insulating layer. The lithium compound aids in establishing a low-resistance electrical contact between the front-side metallization and underlying semiconductor substrate during firing.

Abstract: A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.

Abstract: Method of applying a conformal coating to a highly structured substrate and devices made by the disclosed methods are disclosed. An example method includes the deposition of a substantially contiguous layer of a material upon a highly structured surface within a deposition process chamber. The highly structured surface may be associated with a substrate or another layer deposited on a substrate. The method includes depositing a material having an amorphous structure on the highly structured surface at a deposition pressure of equal to or less than about 3 mTorr. The method may also include removing a portion of the amorphous material deposited on selected surfaces and depositing additional amorphous material on the highly structured surface.

Abstract: Wafer-level package semiconductor devices are described that have a smallest distance between two adjacent attachment bumps smaller than about twenty-five percent (25%) of a pitch between the two adjacent attachment bumps. The smallest distance between the two adjacent attachment bumps allows for an increase in the number of attachment bumps per area without reducing the size of the bumps, which increases solder reliability. The increased solder reliability may reduce stress to the attachment bumps, particularly stress caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on.

Abstract: The present description relates to the field of microelectronic devices and the fabrication thereof, wherein through-substrate vias are utilized to route signals between microelectronic integrated circuit components, such as transistors, resistors, capacitors, inductors, and the like, within the microelectronic devices. The through-substrate vias may be used for routing critical signals, which may include, but are not limited to, timing sensitive signal, such as clock signals and the like.

Abstract: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.

Abstract: An embodiment of the present invention provides a manufacturing method of an interposer including: providing a semiconductor substrate having a first surface, a second surface and at least a through hole connecting the first surface to the second surface; electrocoating a polymer layer on the first surface, the second surface and an inner wall of the through hole; and forming a wiring layer on the electrocoating polymer layer, wherein the wiring layer extends from the first surface to the second surface via the inner wall of the through hole. Another embodiment of the present invention provides an interposer.

Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.

Abstract: A method of etching through-substrate vias comprising depositing a layer of embossable material on a first side and a second side of a thin-film stack, the thin-film stack including a base substrate, embossing the embossable material deposited on the first side and the second side of the thin-film stack with a pattern, hardening the embossable material, and etching the first and second sides of the thin-film stack, the etching of the second side of the thin-film stack forming vias through the base substrate.

Abstract: The present invention relates to a gallium nitride-based compound semiconductor device and a method of manufacturing the same. According to the present invention, there is provided a gallium nitride-based III-V group compound semiconductor device comprising a gallium nitride-based semiconductor layer and an ohmic electrode layer formed on the gallium nitride-based semiconductor layer. The ohmic electrode layer comprises a contact metal layer, a reflective metal layer, and a diffusion barrier layer.

Abstract: A semiconductor device can include a substrate and a trace layer positioned in proximity to the substrate and including a trace for supplying an electrical connection to the semiconductor device. Conductive layers can be positioned in proximity to the trace layer and form a bond pad. A non-conductive thin film layer can be positioned between the trace layer and the conductive layers. The thin film layer can include a via to enable the electrical connection from the trace to the bond pad. A portion of the trace between the substrate and the plurality of conductive layers can have a beveled edge.

Abstract: When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole.

Abstract: A method for fabricating through-silicon via structure is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a through-silicon via in the semiconductor substrate; covering a liner in the through-silicon via; performing a baking process on the liner; forming a barrier layer on the liner; and forming a through-silicon via electrode in the through-silicon via.

Abstract: The method for making a hole in a layer includes the provision of first and second adhesion areas on a surface of a support. The first area has dimensions corresponding to the dimensions of the hole. The method includes depositing a layer on the first and second adhesion areas. The material of the layer has an adhesion coefficient to the first area lower than the adhesion coefficient to the second area. The part of layer arranged above the first area is eliminated by a fluid jet.

Abstract: A semiconductor substrate having an electrode formed thereon, the electrode including at least silver and glass frit, the electrode including: a multi-layered structure with a first electrode layer joined directly to the semiconductor substrate, and an upper electrode layer formed of at least one layer and disposed on the first electrode layer. The upper electrode layer is formed by firing a conductive paste having a total silver content of 75 wt % or more and 95 wt % or less, the content of silver particles having an average particle diameter of 4 ?m or greater and 8 ?m or smaller with respect to the total silver content in the upper electrode layer being higher than that in the first electrode layer.

Abstract: In a method of forming a pattern, a plurality of first line patterns and first spacers filling spaces between the adjacent first line patterns are formed on an object layer. The first line patterns and the first spacers extend in a first direction. A plurality of second line patterns are formed on the first line patterns and the first spacers. The second line patterns extend in a second direction substantially perpendicular to the first direction. The first spacers are partially removed by a wet etching process. The object layer is etched using the first and second line patterns as an etching mask.

Abstract: A semiconductor device includes gates formed over a semiconductor substrate that are spaced apart from one another and each have a stack structure of a tunnel insulation layer, a floating gate, a dielectric layer, a first conductive layer, and a metal silicide layer, a first insulation layer formed along the sidewalls of the gates and a surface of the semiconductor substrate between the gates and configured to have a height lower than the top of the metal silicide layer; and a second insulation layer formed along surfaces of the first insulation layer and surfaces of the metal silicide layer and configured to cover an upper portion of a space between the gates, wherein an air gap is formed between the gates.

Abstract: A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability.