Abstract: A method of manufacturing a semiconductor device includes providing a transfer foil. A plurality of semiconductor chips is placed on and adhered to the transfer foil. The plurality of semiconductor chips adhered to the transfer foil is placed over a multi-device carrier. Heat is applied to laminate the transfer foil over the multi-device carrier, thereby accommodating the plurality of semiconductor chips between the laminated transfer foil and the multi-device carrier.

Abstract: A semiconductor package includes a light transmissive cover having a conductive pattern, a substrate having a cavity, a semiconductor chip in the cavity of the substrate and electrically connected to the conductive pattern arranged on the light transmissive cover, and a blocking pattern between the light transmissive cover and the substrate.

Abstract: Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.

Abstract: A semiconductor assembly includes a first substrate and a chip. The chip is coupled to and spaced apart from the substrate. Further, the chip has a first surface facing the substrate. The chip also has a warpage profile indicating stress imparted on the chip following a reflow operation. The assembly includes a back layer disposed on the chip on a second surface substantially opposite from the first surface. The back layer has a non-uniform thickness. Additionally, the thickness of the back layer on each of a plurality of elements of the chip is based on the warpage profile.

Abstract: A capacitance type gyro sensor includes a semiconductor substrate, a first electrode integrally including a first base portion and first comb tooth portions and a second electrode integrally including a second base portion and second comb tooth portions, formed by processing the surface portion of the semiconductor substrate. The first electrode has first drive portions that extend from opposed portions opposed to the respective second comb tooth portions on the first base portion toward the respective second comb tooth portions. The second electrode has second drive portions formed on the tip end portions of the respective second comb tooth portions opposed to the respective first drive portions. The first drive portions and the second drive portions engage with each other at an interval like comb teeth.

Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.

Abstract: A method of testing a device includes setting a potential of a cap terminal of the device to a first voltage, setting a potential of a self test plate of the device to a testing voltage, and detecting a first displacement of a proof mass of the device when the cap terminal is set to the first voltage and the self test plate is set to the testing voltage. The method includes setting a potential of the cap terminal of the device to a second voltage, detecting a second displacement of the proof mass of the device when the cap terminal is set to the second voltage and the self test plate is set to the testing voltage, and comparing the first displacement and the second displacement to evaluate an electrical connection between the cap terminal and a cap of the device.

Abstract: A tape capable of laser ablation may be used in the formation of microelectronic interconnects, wherein the tape may be attached to bond pads on a microelectronic device and vias may be formed by laser ablation through the tape to expose at least a portion of corresponding bond pads. The microelectronic interconnects may be formed on the bond pads within the vias, such as by solder paste printing and solder reflow. The laser ablation tape can be removed after the formation of the microelectronic interconnects.

Abstract: A semiconductor device includes a lead frame having a down bond area, a die attach area and a dam formed between the down bond area and the die attach area. A bottom of the dam is attached on a surface of the lead frame. The dam prevents contamination of the down bond area from die attach material, which may occur during a die attach process.

Abstract: A light-emitting device package including a lead frame formed of a metal and on which a light-emitting device chip is mounted; and a mold frame coupled to the lead frame by injection molding. The lead frame includes: a mounting portion on which the light-emitting device chip is mounted; and first and second connection portions that are disposed on two sides of the mounting portion in a first direction and connected to the light-emitting device chip by wire bonding, wherein the first connection portion is stepped with respect to the mounting portion, and a stepped amount is less than a material thickness of the lead frame.

Abstract: A method of silicide formation in a semiconductor fabrication process is disclosed. An active area (RX) mask is used to form an active silicon area, and is then reused to form a trench transfer (TT) area. A trench block (TB) mask is logically ANDed with the active area (RX) mask to form a trench silicide (TS) region.

Abstract: An LED package includes a package body having a well formed in its upper surface, where the well is configured to receive a light emitting chip. An optical lens is disposed above the package body and includes a hollow dome structure located above and encompassing the lateral extent of the light emitting chip within the well of the package body. In one implementation, the package body and the optical lens collectively include at least one protrusion and concave, where the protrusion is aligned with the concave so that the optical lens mates with the package body, thereby causing the optical lens to self align with the package body. In another implementation, a protruding inner portion of the upper surface of the package body mates with the hollow dome structure, achieving a similar purpose. Consequently, generation of an eccentric fault between the optical lens and the package body is prevented.

Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A heat spreader encircles the die and the interposer. A wire includes a first end bonded to one of the plurality of metal lines, and a second end bonded to the heat spreader.

Abstract: A semiconductor device comprising: a lower semiconductor package that comprises a first set of one or more semiconductor dies, an upper semiconductor package that is stacked on the lower semiconductor package, the upper semiconductor package comprises a second set of one or more semiconductor dies, and a first interconnect pad that is embedded in a top side of the lower semiconductor package to couple the upper semiconductor package to the lower semiconductor package.

Abstract: A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.

Abstract: A method of forming a MEMS device provides first and second wafers, where at least one of the first and second wafers has a two-dimensional array of MEMS devices. The method deposits a layer of first germanium onto the first wafer, and a layer of aluminum-germanium alloy onto the second wafer. To deposit the alloy, the method deposits a layer of aluminum onto the second wafer and then a layer of second germanium to the second wafer. Specifically, the layer of second germanium is deposited on the layer of aluminum. Next, the method brings the first wafer into contact with the second wafer so that the first germanium in the aluminum-germanium alloy contacts the second germanium. The wafers then are heated when the first and second germanium are in contact, and cooled to form a plurality of conductive hermetic seal rings about the plurality of the MEMS devices.

Abstract: Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.

Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof are provided in the present invention. The wafer-level package structure of a light emitting diode includes a die, a first insulating layer, at least two wires, bumps, an annular second insulating layer on the wires and the insulating layer, the annular second insulating layer surrounding an area between the bumps and there being spaces arranged between the second insulating layer and the bumps; a light reflecting cup on the second insulating layer; at least two discrete lead areas and leads in the lead areas. The technical solution of the invention reduces the area required for the substrate; and the electrodes can be extracted in the subsequent structure of the package without gold wiring to thereby further reduce the volume of the package.

Abstract: A method of forming a focal plane array by: preparing a first wafer having sensing material provided on a surface, which is covered by a sacrificial layer; preparing a second wafer including read-out integrated circuit and a contact pad, which is covered by another sacrificial layer into which are formed support legs in contact with the contact pad, the support legs being covered with a further sacrificial layer; bonding the sacrificial layers of the first and second wafers together such that the sensing material is transferred from the first wafer to the second wafer when a sacrificial bulk layer of the first wafer is removed; defining a pixel in the sensing material and forming a conductive via through the pixel for providing a connection between an uppermost surface of the pixel and the supporting legs; and removing the sacrificial layers to release the pixel, with the supporting legs underneath it.

Abstract: A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.

Abstract: A light-emitting device package having improved connection reliability of a bonding wire, heat dissipation properties, and light quality due to post-molding and a method of manufacturing the light-emitting device package. The light-emitting device package includes, for example, a wiring substrate having an opening; a light-emitting device that is disposed on the wiring substrate and covers the opening; a bonding wire electrically connecting a bottom surface of the wiring substrate to a bottom surface of the light-emitting device via the opening; a molding member that surrounds a side surface of the light-emitting device and not a top surface of the light-emitting device, which is an emission surface, is formed on a portion of a top surface of the wiring substrate, and is formed in the opening of the wiring substrate to cover the bonding wire; and a solder resist and a bump formed on the bottom surface of the wiring substrate.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent.

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.

Abstract: Disclosed is a light emitting apparatus. The light emitting apparatus includes a package body; first and second electrodes; a light emitting device electrically connected to the first and second electrodes and including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer between the first and second conductive semiconductor layers; and a lens supported on the package body and at least a part of the lens including a reflective structure. The package body includes a first cavity, one ends of the first and second electrodes are exposed in the first cavity and other ends of the first and second electrodes are exposed at lateral sides of the package body, and a second cavity is formed at a predetermined portion of the first electrode exposed in the first cavity.

Abstract: Embodiments provide a method of forming a chip package. The method may include attaching at least one chip on a carrier, the chip including a plurality of chip pads on a surface of the chip opposite to the carrier; depositing a first adhesion layer on the carrier and on the chip pads of the chip, the first adhesion layer including tin or indium; depositing a second adhesion layer on the first adhesion layer, the second adhesion layer including a silane organic material; and depositing a lamination layer or an encapsulation layer on the second adhesion layer and the chip.

Abstract: One method of making an electronic assembly includes mounting one electrical substrate on another electrical substrate with a face surface on the one substrate oriented transversely of a face surface of the other substrate. The method also includes inkjet printing on the face surfaces a conductive trace that connects an electrical contact on the one substrate with an electrical connector on the other substrate. An electronic assembly may include a first substrate having a generally flat surface with a first plurality of electrical contacts thereon; a second substrate having a generally flat surface with a second plurality of electrical contacts thereon, the surface of the second substrate extending transversely of the surface of said first substrate; and at least one continuous conductive ink trace electrically connecting at least one of the first plurality of electrical contacts with at least one of the second plurality of electrical contacts.

Abstract: The present invention provides a CMOS type semiconductor image sensor module in which the aperture ratio of the pixel is improved and at the same time chip use efficiency is attempted to be improved and furthermore, simultaneous shuttering of all the pixels is made possible, and a method of manufacturing the same. The semiconductor image sensor module of the present invention is constituted by laminating a first semiconductor chip including an image sensor in which a plurality of pixels, each constituted by a photoelectric conversion element and transistors, are arranged, and a second semiconductor chip including an A/D converter array. Preferably, a third semiconductor chip including a memory element array is further laminated. Also, a semiconductor image sensor module of the present invention is constituted by laminating a first semiconductor chip provided with the aforesaid image sensor and a fourth semiconductor chip provided with an analog type nonvolatile memory array.

Abstract: A simple and cost-effective manufacturing method for hybrid integrated components including at least one MEMS element, a cap for the micromechanical structure of the MEMS element, and at least one ASIC substrate, using which a high degree of miniaturization may be achieved. The micromechanical structure of the MEMS element and the cap are manufactured in a layered structure, proceeding from a shared semiconductor substrate, by applying at least one cap layer to a first surface of the semiconductor substrate, and by processing and structuring the semiconductor substrate proceeding from its other second surface, to produce and expose the micromechanical MEMS structure. The semiconductor substrate is then mounted with the MEMS-structured second surface on the ASIC substrate.

Abstract: The present disclosure provides the ability to produce backplanes for AMLCD and AMOLED. Specifically, each and every component of the backplanes can be printed. Depending on the resolution and screen size of the displays, backplanes can include over a million different components that must be printed that include components of the thin film transistor (TFT) and electrodes to address each of those TFTs. Even a slight misregistry of components during printing can lead to failure of one or more pixels, potentially rendering the entire display unsuitable for use. The present disclosure provides the ability to reproducibly and accurately print each and every component of the backplane for both AMLCD and AMOLED. The ability to completely print backplanes provides numerous advantages, such as reduced costs, improved throughput, more environmental friendliness, and the like.

Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.

Abstract: Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate.

Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.

Abstract: The present disclosure relates to a multi-level integrated inductor that provides for a good inductance and Q-factor. In some embodiments, the integrated inductor has a first inductive structure with a first metal layer disposed in a first spiral pattern onto a first IC die and a second inductive structure with a second metal layer disposed in a second spiral pattern onto a second IC die. The first IC die is vertically stacked onto the second IC die. A conductive interconnect structure is located vertically between the first and second IC die and electrically connects the first metal layer to the second metal layer. The conductive interconnect structure provides for a relatively large distance between the first and second inductive structures that provides for an inductance having a high Q-factor over a large range of frequencies.

Abstract: An LED manufacturing method includes following steps: providing an LED die; providing an electrode layer having a first section and a second section electrically insulated from the first section, and arranging the LED die on the second section wherein an electrically conductive material electrical connects a bottom of the LED die with second section; forming a transparent conductive layer to electrically connect a top of the LED die with the first section; providing a base and coating an outer surface of the base with a layer of electrically conductive material, defining a continuous gap in the electrically conductive material to divide the electrically conductive material into a first electrode part, and a second electrode part, arranging the electrode layer on the base so that the first section contacts the first electrode part, and the second section contacts the second electrode part.

Abstract: Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated.

Abstract: An integrated circuit package system is provided including connecting an integrated circuit die with an external interconnect, forming a first encapsulation having a device cavity with the integrated circuit die therein, mounting a device in the device cavity over the integrated circuit die, and forming a cover over the device and the first encapsulation.

Abstract: A light emitting device includes a light emitting element that emits light having a wavelength of 250 nm to 500 nm and a fluorescent layer that is disposed on the light emitting element. The fluorescent layer includes a phosphor having a composition expressed by the equation, ((M1?x1Eux1)3?ySi13?zAl3+zO2+uN21?w), and an average particle diameter of 12 ?m or more, wherein in the equation, M is an element that is selected from IA group elements, IIA group elements, IIIA group elements, IIIB group elements except Al, rare-earth elements, and IVB group elements, and x1, y, z, u, and w satisfy each of the inequalities simultaneously, that is to say each of the following inequalities is satisfied by the choice of values of the identified paramaters within the noted ranges of 0<x1<1, ?0.1<y<0.3, ?3<z?1, ?3<u?w?1.5, 2<u, w<21.

Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.

Abstract: The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.

Abstract: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.

Abstract: A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.

Abstract: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base.

Abstract: A semiconductor package includes a circuit board having an inner circuit pattern and a plurality of contact pads connected to the inner circuit pattern, at least one integrated circuit (IC) device on the circuit board and making contact with the contact pads, a mold on the circuit board, the mold fixing the IC device to the circuit board, and a surface profile modifier on a surface of the IC device and a surface of the mold, and the surface profile modifier enlarging a surface area of the IC device and the mold to dissipate heat.

Abstract: An integrated circuit package includes an integrated circuit die in a reconstituted substrate. The active side is processed then covered in molding compound while the inactive side is processed. The molding compound on the active side is then partially removed and solder balls are placed on the active side.

Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor package having a first semiconductor die, which is disposed in a first encapsulant. An opening is disposed in the first encapsulant. A second semiconductor package including a second semiconductor die is disposed in a second encapsulant. The second semiconductor package is disposed at least partially within the opening in the first encapsulant.

Abstract: An integrated circuit device including a die with a substrate with a first surface and a second surface opposite the first surface is provided. The die includes at least one circuit element positioned on the first surface. Formed on the second surface, is a wetting feature that includes an array of spaced-apart nanoscale structures and/or an array of spaced-apart microscale structures. The wetting feature also includes a wettability coating applied to at least a portion of the second surface. The integrated circuit device includes a spacer coupled to the die adjacent to the second surface. In addition, an injector plate is coupled to the spacer. The injector plate includes at least one microjet and at least one exit hole defined through the injector plate. The at least one exit hole is positioned adjacent to the at least one microjet.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip.

Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.