Capacitor Stacked Over Transfer Transis Tor (epo) Patents (Class 257/E21.648)
E Subclasses
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Patent number: 7910452Abstract: A method for fabricating a capacitor includes forming an isolation layer over a substrate. The isolation layer forms a plurality of open regions. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial layer is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer and the sacrificial layer are then removed.Type: GrantFiled: June 29, 2007Date of Patent: March 22, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae-Sung Roh, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
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Patent number: 7888718Abstract: An information storage medium in which charges and electric dipoles are coupled with one another. The information storage medium includes a substrate, an electrode layer formed on the substrate, a ferroelectric layer formed on the electrode layer, and an insulating layer formed on the ferroelectric layer. Accordingly, it is possible to stably record information on the information storage medium.Type: GrantFiled: November 24, 2004Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-hwan Jung, Seung-bum Hong, Hong-sik Park
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Patent number: 7883961Abstract: A manufacturing method for a ferroelectric memory device including: forming a lower electrode; forming an electrode oxide film composed of an oxide of a constituent material of the lower electrode; forming a first ferroelectric layer on the lower electrode by reaction between organometallic source material gas and oxygen gas; forming a second ferroelectric layer on the first ferroelectric layer by reaction between organometallic source material gas and oxygen gas; and forming an upper electrode on the second ferroelectric layer. In the method, the oxygen gas in the forming of the first ferroelectric layer is in an amount less than the amount of oxygen necessary for reaction of the organometallic source material gas. In the method, the oxygen gas in the forming of the second ferroelectric layer is in an amount greater than the amount of oxygen necessary for reaction of the organometallic source material gas.Type: GrantFiled: November 28, 2007Date of Patent: February 8, 2011Assignees: Seiko Epson Corporation, Fujitsu Semiconductor LimitedInventors: Hiroaki Tamura, Masaki Kurasawa, Hideki Yamawaki
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Patent number: 7884410Abstract: Example embodiments may provide nonvolatile memory devices and example methods of fabricating nonvolatile memory devices. Example embodiment nonvolatile memory devices may include a switching device on a substrate and/or a storage node electrically connected to the switching device. A storage node may include a lower metal layer electrically connected to the switching device, a first insulating layer, a middle metal layer, a second insulating layer, an upper metal layer, a carbon nanotube layer, and/or a passivation layer stacked on the lower metal layer.Type: GrantFiled: October 31, 2007Date of Patent: February 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-wook Moon, Joong S. Jeon, El Mostafa Bourim, Hyun-deok Yang
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Patent number: 7875515Abstract: A method for manufacturing a capacitor of a semiconductor device includes: forming an interlayer insulating film including a contact plug over a semiconductor substrate; forming a first stack film including a capacitor oxide film and a nitride film over the interlayer insulating film; etching the first stack film to form a first stack pattern and a contact hole that exposes the contact plug; forming a lower electrode in the contact hole; forming a capping oxide film continuously over the first stack pattern to form a bridge connecting the neighboring first stack patterns; forming an etching barrier film including cavities over the capping oxide film; performing a blanket etching process onto the etching barrier film including cavities until the capacitor oxide film is exposed to form a nitride film pattern; and removing the exposed capacitor oxide film.Type: GrantFiled: June 30, 2008Date of Patent: January 25, 2011Assignee: Hynix Semiconductor Inc.Inventors: Sang Man Bae, Hyoung Ryeun Kim
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Patent number: 7859081Abstract: A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.Type: GrantFiled: March 29, 2007Date of Patent: December 28, 2010Assignee: Intel CorporationInventors: Brian S. Doyle, Robert S. Chau, Suman Datta, Vivek De, Ali Keshavarzi, Dinesh Somasekhar
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Patent number: 7858486Abstract: The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node locations. Insulative material is deposited over the first material laterally about sidewalls of the projecting pillars, and is anisotropically etched effective to expose underlying first material and leave electrically insulative material received laterally about the sidewalls of the projecting pillars. Openings are formed within a second material to the pillars. The pillars are etched from the substrate through the openings in the second material, and individual capacitor electrodes are formed within the openings in electrical connection with the storage node locations. The individual capacitor electrodes have the anisotropically etched insulative material received laterally about their outer sidewalls. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other implementations and aspects are contemplated.Type: GrantFiled: April 8, 2009Date of Patent: December 28, 2010Assignee: Micron Technology, Inc.Inventor: H. Montgomery Manning
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Patent number: 7855113Abstract: A method for fabricating a semiconductor memory device includes: forming a lower conductive layer over a semiconductor substrate; forming an insulation layer over the lower conductive layer; etching the insulation layer to form a contact hole that exposes a portion of the lower conductive layer; forming a contact plug in the contact hole; doping the contact plug by performing a plasma doping process while varying a temperature of regions the semiconductor substrate; and forming an upper conductive layer connected with the lower conductive layer through the contact plug.Type: GrantFiled: June 22, 2009Date of Patent: December 21, 2010Assignee: Hynix Semiconductor Inc.Inventors: Yong Soo Joung, Seung Woo Jin, An Bae Lee, Young Hwan Joo
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Patent number: 7846809Abstract: A method for forming a capacitor of a semiconductor device includes the steps of forming first and second sacrificial insulation layers over a semiconductor substrate divided into first and second regions. The second and first sacrificial insulation layers in the first region are etched to define in the first region of the semiconductor substrate. Storage nodes on surfaces of the holes are formed. A partial thickness of the second sacrificial insulation layer is etched to partially expose upper portions of the storage nodes. A mask pattern is formed to cover the first region while exposing the second sacrificial insulation layer remaining in the second region. The exposed second sacrificial insulation layer in the second region is removed to expose the first sacrificial insulation layer in the second region. The exposed first sacrificial insulation layer in the second region and the first sacrificial insulation layer in the first region is removed. The mask pattern is removed.Type: GrantFiled: December 28, 2007Date of Patent: December 7, 2010Assignee: Hynix Semiconductor Inc.Inventor: Gyu Hyun Kim
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Publication number: 20100297820Abstract: An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed.Type: ApplicationFiled: August 4, 2010Publication date: November 25, 2010Inventors: Se-young LEE, IL-young YOON, Boung-ju LEE
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Publication number: 20100273303Abstract: A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays.Type: ApplicationFiled: July 1, 2010Publication date: October 28, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Gordon A. Haller, Sanh D. Tang
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Patent number: 7820508Abstract: A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.Type: GrantFiled: November 6, 2006Date of Patent: October 26, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Min Oh, Jeong-Nam Han, Chang-Ki Hong, Woo-Gwan Shim, Im-Soo Park
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Patent number: 7816204Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: GrantFiled: May 23, 2008Date of Patent: October 19, 2010Assignee: Renesas Technology Corp.Inventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
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Patent number: 7811882Abstract: A method of manufacturing a semiconductor device. The method comprises fabricating a ferroelectric capacitor. The capacitor's fabrication includes forming conductive and ferroelectric material layers on a semiconductor substrate, forming a hardmask layer on the conductive and ferroelectric material layers, forming an organic bottom antireflective coating layer on the hardmask layer, and, patterning the organic bottom antireflective coating layer. Seasoning in a hardmask etching chamber is substantially unaffected by the patterning.Type: GrantFiled: January 13, 2009Date of Patent: October 12, 2010Assignee: Texas Instruments IncorporatedInventor: Francis Gabriel Celii
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Patent number: 7807542Abstract: A highly reliable semiconductor device and a method fabricating the same are provided, the semiconductor device having a low resistance electrode structure. The semiconductor device includes an interlayer insulation film formed on a semiconductor substrate. A storage node electrode is formed on the interlayer insulation film. A protection film is formed on the storage node electrode and includes a nitrided metal film. A dielectric film overlies the protection film. A plate electrode is formed on the dielectric film.Type: GrantFiled: November 21, 2006Date of Patent: October 5, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-Byoung Yoon, Jin-Sung Kim, Kyung-Woo Lee, Yeong-Cheol Lee, Sang-Jun Park, Hye-Sun Kim
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Publication number: 20100237396Abstract: Some embodiments include methods of forming capacitors. A first capacitor storage node may be formed within a first opening in a first sacrificial material. A second sacrificial material may be formed over the first capacitor storage node and over the first sacrificial material, and a retaining structure may be formed over the second sacrificial material. A second opening may be formed through the retaining structure and the second sacrificial material, and a second capacitor storage node may be formed within the second opening and against the first storage node. The first and second sacrificial materials may be removed, and then capacitor dielectric material may be formed along the first and second storage nodes. Capacitor electrode material may then be formed along the capacitor dielectric material. Some embodiments include methods of forming DRAM unit cells, and some embodiments include DRAM unit cell constructions.Type: ApplicationFiled: March 23, 2009Publication date: September 23, 2010Inventor: John Kennedy
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Patent number: 7799633Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device, for example, a semiconductor device using carbon nanotubes or nanowires as lower electrodes of a capacitor, and a method of manufacturing the semiconductor device. The semiconductor device may include a lower electrode including a plurality of tubes or wires on a semiconductor substrate, a dielectric layer on the surface of the lower electrode, and an upper electrode on the surface of the dielectric layer, wherein the plurality of tubes or wires radiate outwardly from each other centering on the lower portion of the plurality of tubes or wires. Thus, the off current of the capacitor may be increased by increasing the surface area of the lower electrodes of the capacitor.Type: GrantFiled: October 31, 2007Date of Patent: September 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Young-moon Choi, Ji-young Kim, In-seok Yeo, Sun-woo Lee
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Patent number: 7795648Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: GrantFiled: February 10, 2009Date of Patent: September 14, 2010Assignee: Renesas Technology CorporationInventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
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Patent number: 7786523Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.Type: GrantFiled: November 16, 2009Date of Patent: August 31, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yumi Hayashi, Hayato Nasu, Kazumichi Tsumura, Takamasa Usui, Hiroyoshi Tanimoto
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Patent number: 7786521Abstract: A semiconductor device with a dielectric structure and a method for fabricating the same are provided. A capacitor in the semiconductor device includes: a bottom electrode formed on a substrate; a first dielectric layer made of titanium dioxide (TiO2) in rutile phase and formed on the bottom electrode; and an upper electrode formed on the first dielectric layer.Type: GrantFiled: January 26, 2009Date of Patent: August 31, 2010Assignee: Hynix Semiconductor Inc.Inventors: Ki-Seon Park, Jae-Sung Roh
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Patent number: 7781298Abstract: A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to form a patterned second mask layer in a predetermined region for formation of a capacitor. A plurality of hemispherical grain structures are formed on a sidewall of the patterned second mask layer. The first mask layer is etched by using the hemispherical grain structures and the patterned second mask layer as a mask, thereby forming a patterned first mask layer having a pattern. The pattern of the first mask layer is transferred to the bottom electrode material layer. And, a capacitor dielectric layer and a top electrode layer are formed on the bottom electrode material layer to form the capacitor.Type: GrantFiled: July 3, 2008Date of Patent: August 24, 2010Assignee: Industrial Technology Research InstituteInventors: Hengyuan Lee, Lurng-Shehng Lee, Ching Chiun Wang, Pei-Jer Tzeng
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Patent number: 7776685Abstract: The invention is directed to particular polymer compositions that may be generally characterized by the formula: wherein the variables L, M and N represent the relative molar fractions of the monomers and satisfy the expressions 0<L?0.8; 0<M?0.2; 0<L?0.35; and L+M+N=1; and, wherein R1, R2 and R3 are independently selected from C1-C6 alkyls and derivatives thereof. The invention is also directed to polymer compositions that, when used to form a buffer layer or pattern, can be more easily removed from the surface of a semiconductor substrate, thereby increasing productivity and/or reducing the likelihood of defects and failures associated with residual photoresist material.Type: GrantFiled: February 19, 2009Date of Patent: August 17, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Yul Ahn, Kyong-Rim Kang, Tae-Sung Kim, Young-Ho Kim, Jung-Hoon Lee
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Patent number: 7754562Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: GrantFiled: February 10, 2009Date of Patent: July 13, 2010Assignee: Renesas Technology Corp.Inventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
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Patent number: 7749834Abstract: A method includes forming a lower dielectric layer on a semiconductor substrate, forming a bit line landing pad and a storage landing pad that penetrate the lower dielectric layer, covering the lower dielectric layer, the bit line landing pad, and the storage landing pad with an intermediate dielectric layer, forming an upper dielectric layer on the intermediate dielectric layer, partially removing the upper dielectric layer and the intermediate dielectric layer to form a contact opening that exposes the storage landing pad and a portion of the lower dielectric layer, forming a contact spacer on an inner wall of the contact opening, and filling the contact opening with a contact plug, a top surface of the contact plug larger than a surface of the contact plug that is in contact with the storage landing pad, the top surface of the contact plug eccentric in relation to the storage landing pad.Type: GrantFiled: February 27, 2006Date of Patent: July 6, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Je-Min Park, Yoo-Sang Hwang, Seok-Soon Song
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Patent number: 7737506Abstract: An objective is to provide a method of manufacturing a semiconductor device, and a semiconductor device manufactured by using the manufacturing method, in which a laser crystallization method is used that is capable of preventing the formation of grain boundaries in TFT channel formation regions, and is capable of preventing conspicuous drops in TFT mobility, reduction in the ON current, and increases in the OFF current, all due to grain boundaries. Depressions and projections with stripe shape or rectangular shape are formed. Continuous wave laser light is then irradiated to a semiconductor film formed on an insulating film along the depressions and projections with stripe shape of the insulating film, or along a longitudinal axis direction or a transverse axis direction of the rectangular shape. Note that although it is most preferable to use continuous wave laser light at this point, pulse wave laser light may also be used.Type: GrantFiled: August 31, 2006Date of Patent: June 15, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Shunpei Yamazaki, Chiho Kokubo, Koichiro Tanaka, Akihisa Shimomura, Tatsuya Arao, Hidekazu Miyairi, Mai Akiba
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Patent number: 7728376Abstract: HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.Type: GrantFiled: March 21, 2007Date of Patent: June 1, 2010Assignee: Hitachi, Ltd.Inventors: Yuichi Matsui, Hiroshi Miki
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Patent number: 7723202Abstract: A method for forming a semiconductor device includes a plurality of crown-type capacitors in a capacitor-receiving insulating film, wherein bottom electrodes of the capacitors have an insulating spacer between each two of the bottom electrodes. The insulating spacer is formed by removing a hard mask used as an etching mask for forming cylindrical holes receiving therein capacitors including the bottom electrodes.Type: GrantFiled: July 6, 2007Date of Patent: May 25, 2010Assignee: Elpida Memory, Inc.Inventor: Toyonori Eto
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Patent number: 7713774Abstract: Embodiments relate to a method of manufacturing an image sensor which may include forming a gate pattern including a tunnel oxide film, an oxide-nitride-oxide (ONO) film, a floating gate and a control gate over a semiconductor substrate. An oxide film and a nitride film may be formed over the semiconductor substrate including the gate pattern. A photoresist pattern may be formed which covers the oxide film and the nitride film formed over the gate pattern. The nitride film may be etched in a region not covered by the photoresist pattern. The oxide film may be etched to have a predetermined thickness. A deep implant process may deeply implant an N-type dopant into the semiconductor substrate. Ashing and cleaning processes may remove the remaining photoresist pattern.Type: GrantFiled: August 30, 2007Date of Patent: May 11, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Joo-Hyeon Lee
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Patent number: 7709319Abstract: Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semiconductor substrate. Capacitors are formed in the cell area, a mold pattern is provided in the peripheral areas and an elongated dummy pattern is provided in the boundary areas. The dummy pattern includes a boundary opening in which a thin layer is formed on the elongated inner sidewalls and on the exposed portion of the substrate during formation of the lower electrode. A mold pattern and lower electrode structures having substantially the same height are then formed area so that subsequent insulation interlayer(s) exhibit a generally planar surface, i.e., have no significant step difference between the cell areas and the peripheral areas.Type: GrantFiled: June 12, 2006Date of Patent: May 4, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yeol Jon, Chung-Ki Min, Yong-Sun Ko, Kyung-Hyun Kim
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Patent number: 7696040Abstract: A semiconductor fin memory structure and a method for fabricating the semiconductor fin memory structure include a semiconductor fin-channel within a finFET structure that is contiguous with and thinner than a conductor fin-capacitor node within a fin-capacitor structure that is integrated with the finFET structure. A single semiconductor layer may be appropriately processed to provide the semiconductor fin-channel within the finFET structure that is contiguous with and thinner than the conductor fin-capacitor node within the fin-capacitor structure.Type: GrantFiled: May 30, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventor: Huilong Zhu
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Patent number: 7691699Abstract: Disclosed herein is a transistor for a semiconductor device and a method of forming the same. According to the present invention, a recess channel region is formed on a cell region to increase a channel length and a fin-type channel region is simultaneously formed on a peripheral circuit region to increase a channel area so as to simplify process steps, thereby improving the yield and productivity for manufacturing a semiconductor device.Type: GrantFiled: December 30, 2005Date of Patent: April 6, 2010Assignee: Hynix Semiconductor Inc.Inventors: Sung Woong Chung, Sang Don Lee
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Publication number: 20100081242Abstract: Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O2 and one or more fluorocarbons. The openings formed in the silicon oxide-containing material may be utilized for fabrication of container capacitors, and such capacitors may be incorporated into DRAM.Type: ApplicationFiled: December 4, 2009Publication date: April 1, 2010Applicant: MICRON TECHNOLOGY, INC.Inventor: Russell A. Benson
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Patent number: 7670903Abstract: A method for fabricating a cylindrical capacitor. The method includes forming an isolation structure including an interlayer on a substrate, the substrate having a plurality of contact plugs formed therein, forming a plurality of opening regions by etching the isolation structure, thereby exposing selected portions of the contact plugs, forming storage nodes on a surface of the opening regions, etching selected portions of the isolation structure to form a patterned interlayer that encompasses selected portions of the storage nodes, thereby supporting the storage nodes, removing remaining portions of the isolation structure, and removing the patterned interlayer to expose inner and outer walls of the storage nodes.Type: GrantFiled: December 28, 2006Date of Patent: March 2, 2010Assignee: Hynix Semiconductor, Inc.Inventors: Ki-Seon Park, Jae-Sung Roh, Deok-Sin Kil, Han-Sang Song, Seung-Jin Yeom, Jin-Hyock Kim, Kee-Jeung Lee
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Patent number: 7666737Abstract: A method of forming a metal-insulator-metal capacitor has the following steps. A stack dielectric structure is formed by alternately depositing a plurality of second dielectric layers and a plurality of third dielectric layers. A wet etch selectivity of the second dielectric layer relative to said third dielectric layer is of at least 5:1. An opening is formed in the stack dielectric structure, and then a wet etch process is employed to remove relatively-large portions of the second dielectric layers and relatively-small portions of the third dielectric layers to form a plurality of lateral recesses in the second dielectric layers along sidewalls of the opening. A bottom electrode layer is formed to extend along the serrate sidewalls, a capacitor dielectric layer is formed on the bottom electrode layer, and a top electrode layer is formed on the capacitor dielectric layer.Type: GrantFiled: December 18, 2006Date of Patent: February 23, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Kuo-Chi Tu
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Patent number: 7663179Abstract: A semiconductor device having a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, the transistors each including a gate insulating film formed over a semiconductor substrate, a gate electrode over the gate insulating film and sidewall spacers over the sidewalls of the corresponding gate electrode. Sidewall spacers of the first field effect transistor are different from those of at least the second field effect transistors. Also, the gate insulating film of the third field effect transistor has a thickness larger than that of the second field effect transistor and the gate electrode of the third field effect transistor has a length different from that of either the first field effect transistor or second field effect transistor.Type: GrantFiled: May 31, 2006Date of Patent: February 16, 2010Assignee: Renesas Technology Corp.Inventors: Masaaki Shinohara, Kozo Watanabe, Fukuo Owada, Takashi Aoyama
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Patent number: 7655519Abstract: A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.Type: GrantFiled: September 1, 2005Date of Patent: February 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-ae Chung, Jae-hyoung Choi, Jung-hee Chung, Young-sun Kim, Cha-young Yoo
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Patent number: 7651907Abstract: A method for fabricating a semiconductor device, the method includes forming an etch stop layer and an insulation layer over a substrate having a first region and a second region, selectively removing the insulation layer and the etch stop layer in the first region to expose parts of the substrate, thereby forming at least two electrode regions on the exposed substrate and a resultant structure, forming a conductive layer over the resultant structure, removing the conductive layer in the second region, removing the insulation layer in the first region and the second region by using wet chemicals, and removing parts of the conductive layer, which formed between the at least two electrode regions in the first region, to form cylinder type electrodes in the first region.Type: GrantFiled: December 26, 2007Date of Patent: January 26, 2010Assignee: Hynix Semiconductor Inc.Inventor: Jun-Hee Cho
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Patent number: 7651908Abstract: A method of fabricating an image sensor which reduces fabricating costs through simultaneous formation of capacitor structures and contact structures may be provided. The method may include forming a lower electrode on a substrate, forming an interlayer insulating film on the substrate, the interlayer insulating film may have a capacitor hole to expose a first portion of the lower electrode.Type: GrantFiled: February 15, 2007Date of Patent: January 26, 2010Assignee: Samsung Electronic Co., Ltd.Inventors: Gil-Sang Yoo, Byung-Jun Park
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Patent number: 7646052Abstract: A semiconductor device in which a DRAM and a SRAM are mixedly mounted is provided. The DRAM and the SRAM have a stack-type structure in which a bitline is formed below a capacitive element. A cross couple connection of the SRAM is formed in a layer or below the layer in which a capacitive lower electrode of the DRAM is formed and in a layer or above the layer in which the bitline is formed. For example, the cross couple connection of the SRAM is formed in a same layer as a capacitive contact.Type: GrantFiled: October 4, 2007Date of Patent: January 12, 2010Assignee: NEC Electronics CorporationInventors: Takami Nagata, Masaru Ushiroda
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Patent number: 7645675Abstract: A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.Type: GrantFiled: January 13, 2006Date of Patent: January 12, 2010Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Hanyi Ding, Ebenezer E. Eshun, Michael D. Gordon, Zhong-Xiang He, Anthony K. Stamper
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Patent number: 7638407Abstract: Forming a capacitor of a semiconductor device includes forming an interlayer dielectric having holes over a semiconductor substrate. A conductive layer is then formed on surfaces of the holes and on the upper surface of the interlayer dielectric. A silicon-containing conductive layer is formed by flowing a silicon source gas for the semiconductor substrate formed with the conductive layer, so that silicon atoms can penetrate into the conductive layer. The silicon-containing conductive layer prevents etchant from infiltrating the interlayer dielectric below the silicon-containing conductive layer.Type: GrantFiled: November 6, 2008Date of Patent: December 29, 2009Assignee: Hynix Semiconductor Inc.Inventors: Cheol Hwan Park, Ho Jin Cho, Jae Soo Kim, Dong Kyun Lee
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Patent number: 7638401Abstract: A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The array gates 58a and the first conductivity type peripheral gates 58n are masked such that the second conductivity type peripheral gates 58p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58p, while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58p. The second conductivity type peripheral gates 58p are then masked such that the first conductivity type peripheral gates 58n remain unmasked.Type: GrantFiled: January 10, 2008Date of Patent: December 29, 2009Assignee: Texas Instruments IncorporatedInventor: Toshiyuki Nagata
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Patent number: 7629183Abstract: A method for fabricating a semiconductor device includes the steps of forming a PbTiOx film having a predominantly (111) orientation on a lower electrode as a nucleation layer by an MOCVD process with a film thickness exceeding 2 nm, and forming a PZT film having a predominantly (111) orientation on the nucleation layer, wherein the step of forming the PbTiOx film is conducted under an oxygen partial pressure of less than 340 Pa.Type: GrantFiled: June 12, 2006Date of Patent: December 8, 2009Assignee: Tokyo Electron LimitedInventors: Kenji Matsumoto, Masayuki Nasu, Tomoyuki Sakoda
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Patent number: 7622307Abstract: A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping layer, the planarized protecting layer, and the planarized insulating layer. The interconnection layer pattern is in contact with the phase-change pattern.Type: GrantFiled: July 19, 2005Date of Patent: November 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hyun Park, Jae-Hee Oh, Won-Cheol Jeong
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Patent number: 7615444Abstract: A method for forming a capacitor structure, according to which the following consecutive steps are executed: providing a substrate having on its surface contact pads and a dielectric mold provided with at least one trench leaving exposed the contact pads; forming a first conductive layer on side walls of the trench in a top region of the trench the conductive layer being without contact to the contact pads; depositing a first dielectric layer; depositing a second conductive layer on the contact pad and on the side walls of the trench; depositing a second dielectric layer; depositing a third conductive layer; and forming a vertical plug interconnecting the first conductive layer and the third conductive layer.Type: GrantFiled: June 29, 2006Date of Patent: November 10, 2009Assignee: Qimonda AGInventors: Odo Wunnicke, Peter Moll, Kristin Schupke
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Patent number: 7611945Abstract: A method for forming a capacitor structure for a dynamic random access memory device. The method includes forming a device layer overlying a semiconductor substrate, e.g., silicon wafer. The method includes forming a first interlayer dielectric overlying the device layer and forming a via structure within the first interlayer dielectric layer. The method includes forming a first oxide layer overlying the first interlayer dielectric layer and forming a stop layer overlying the first oxide layer. The method includes forming a second oxide layer overlying the first stop layer and forming a trench region through a portion of the second oxide layer, through a portion of the stop layer, and a portion of the second oxide layer. A bottom electrode structure is formed to line the trench region. The bottom electrode structure includes an inner region. The bottom electrode structure is coupled to the via structure.Type: GrantFiled: September 11, 2007Date of Patent: November 3, 2009Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Jeong Gi Kim
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Patent number: 7605037Abstract: The present invention provides an integrated semiconductor memory device comprising: a semiconductor substrate; a plurality of active area lines formed in said semiconductor substrate, each of which active area lines includes a plurality of memory cell selection transistors having a respective wordline contact, bitline contact, and node contact; a plurality of filled insulation trenches arranged between said active area lines; a plurality of rewiring stripes each of which rewires an associated node contact of a memory cell selection transistor from an active area line to above a neighboring filled insulation trench so as to form a respective rewired node contact; a plurality of bitlines being aligned with and running above said active area lines which bitlines are connected to the bitline contacts of the memory cell selection transistors of the respective active area lines; a plurality of wordlines running perpendicular to said bitlines which are connected to the wordline contacts of the memory cell selectionType: GrantFiled: February 9, 2007Date of Patent: October 20, 2009Assignee: Qimonda AGInventor: Rolf Weis
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Publication number: 20090257170Abstract: Methods for forming ruthenium films and semiconductor devices such as capacitors that include the films are provided.Type: ApplicationFiled: April 10, 2008Publication date: October 15, 2009Inventors: Vishwanath Bhat, Dan Gealy, Vassil Antonov
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Patent number: 7585723Abstract: A method for fabricating a semiconductor device includes forming an insulation structure over a substrate structure including contact plugs, etching the insulation structure to form opening regions each of which has a lower opening portion having a critical dimension wider than an upper opening portion, and forming a conductive layer contacting the contact plugs inside the opening regions.Type: GrantFiled: February 13, 2007Date of Patent: September 8, 2009Assignee: Hynix Semiconductor IncInventor: Ky-Hyun Han
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Patent number: 7586196Abstract: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.Type: GrantFiled: August 15, 2007Date of Patent: September 8, 2009Assignee: Intel CorporationInventors: Valery M. Dubin, Peter K. Moon