Abstract: A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

Abstract: A lead frame used in semiconductor packaging has an outer dam bar and inner leads that extend away from the dam bar. The inner leads have distal ends and tips at the distal ends. Each inner lead has a coined area on a first major surface at the distal end and spaced from the tip. The coined area and the spacing of the coined area from the tip form a shoulder structure. The coined area is configured to receive one end of a bond wire that interconnects the inner lead with a wire bond pad of a semiconductor die. The shoulder structure creates a molding compound locking mechanism to reduce shear stress and delamination in the lead bonding area.

Abstract: A lead frame including rails, section bars, and lead frame cells. The rails are respectively arranged at edges of the lead frame extending in a first direction. The section bars extend between the rails in a second direction and are orthogonal to the rails. The lead frame cells are aligned along the section bars. At least one of the section bars includes a rib extending in the second direction and formed through a half blanking process.

Abstract: To provide an inexpensive lead component which can be easily connected to a semiconductor chip and which has satisfactory connectability. There is provided a lead component including a base material having a connection part for connecting to a semiconductor chip, comprising: a solder part having a Zn layer made of a Zn-bonding material rolled and clad-bonded on the base material, and an Al layer made of an Al-bonding material rolled and clad-bonded on the Zn layer, in a prescribed region including the connection part on the base material; and the solder part further comprising a metal thin film composed of one kind or two kinds or more of Au, Ag, Cu, Ni, Pd, and Pt covering a surface of the Al layer.

Abstract: An integrated circuit package system is provided including forming a leadframe having a frame and a die paddle having leads thereon. The leads are held with respect to the die paddle. The leads are separated from the die paddle, and a die is attached to the die paddle. Bond wires are bonded between the leads and the die. The die and bond wires are encapsulated. The leadframe is singulated to separate the frame and the die paddle.

Abstract: A method of manufacturing of an integrated circuit packaging system includes: providing a base substrate; mounting a first die over the base substrate; mounting a second die over the first die; attaching an interposer substrate over the first die with an attachment adhesive therebetween, the interposer substrate having a central cavity and the second die within the central cavity; attaching a lateral interconnect to a second active side away from the first die of the second die and to the interposer substrate; and encapsulating the first die and the second die.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a substrate having a redistribution line thereon; mounting an integrated circuit to the substrate; and molding a transparent encapsulation over the substrate covering the integrated circuit and the redistribution line and the integrated circuit seen through the transparent encapsulation.

Abstract: A semiconductor apparatus includes a semiconductor device, a bed, a plurality of leads, a suspension pin, and a mold resin. The bed includes an alignment pin provided in a peripheral portion of the bed. The semiconductor device is mounted on the bed via a first solder. The plurality of leads are electrically connected to a plurality of electrodes of the semiconductor device. The suspension pin is made of the same conductive material as the lead. The suspension pin has an alignment hole in a tip of the suspension pin. The suspension pin engages the peripheral portion of the bed by the alignment pin being inserted into the alignment hole. The suspension pin is fixed to the peripheral portion of the bed by a second solder. The mold resin contains the semiconductor device, the bed, one end of the leads, and the suspension pin.

Abstract: A heat spreader frame is provided including: heat spreaders having upper surfaces; a peripheral frame surrounding the heat spreaders; spreaders, the peripheral frame having stand-off legs; tie bars having upper surfaces and a pin identifier at an end portion of the tie bars, the heat spreaders connected to one another and to the peripheral frame by the tie bars, the width of the stand-off legs wider than widths of the tie bars; at least portions of the upper surfaces of the tie bars being thinned to reduce heights of the tie bars; the upper surfaces of the heat spreader in an elevated position supported by the peripheral frame; and the heat spreaders and the tie bars covered by an package molding compound exposing the upper surface of the heat spreaders and one surface of the pin identifier coplanar to the upper surfaces of the heat spreaders.

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: leads and a paddle; a first encapsulant molded between the leads and the paddle, the first encapsulant thinner than the leads; a non-conductive layer over the paddle; and conductive traces directly on the leads, the first encapsulant, and the non-conductive layer.

Abstract: A Plastic Leaded Chip Carrier (PLCC) package is disclosed. The PLCC package provides a light source that is both high contrast and high brightness. Specifically, the PLCC package includes a reflector cup whose surface area is partially inclusive of a lead frame and partially inclusive of a plastic housing that surrounds the lead frame.

Abstract: Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding compound, proximate a selected surface or surfaces of a semiconductor die or dice during encapsulation are disclosed. Flow diverting structures may be included in or associated with one or more portions of a lead frame, such as a paddle, tie bars, or lead fingers. Flow diverting structures may also be inserted into a mold in association with semiconductor dice carried on non-lead frame substrates, such as interposers and circuit boards, to preferentially impede, redirect or both impede and redirect the flow of molding compound flowing between and over the semiconductor dice.

Abstract: According to one exemplary embodiment, a lead frame package includes a number of leads and a number of contacts, where each of the contacts is situated over one of the leads. The lead frame package further includes a semiconductor die including a number of bond pads. Each of the contacts is directly attached and bonded to one of the bond pads on the semiconductor die. Each of the contacts is situated over a top portion of one of the leads, where the top portion has a shorter length than a middle portion of each of the leads. Each of the contacts is connected to one of the bond pads on the semiconductor die without a wire bond. The semiconductor die does not include a redistribution layer situated over an active surface of the semiconductor die.

Abstract: According to one embodiment, a semiconductor storage device includes an organic board provided with external connection terminals on one surface and formed as an individual piece into a plane shape substantially identical to that of an area where the external connection terminals are provided, a lead frame having a mounting area positioned relative to the organic board, and a semiconductor memory chip bonded to the mounting area.

Abstract: A method of manufacturing of an integrated circuit packaging system includes: providing a bottom package in a cavity in a central region of the bottom package having inter-package interconnects in the cavity; forming a vent on an inter-package connection side of the bottom package from an exterior of the bottom package to the cavity; mounting a top package on the inter-package interconnects; and applying an underfill through the vent and into the cavity.

Abstract: A lead frame strip includes an array of sites connected to two side rails which traverse the lead frame strip on two opposite sides. Each site includes a die pad for affixing a semiconductor die and leads for enabling electrical communication between the semiconductor die and a workpiece. Each site is further connected to the two side rails by a sub-rail, which extends between the two side rails. The sub-rail includes a flat portion and a raised or indented rib protruding from the flat portion. The rib has a long dimension parallel to the sub-rail.

Abstract: An integrated circuit packaging apparatus includes a first conductive layer disposed between an integrated circuit die and a conductive die paddle. Bond wires connect the first conductive layer to the lead frame package and to the integrated circuit die. A first dielectric layer is disposed between the first conductive layer and the conductive die paddle such that the first conductive layer, the first dielectric layer, and the conductive die paddle provide bypass capacitance. A method for providing bypass capacitance and power routing for an integrated circuit packaging apparatus includes; depositing a first dielectric layer on a conductive die paddle, depositing a first conductive layer on the first dielectric layer, and connecting the first conductive layer to the lead frame package and to the integrated circuit die. The first conductive layer, the first dielectric layer, and the conductive die paddle cooperate to provide bypass capacitance.

Abstract: A leadframe structure for an electronic package is provided, wherein the leadframe structure comprises a die-pad, a barrier area, and a bonding area, wherein the barrier area is arranged between the die-pad and the bonding area, and wherein the barrier area is adapted to electrically connect the die-pad and the bonding area, and is further constructed in such a way that delamination growth between the leadframe structure and a moulding compound fixable to the leadframe structure is reduced.

Abstract: A method for manufacturing a semiconductor device, includes: placing a seal layer including a connection conductive film on the surface so that the connection conductive film is in contact with an electrode of a semiconductor element and a lead; electrically coupling the electrode and the lead through the connection conductive film; and sealing the semiconductor element by the seal layer.

Abstract: A semiconductor device of the present invention has a stacked structure including a lead frame having a front surface and a back surface, the front surface being made of Cu, a semiconductor chip having a front surface and a back surface, including a Cu layer that forms the back surface, disposed so that the back surface is opposed to the front surface of the lead frame, and a bonding layer interposed between the lead frame and the semiconductor chip, in which the bonding layer includes a Bi-based material layer and Cu alloy layers not containing Pb that sandwich the Bi-based material layer from both sides in an opposing direction of the lead frame and the semiconductor chip with respect to the Bi-based material layer.

Abstract: In a semiconductor device, a first semiconductor element having a first terminal is embedded in a resin layer such that terminals thereof are exposed through a first surface of the resin layer. A wiring layer is formed in the first surface of the resin layer. A second semiconductor element includes second and third terminals. Regardless of the relationship between the plane size of the first semiconductor element and that of the second semiconductor element, the second terminal of the second semiconductor element is connected to the first terminal of the first semiconductor element exposed through the first surface of the resin layer, and the third terminal of the second semiconductor element is connected to the wiring layer formed in the resin layer.

Abstract: A ceramic semiconductor package provides for being surface mounted on a printed circuit board or other mounting surface. A ceramic frame is directly attached to a lead frame to define a cavity in which the base of a semiconductor device is mounted to the portion of the lead frame exposed at the bottom of the cavity. Interface terminals of the semiconductor device are attached to electrical contacts on the ceramic frame inside the cavity. The ceramic package provides a hermetic insulated path through which the signals can be routed from the device to the external leads. Additionally, because the semiconductor device is directly attached to the lead frame, power dissipation, i.e., heat dissipation, is more effectively provided by this direct connection without intervening layers of ceramic or conductor.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle; forming a pad extension having a spacing to the package paddle; forming a lead adjacent the pad extension, the pad extension between the package paddle and the lead; forming a conductive layer directly on and between the package paddle and the pad extension; and connecting an integrated circuit to the pad extension and the lead, the integrated circuit over the package paddle.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base circuit assembly having an integrated circuit device; mounting a pre-formed conductive frame having an outer interconnect and an inner interconnect over the base circuit assembly, the inner interconnect on the integrated circuit device and the outer interconnect around the integrated circuit device; applying an encapsulant over the inner interconnect and the outer interconnect; and removing a portion of the pre-formed conductive frame exposing an end of the inner interconnect and the outer interconnect.

Abstract: Semiconductor packages include a semiconductor chip, a lead frame on which the semiconductor chip is mounted, and a mold layer to encapsulate the semiconductor chip and the lead frame. The lead frame is electrically connected to the semiconductor chip. The lead frame includes a first lead frame and a second lead frame. The first lead frame is electrically connected to the semiconductor chip by a plurality of bonding wires. The first lead frame has outer leads that protrude from the mold layer. The second lead frame is attached to the first lead frame by an insulating adhesion layer. The second lead frame provides a mounting surface on which the semiconductor chip is mounted. The first and second lead frames support the semiconductor chip.

Abstract: A process for increasing the adhesion of a polymeric material to a metal surface, the process comprising contacting the metal surface with an adhesion promoting composition comprising: 1) an oxidizer; 2) an inorganic acid; 3) a corrosion inhibitor; and 4) an organic phosphonate; and thereafter b) bonding the polymeric material to the metal surface. The organic phosphonate aids in stabilizing the oxidizer and organic components present in the bath and prevents decomposition of the components, thereby increasing the working life of the bath, especially when used with copper alloys having a high iron content.

Abstract: A method for manufacturing a microelectronic package (1) comprises the steps of providing two parts (13, 14) comprising electrically insulating material such as plastic; providing members (21, 22, 23) comprising electrically conductive material; providing a microelectronic device (30); positioning the electrically conductive members (21, 22, 23) and the microelectronic device (30) on the electrically insulating parts (13, 14); and placing the electrically insulating parts (13, 14) against each other, wherein the microelectronic device (30) and portions of the electrically conductive members (21, 22, 23) are sandwiched between the electrically insulating parts (13, 14). The electrically conductive members (21, 22, 23) are intended to be used for realizing contact of the microelectronic device (30) arranged inside the package (1) to the external world.

Abstract: An IC package is provided. The IC package comprises a leadframe comprising a metal strip(222) partially etched on a first side. The leadframe may be configured for an IC chip to be mounted thereon and for a plurality of bonding areas(218) to be electrically coupled to the leadframe and the IC chip. The IC chip, the bonding areas, and a portion of the metal leadframe are covered with an encapsulation compound, with a plurality of contact pads(206) protruding from the bottom surface of the leadframe. The bottom surface of the leadframe may be etched one or more times during the manufacturing process to reduce the depth of the undercutting. A method for manufacturing an IC package is also provided.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board.

Abstract: According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.

Abstract: A method of manufacturing a semiconductor apparatus according to aspects of the invention can include the steps of coating solder on an predetermined area in the upper surface of a lead frame, mounting a chip on solder and melting solder with a hot plate for bonding the chip to the lead frame. The method can also include wiring with bonding wires, turning lead frame upside down, placing lead frame turned upside down on heating cradle, coating solder, the melting point of which is lower than the solder melting point and mounting electronic part on solder; and melting solder with heating cradle for bonding electronic part to lead frame. The bonding with solder can be conducted at a high ambient temperature. Aspects of the semiconductor apparatus can facilitate mounting semiconductor devices and electronic parts on both surfaces of a lead frame divided to form wiring circuits without through complicated manufacturing steps.

Abstract: A lead frame and a semiconductor package including the lead frame are provided. The lead frame includes: a base material; a first metal layer which is formed on at least one side of the base material, of which a surface is roughly formed, and which includes copper or nickel; a second metal layer which is formed on a surface of the first metal layer, of which a surface is roughly formed, and which includes palladium or a palladium alloy; a third metal layer which is formed on a surface of the second metal layer, of which a surface is roughly formed, and which includes gold or a gold alloy; and a fourth metal layer which is formed on a surface of the third metal layer, of which a surface is roughly formed, and which includes metal that includes silver.

Abstract: Semiconductor packages having lead frames include a lead frame, which supports a semiconductor chip and is electrically connected to the semiconductor chip by bonding wires, and a molding layer encapsulating the semiconductor chip. The lead frame includes first lead frames extending in a first direction and second lead frames extending in a second direction. The first lead frames may run across the semiconductor chip and support the semiconductor chip and the second lead frames may run across the bottom surface of the semiconductor chip.

Abstract: An electronic device is provided with: a first electronic circuit, integrated in a first die; a second electronic circuit, integrated in a second die; and a galvanic isolator element, designed to insulate galvanically, and to enable transfer of signals between, the first electronic circuit and the second electronic circuit. The galvanic isolator element has: a transformer substrate, distinct from the first die and from the second die; and a galvanic-insulation transformer formed by a first inductive element, integrated in the first die, and by a second inductive element, integrated in the transformer substrate and so arranged as to be magnetically coupled to the first inductive element.

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a leadframe, a flip chip driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. The source of the control transistor is electrically coupled to the drain of the sync transistor using the leadframe and one of the transistor conductive clips. In this manner, the leadframe and the conductive clips provide efficient current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract: A stack type semiconductor package and a method of fabricating the stack type semiconductor package. The stack type semiconductor package includes: a lower semiconductor package including a circuit board, a semiconductor chip which is disposed on an upper surface of the circuit board, via-pads which are arrayed on the upper surface of the circuit board around the semiconductor chip, and an encapsulation layer which encapsulates the upper surface of the circuit board and has via-holes through which the via-pads are exposed; and an upper semiconductor package which is stacked on the encapsulation layer, is electrically connected to the lower semiconductor package, and comprises internal connection terminals which are formed on a lower surface of the upper semiconductor package.

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a sync transistor with a top surface having a drain, a flip chip driver integrated circuit (IC) having an integrated control transistor, the flip chip driver IC driving the sync and control transistors, and a conductive clip electrically coupling the drain of the sync transistor to a common portion of the leadframe shared with a control source of the control transistor. In this manner, the leadframe and the conductive clip provide efficient current conduction by direct mechanical connection and large surface area conduction, significantly reducing package electrical resistance, form factor, complexity, and cost compared to conventional packages.

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip electrically coupling a sync drain of the sync transistor to a first leadframe pad of the package, wherein the first leadframe pad of the package is electrically coupled to a control source of the control transistor using a wirebond. The conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction. A sync source is electrically and mechanically coupled to a second leadframe pad providing a high current carrying capability, and high reliability. The resulting package has significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract: A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands.

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip extending from a sync drain on a top surface of the sync transistor to a control source on a top surface of the control transistor. The conductive clip may also connect to substrate pads such as a leadframe pad for current input and output. In this manner, the conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract: A semiconductor chip package comprises a lead frame having a chip carrier having a first surface and an opposite second surface. A first semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the first semiconductor chip has an area larger that that of the chip carrier. A package substrate has a central region attached to the second surface of the chip carrier, having an area larger than that of the first semiconductor chip, wherein the package substrate comprises a plurality of fingers on a top surface thereof in a marginal region of the package substrate, which are arranged in an array with a row of inner fingers adjacent to the first semiconductor chip and a row of outer fingers adjacent to an edge of the package substrate, wherein the inner and outer fingers are electrically connected to the bonding pads of the first semiconductor chip and the lead frame respectively.

Abstract: An integrated circuit package system comprising: providing a package substrate; attaching an integrated circuit die over the package substrate wherein the integrated circuit die has a mount height; attaching an attachment structure having a height substantially the same as the mount height and planar dimensions predetermined to fit adjacent the integrated circuit die and over the package substrate; and attaching a heat dissipation device over the integrated circuit die and the attachment structure.

Abstract: A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.

Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.

Abstract: An integrated circuit package system is provided including forming a lead frame including forming an inner lead having a planar surface, the inner lead extending inwardly from the lead frame and forming a stiffening structure integral with the lead frame for maintaining the planar surface; encapsulating the inner lead with an electrical connection to an integrated circuit die and with a first inner lead body of the inner lead exposed; and singulating the inner lead from the lead frame.

Abstract: Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.

Abstract: Several embodiments of microelectronic packages with enhanced heat dissipation and associated methods of manufacturing are disclosed herein. In one embodiment, a microelectronic package includes a semiconductor die having a first side and a second side opposite the first side and a lead frame proximate the semiconductor die. The lead frame has a lead finger electrically coupled to the first side of the semiconductor die. The microelectronic package also includes an encapsulant at least partially encapsulating the semiconductor die and the lead frame. The encapsulant does not cover at least a portion of the second side of the semiconductor die.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base structure having a die paddle, an outer lead, and an inner lead between the die paddle and the outer lead, with a pre-plated finish on a base structure system side of the base structure; mounting an integrated circuit device to a side of the die paddle opposite the paddle system side; attaching an interconnect to the integrated circuit device and a side of the inner lead opposite the inner lead system side; applying an encapsulation around the integrated circuit device, the interconnect, and the base structure with the pre-plated finish exposed from the encapsulation; and forming an inward channel in the encapsulation to electrically isolate the inner lead.