Abstract: A method of manufacturing an electronic device is provided. The method comprises providing a carrier sheet, etching the lead frame material sheet to form a recess on a first surface of the lead frame material sheet, placing an electronic chip into the recess of the carrier sheet, and thereafter, selectively etching a second surface of the lead frame material sheet, the second surface being opposite to the first surface.

Abstract: A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.

Abstract: An LED lead frame comprises an insulative housing including a top surface, a bottom surface, and four side surfaces connected the top surface and the bottom surface, and a cavity recessed from the top surface. A pair of conductive leads each has a portion embedded into the insulative housing and another portion exposed out of the insulative housing. The another portion includes an end portion extending downwardly along one of the side surface, a bottom soldering portion extending continuously from the end portion along the bottom surface, and a pair of side soldering portions extending upwardly from two ends of the bottom soldering portion along another two opposite side surfaces. The bottom soldering portion and the side soldering portions can be used as an alternative mounting surface.

Abstract: A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

Abstract: A leadframe includes a die paddle and leads, in which the back side of the die paddle has a fillister. The fillister defines a rim surrounding a recess, and the recess accommodates protrusion of fusible material. Also, a package includes such a leadframe. Also, a method for making a leadframe includes patterning a sheet of metal to form a die paddle and leads, and forming a fillister in the back side of the die paddle.

Abstract: A lead frame for a semiconductor device has a die pad with a first major surface for receiving an semiconductor die and a connection bar that encircles the die pad. First lead fingers that project from the connection bar towards the die pad have proximal ends close to the die pad and distal ends connected to the connection bar. The proximal ends of the first lead fingers lie in a first plane. Second lead fingers that project from the connection bar towards the die pad have proximal ends close to the die pad and distal ends connected to the connection bar. The proximal ends of the second lead fingers lie in a second plane that is parallel and spaced from the first plane. An isolation frame is disposed between the proximal ends of the first and second lead fingers. The isolation frame separates but supports the proximal ends of the first and second lead fingers.

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Abstract: A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package.

Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. A leadframe has a plurality of conductive leads and first and second bodies extending from the opposite sides of the conductive leads. The leadframe is mounted to the carrier with the conductive lead disposed over the first semiconductor die and the bodies disposed around the first semiconductor die. An adhesive layer is deposited between the first semiconductor die and conductive leads. A second semiconductor die is mounted over the leadframe and electrically connected to the conductive leads. An encapsulant is deposited over the first semiconductor die. The carrier is removed. A first interconnect structure is formed over a first surface of the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected to the first and second bodies of the leadframe.

Abstract: An integrated circuit package system includes providing a leadframe that is coplanar with a bottom surface of the integrated circuit package system to which is attached a device with a thermally conductive coating that is coplanar with the bottom surface of the integrated circuit package system to the leadframe, the device having the characteristics of being singulated from a wafer and the thermally conductive coating having the characteristics of being singulated from a wafer level thermally conductive coating and encapsulating the device with an encapsulation material that leaves the thermally conductive coating exposed for thermal dissipation.

Abstract: Lead frames and their fabricating method which reduce generation of defects in the process of fabricating semiconductor devices, in particular connection defects in wire bonding, thereby improving the product yield and reliability, and semiconductor devices using the lead frames and their fabricating method are provided. A method for fabricating a lead frame is characterized in including a process of forming a substrate equipped with a convex portion, and a metal layer having a first portion that overlaps a first surface included in the convex portion and a second portion that extends from the first portion and does not overlap the first surface, and a process of bending the metal layer such that the second portion of the metal layer overlaps a second surface included in the convex portion that intersects the first surface.

Abstract: A Chip-On-Lead (COL) type semiconductor package having small chip hidden between leads is revealed. The lower surfaces of the leadframe's leads are attached to a wiring substrate and the leads are horizontally bent to form a die-holding cavity. A smaller chip is disposed on the wiring substrate by passing through the die-holding cavity to be on the same disposing level with the leads. At least a larger chip is disposed on the leads to overlap the smaller chip so that the small chip does not extrude from the leads. The encapsulant encapsulates a plurality of internal parts of the leads, the wiring substrate, and the larger chip. Therefore, the conventional unbalance issue of mold flow above and below the leads leading to cause excessive warpage can be avoided and numbers of stacked larger chips can be increased to have larger memory capacities.

Abstract: An electronic component is disclosed. In one embodiment, the electronic component includes a frame having a base layer, a first layer, a second layer including palladium placed on the first layer, and a third layer including gold placed on the second layer. A semiconductor chip is positioned on the frame.

Abstract: A leadframe for a leadframe type package includes a chip base, and leads constituting lead lanes. One lead lane includes a pair of first differential signal leads, a pair of second differential signal leads, a pair of third differential signal leads between which and the pair of first differential signal leads is arranged the pair of second differential signal leads and a first power lead arranged between the pair of first and second differential signal leads. One of the pairs of differential signal leads has half-double function transmission mode and two of the other pairs of differential signal leads have double function transmission mode.

Abstract: An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Abstract: A packaged device includes a package defining a well having a well top, a die positioned in the well of the package, and a retaining substrate attached to the package over the well top. The retaining substrate holds the die in direct contact with a portion of the package exposed at a well bottom opposite the well top.

Abstract: A package structure with an embedded die includes a core layer, a first build-up wiring structure, and a second build-up wiring structure. The core layer has a first surface and a second surface opposite thereto. Besides, the core layer includes a first dielectric layer, a leadframe, a die, a first signal layer, and a second signal layer. The die is disposed on and electrically connected to the leadframe. The die and the leadframe are embedded in the first dielectric layer. The first signal layer is disposed on an upper surface of the first dielectric layer and electrically connected to the leadframe. The second signal layer is disposed on a bottom surface of the first dielectric layer and electrically connected to the leadframe. The first and the second build-up wiring structures are disposed on the first and the second surfaces of the core layer, respectively.

Abstract: A component includes a first semiconductor chip attached to a first carrier and second semiconductor chip attached to a second carrier. The first carrier has a first extension, which forms a first external contact element. The second carrier has a second extension, which forms a second external contact element. The first and the second carriers are arranged in such a way that the first and the second extension point in different directions.

Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a first plurality of leads disposed in a lead placement area around the die pad, a second plurality of leads disposed in corner regions of the lead placement area, a semiconductor chip on the die pad and coupled to each lead, and a package body. Each lead includes an upper sloped portion and a lower sloped portion. An average of surface areas of lower surfaces of each of the second plurality of leads is at least twice as large as an average of surface areas of lower surfaces of each of the first plurality of leads. The package body substantially covers the upper sloped portions of the leads. The lower sloped portions of the leads at least partially extend outwardly from a lower surface of the package body.

Abstract: An optical semiconductor device can have a first lead for an optical semiconductor chip to be mounted on and a second lead for joining to a wire extending from the optical semiconductor chip. The device can be configured to be capable of reducing the possibility of a break of the wire even under a thermal shock and the like. The optical semiconductor device can include a first lead for an optical semiconductor chip to be mounted on, a second lead for joining to a wire (for example, gold wire) extending from the optical semiconductor chip mounted on the first lead; a holder part for supporting the first lead and the second lead at two locations each; a lens part; and a light-transmitting sealing part. The second lead can be separated into two lead pieces with a predetermined gap (?0) therebetween as seen in a plan view, or with certain bend configurations as shown in side views, within the inside space of the holder part by which the second lead is supported at two locations.

Abstract: A semiconductor package may include a package substrate having a first surface and a boundary that may be defined by edges of the package substrate. The package further includes a first semiconductor chip having a front surface and a back surface. The back surface of a first portion of the first semiconductor chip may be disposed on the first surface of the package substrate with the back surface of a second portion of the first semiconductor chip extending beyond of the defined boundary of the package substrate. The semiconductor package may also include a second semiconductor chip disposed on the back surface of the second portion of the first semiconductor chip that extends beyond the defined boundary of the package substrate.

Abstract: The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Abstract: A semiconductor device has a plurality of semiconductor die or components mounted over a carrier. A leadframe is mounted over the carrier between the semiconductor die. The leadframe has a plate and bodies extending from the plate. The bodies of the leadframe are disposed around a perimeter of the semiconductor die. An encapsulant is deposited over the carrier, leadframe, and semiconductor die. A plurality of conductive vias is formed through the encapsulant and electrically connected to the bodies of the leadframe and contact pads on the semiconductor die. An interconnect structure is formed over the encapsulant and electrically connected to the conductive vias. A first channel is formed through the interconnect structure, encapsulant, leadframe, and partially through the carrier. The carrier is removed to singulate the semiconductor die. A second channel is formed through the plate of the leadframe to physically separate the bodies of the leadframe.

Abstract: Provided is a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes a package main body with a cavity, a plurality of light emitting diode chips, a wire, and a plurality of lead frames. The plurality of light emitting diode chips are mounted in the cavity. The wire is connected to an electrode of at least one light emitting diode chip. The plurality of lead frames are formed in the cavity, and at least one lead frame is electrically connected to the light emitting diode chip or a plurality of wires.

Abstract: A semiconductor device and a lead frame capable of preventing development of defective mounting resulting from a burr and a method of manufacturing a semiconductor device with the lead frame are provided. The semiconductor device includes a semiconductor chip and a lead arranged on the periphery of the semiconductor chip to extend in a direction intersecting with the side surface of the semiconductor chip, so that at least an end portion on the side farther from the semiconductor chip is bonded to a mounting substrate. A groove opened on a surface bonded to the mounting substrate and an end face on the side farther from the semiconductor chip is formed in the lead over the full width in the width direction orthogonal to the thickness direction and along the end face. An embedded body made of solder is embedded in the groove.

Abstract: A package-on-package includes a package carrier; a semiconductor die assembled face-down to a chip side of the package carrier; a rewiring laminate structure between the semiconductor die and the package carrier; a plurality of bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier; and an IC package mounted on the package carrier. The IC package and the semiconductor die are at least partially overlapped.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion.

Abstract: A rear surface opposite to one plane of a die pad is formed to be exposed from one plane of a sealing resin. In addition, a concave portion disposed to be parallel with at least a first side of an outermost edge of a central structure and a second side adjacent to the first side, respectively, is formed in the one plane of the sealing resin. Here, a depth of the concave portion is equal to or greater than a height of the outermost edge of the central structure.

Abstract: A lead frame having a die thereon connects a conductive area on the die to a lead frame contact using a conductive clip that includes a structural portion that is received with a recess-like “tub” formed in the lead frame contact. The end of the clip received in the tub is held in place during subsequent handling by a solder paste deposit until the clip and leadframe undergo solder reflow to effect a reliable electrical connection. The effective surface area between one side of the clip and the other side of the clip within the tub is different so that the surface tension of the liquefied solder formed during the solder reflow step will “draw” the clip into a preferred alignment against a “stop” surface.

Abstract: A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.

Abstract: A leadframe for use in an integrated circuit (IC) package comprising a metal strip partially etched on a first side. In some embodiments, the leadframe may be selectively plated on the first side and/or on a second side. The leadframe may be configured for an IC chip to be mounted thereon and for a plurality of electrical contacts to be electrically coupled to the leadframe and the IC chip.

Abstract: A semiconductor device includes a lead frame, a semiconductor element mounted on the lead frame, and a frame-like member formed on the lead frame, surrounding the semiconductor element, and covering a side surface of the lead frame and exposing a lower surface of the lead frame. The frame-like member has at least one concave portion in a side surface thereof. The concave portion has a ceiling portion located at the same height as or lower than an upper surface of the lead frame, and a bottom portion located higher than the lower surface of the lead frame.

Abstract: A semiconductor chip package comprises a lead frame having a chip carrier having a first surface and an opposite second surface. A first semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the first semiconductor chip has an area larger that that of the chip carrier. A package substrate has a central region attached to the second surface of the chip carrier, having an area larger than that of the first semiconductor chip, wherein the package substrate comprises a plurality of fingers on a top surface thereof in a marginal region of the package substrate, which are arranged in an array with a row of inner fingers adjacent to the first semiconductor chip and a row of outer fingers adjacent to an edge of the package substrate, wherein the inner and outer fingers are electrically connected to the bonding pads of the first semiconductor chip and the lead frame respectively.

Abstract: A semiconductor package comprises a semiconductor component (e.g., a die) and a via at least partially covered by an encapsulant. The encapsulant forms substantially parallel top and bottom surfaces, with at least part of the via being exposed on the top surface. At least one conductive pad is exposed on the bottom surface, and the via can electrically couple the top and bottom surfaces, as well as couple the semiconductor component at the top and bottom surfaces. An additional semiconductor component can be coupled to the top surface with a circuit pattern formed on the top surface and coupled to the via.

Abstract: A tape carrier substrate includes: a tape carrier base 1; a first terminal section 2A including a plurality of first terminals 2a arranged with one another in a first direction W; a second terminal section 2B including a plurality of second terminals 2b; and first and second conductive wires 3a and 3b. A plurality of slits 7 arranged with one another in the first direction are provided in the tape carrier base. An interval between one of the plurality of slits placed at one end in the first direction and a corresponding end of the tape carrier base in the first direction and an interval between another one of the plurality of slits placed at the other end in the first direction and a corresponding end of the tape carrier base in the first direction are greater than an interval between adjacent ones of the plurality of slits.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having an upper hole below a paddle top side, the upper hole bounded by an upper non-horizontal side with a curve surface; forming a terminal adjacent the package paddle; mounting an integrated circuit on the paddle top side; and forming an encapsulation within the upper hole.

Abstract: Provided is a manufacturing method of a substrate for a semiconductor element including the steps of: providing a first photosensitive resin layer on a first surface of a metal plate; providing a second photosensitive resin layer on a second surface different from the first surface of the metal plate; forming a first etching mask for forming a connection post on the first surface of the metal plate; forming a second etching mask for forming a wiring pattern on the second surface of the metal plate; forming the connection post by performing an etching from the first surface to a midway of the metal plate; filling in a premold resin to a portion of the first surface where the connection post does not exist; processing so that a height of the connection post of the first surface is lower than a height of the premold resin surrounding the connection post; and forming the wiring pattern by performing an etching on the second surface.

Abstract: A semiconductor chip 101 with surface 101b free of circuitry assembled on a metal carrier 102 by an attachment layer 103 with thickness 103a. Included in layer 103 are metal bodies 104 and an adhesive polymeric compound 105 between bodies 104. Metal bodies 104 form metal inter-diffusions with carrier 102 and extend from the carrier across thickness 103a, stopping at and contacting second chip surface 101b. The high thermal conductivity of metal bodies 104 greatly increases the thermal conductivity of the attachment layer. The metal bodies may be arrayed in a regularly spaced pattern in x- and y-directions, as well as in enhanced concentrations in locations of thermal hot spots and of high thermomechnical stresses. In the latter application, the metal bodies prevent the growth of microcracks and delamination.

Abstract: A semiconductor device having an improved whisker resistance in an exterior plating film is disclosed. The semiconductor device includes a tab with a semiconductor chip fixed thereto, plural inner leads, plural outer leads formed integrally with the inner leads, a plurality of wires for coupling electrode pads of the semiconductor chip and the inner leads with each other, and a sealing body for sealing the semiconductor chip. The outer leads project from the sealing body and an exterior plating film, which is a lead-free plating film, is formed on a surface of each of the outer leads.

Abstract: A modular package for a light emitting device includes a leadframe including a first region having a top surface, a bottom surface and a first thickness and a second region having a top surface, a bottom surface and a second thickness that is less than the first thickness. The leadframe further includes an electrical lead extending laterally away from the second region, and the package further includes a thermoset package body on the leadframe and surrounding the first region. The thermoset package body may be on both the top and bottom surfaces of the second region. A leak barrier may be on the leadframe, and the package body may be on the leak barrier. Methods of forming modular packages including thermoset package bodies on leadframes are also disclosed.

Abstract: A package is disclosed. The package includes a premolded substrate having a leadframe structure, a first device attached to the leadframe structure, and a molding material covering at least part of the leadframe structure and the first device. It also includes a second device attached to the premolded substrate.

Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.

Abstract: A leadframe for a semiconductor package is disclosed including electrical leads which extend from one side of the leadframe to an opposite side of the leadframe, where electrical connection may be made with the semiconductor die at the second side of the leadframe. The semiconductor die may be supported on the leads extending across the leadframe. The package may further include a spacer layer affixed to the electrical leads to fortify the semiconductor package and to prevent exposure of the electrical leads during the molding of the package.

Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.

Abstract: Apparatuses are disclosed, such as those involving integrated circuit packaging. In one embodiment, a chip package includes: an encapsulation having a top surface and a bottom surface facing away from the top surface. The package further includes a leadframe including a plurality of leads. Each of the leads includes an exposed portion exposed through one of edges of the bottom surface of the encapsulation. The exposed portion has a length. At least one of exposed portions positioned along one of the edges of the bottom surface of the encapsulation has a length different from other exposed portions along the edge. The package can also include a dummy pad exposed through a corner of the bottom surface. The configuration can enhance solder joint reliability of the package when the package is attached to a printed circuit board.

Abstract: A circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface. A nonconductive adhesive is on the surface. A plurality of electronic circuit dies are on the surface of the die attach pad. Each die has a top surface and a bottom surface with the bottom surface on the adhesive. The top surface has a plurality of bonding pads. A first electronic circuit die has at least one routing path of a conductive material connecting a first bonding pad to a second bonding pad. A first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die. A second bonding wire connects the second bonding pad of the first electronic circuit die to a lead. Where one of the dies contains vertical circuit element, where a doped layer forms a terminal along the bottom surface of the layer, a trench filled with doped polysilicon extends from the top surface to the terminal to connect to the terminal.

Abstract: Various semiconductor package arrangements and methods that improve the reliability of wire bonding a die to ground or other outside contacts are described. In one aspect, selected ground pads on the die are wire bonded to a bonding region located on the tie bar portion of the lead frame. The tie bar is connected to an exposed die attach pad that is downset from the bonding region of the tie bar. In some embodiments, the bonding region and the leads are at substantially the same elevation above the die and die attach pad. The die, bonding wires, and at least a portion of the lead frame can be encapsulated with a plastic encapsulant material while leaving a contact surface of the die attach pad exposed to facilitate electrically coupling the die attach pad to an external device.

Abstract: An integrated circuit package system is provided including forming an external interconnect having a lead tip and a lead body, forming a recess in the lead body from a lead body top surface, connecting an integrated circuit die and the external interconnect, and molding the external interconnect with the recess filled.

Abstract: A lead frame comprises: a base metal layer; a copper plating layer, including one of a copper layer and an alloy layer including a copper, configured to plate the based metal layer to make a surface roughness; and an upper plating layer, including at least one plating layer including at least one selected from the group of a nickel, a palladium, a gold, a silver, a nickel alloy, a palladium alloy, a gold alloy, and a silver alloy, configured to plate the copper plating layer.

Abstract: A two tier power module has, in one form thereof, a PC board having upper and lower traces with an opening in the insulating material that contains a power device which has upward extending solder bump connections. An upper leadframe is mounted on the solder bumps and the upper tracks of the PC board. Vias in the PC board connect selected upper and lower traces. A control device is mounted atop the leadframe and wire bonded to the leadframe, and the assembly is encapsulated leaving exposed the bottom surfaces of the lower traces of the PC board as external connections. In another form the PC board is replaced by a planar leadframe and the upper leadframe has stepped sections which make connections with the planar leadframe, the bottom surfaces of the planar leadframe forming external connections of the module.