Abstract: A miniaturized floating gate (FG) MOSFET radiation sensor system is disclosed, The sensor preferably comprises a matched pair of sensor and reference FGMOSFETs wherein the sensor FGMOSFET has a larger area floating gate with an extension over a field oxide layer, for accumulation of charge and increased sensitivity. Elimination of a conventional control gate and injector gate reduces capacitance, and increases sensitivity, and allows for fabrication using standard low cost CMOS technology. A sensor system may be provided with integrated signal processing electronics, for monitoring a change in differential channel current ID, indicative of radiation dose, and an integrated negative bias generator for automatic pre-charging from a low voltage power source. Optionally, the system may be coupled to a wireless transmitter. A compact wireless sensor System on Package solution is presented, suitable for dosimetry for radiotherapy or other biomedical applications.

Abstract: A TFA (thin film on ASIC) image sensor with stability-optimized photodiode for converting electromagnetic radiation into an intensity-dependent photocurrent. The TFA includes an intermetal dielectric layer, pixel back electrodes, vias, metal contacts, a transparent conductive oxide (TCO) layer, and an intrinsic absorption layer with a thickness between 300 nm and 600 nm. The pixel back electrodes are disposed over the intermetal dielectric layer, which is disposed over the ASIC. The vias connect to the pixel back electrodes and the metal contacts, which are formed in the intermetal dielectric layer. The TCO is disposed above the intrinsic absorption layer, which is disposed above the pixel back electrodes.

Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.

Abstract: CMOS image sensor is realized, wherein a pre-amp amplifies the voltage of a photo detector, and a main amp amplifies the output of the pre-amp. And the pre-amp is adjustable for receiving the output of the photo detector, and also the main amp is adjustable for optimizing the output swing. With the adjustable amps, low sensitivity photo detector can be amplified more, and high sensitivity photo detector can be amplified less, which enables to adjust the gain of each amp from the low-sensitive to high-sensitive photo detector. The information for adjusting the amps is stored in the latches of the chip, wherein include laser-blown fuses or electric fuses. In doing so, the photo detector can be stacked over the access device. In particular, photo detector is repairable, wherein failed photo detector is replaced with non-failed photo detector.

Abstract: A photoelectric conversion device in which at least a first metal wiring layer and a second metal wiring layer are arranged on a semiconductor substrate in an order named, the semiconductor substrate comprises a pixel region where a plurality of pixels are arrayed in a matrix, each pixel including at least a photoelectric conversion portions and an amplification transistor, wherein the second metal wiring layer includes power supply lines each configured to supply a power supply voltage to the amplification transistors of at least two pixel columns, and wherein the amplification transistor of a pixel column having no power supply line receives the power supply voltage from the power supply line via the first metal wiring layer.

Abstract: The disclosure includes methods of manufacturing a semiconductor device formed on an SOI structure. In one example, a first and second semiconductor layer is formed on a semiconductor substrate including a first region. The first semiconductor layer and the second semiconductor layer are removed from a second region to form a recess for a support. A support precursor layer is formed. A portion of the support precursor layer is removed to form a support coupling the recess and the second semiconductor layer. A part of the first and second semiconductor layer is etched using the support as a mask. The first semiconductor layer is etched and removed to form a cavity under the second semiconductor layer. The second semiconductor layer is thermally oxidized to form a buried insulating layer in the cavity and the support is removed from at least the first region to expose the second semiconductor layer.

Abstract: A sensor includes: a semiconductor chip having a sensing portion and a first bump; a circuit chip having a second bump; and a resin film having a groove. The semiconductor chip and the circuit chip are integrated with sandwiching the resin film therebetween. The resin film includes a first space and a second space before the first bump is bonded to the second bump. The first space faces the sensing portion. The second space is disposed on a periphery of the first space. The resin film expands when the first bump is bonded to the second bump. The second space accommodates an expanded portion of the resin film. The first space provides the groove after the first bump is bonded to the second bump.

Abstract: A detector includes a light detecting layer and a grating structure. The light detecting layer, which can be a photodiode, has an optical mode that resonates in the light detecting layer, and the grating structure is positioned to interact with the optical mode. The grating structure further couples incident light having a resonant frequency into the optical mode, and causes destructive interference to prevent light having the resonant frequency from escaping the detecting layer. The light detecting layer can be made transparent to light having other frequencies, so that a stack of such detectors, each having a different resonant frequency, can be integrated into a WDM detector that is compact and efficient.

Abstract: A method of forming a mask for lithography includes the step of forming the mask by using reverse data in which positions of at least part of output terminals are reversed, when forming the mask for lithography used for manufacturing a back-illuminated solid-state imaging device which takes incident light from the side of a surface opposite to the side of a surface on which wiring of a device region in which photoelectric conversion elements are formed is formed.

Abstract: An infrared ray sensor element includes: a first signal wiring part including a first signal wire and provided on a first region of a semiconductor substrate different from a region on which a concave part is provided; a second signal wiring part including a second signal wire and provided on the first region so as to intersect the first signal wiring part; a supporter including a support wiring part disposed over the concave part, and including a first wire electrically connected at a first end thereof to the first signal wire, and a second wire insulated from the first wire, disposed in parallel with the first wire, and electrically connected at a first end thereof to the second signal wire; a thermoelectric transducer electrically connected to second ends of the first and second wires; an infrared ray absorption layer provided over the thermoelectric transducer; and a detection cell provided over the concave part.

Abstract: A semiconductor device includes a semiconductor substrate formed of at least two kinds of group III elements and nitrogen, an active layer formed on the semiconductor substrate, and a nitride semiconductor layer formed on a surface of the semiconductor substrate and formed between the semiconductor substrate and the active layer. The nitride semiconductor layer is formed of the same constituent elements of the semiconductor substrate. A composition ratio of the lightest element among the group III elements of the nitride semiconductor layer is higher than a composition ratio of the corresponding element of the semiconductor substrate.

Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is flexible and superiority in physical strength. As a method for manufacturing a semiconductor device, an element layer including a plurality of integrated circuits is formed over one surface of a substrate; a hole having curvature is formed in part of one surface side of the substrate; the substrate is thinned (for example, the other surface of the substrate is ground and polished); and the substrate is cut off so that a cross section of the substrate has curvature corresponding to a portion where the hole is formed; whereby a laminated body including an integrated circuit is formed. Further, a thickness of the substrate, which is polished, is 2 ?m or more and 50 ?m or less.

Abstract: A device (100) may use one or more conductive elements (112) to electrically couple a substrate (116) and a cap (114). In one embodiment, an acceleration sense element may be formed on the substrate (116), and the cap (114) may be used to provide hermetic protection to the acceleration sense element. In one embodiment, conductive elements (112) may be formed by dispensing conductive die attach material. Wire bonds (e.g. 322) bonded to bond pads (e.g. 332) on the substrate (e.g. 316) may be used to couple substrate (116), the conductive element pad (335), and the cap (114), to a desired predetermined potential.

Abstract: There is provided a backplane for an organic electronic device. The backplane has a TFT substrate; a multiplicity of electrode structures; and a bank structure defining a multiplicity of pixel openings on the electrode structures. The bank structure has a height adjacent to the pixel opening, hA, and a height removed from the pixel opening, hR, and hA is significantly less than hR.

Abstract: The present invention provides a method for fabricating a dielectric stack in an integrated circuit comprising the steps of (i) forming a high-k dielectric layer on a semiconductor substrate, (ii) subjecting the semiconductor substrate with the high-k dielectric layer to a nitrogen comprising vapor phase reactant and silicon comprising vapor phase reactant in a plasma-enhanced chemical vapor deposition process (PECVD) or a plasma-enhanced atomic layer chemical vapor deposition (PE ALCVD) process. Furthermore, the present invention provides a dielectric stack in an integrated circuit comprising (i) a high-k dielectric layer comprising at least a high-k material, (ii) a dielectric layer comprising at least silicon and nitrogen; (iii) an intermediate layer disposed between the high-k dielectric layer and the dielectric layer, the intermediate layer comprising the high-k material, silicon, and nitrogen.

Abstract: A method of packaging a MEMS device that includes, for example, the steps of providing a MEMS die that has a MEMS device, a seal ring and bond pads disposed thereon, providing a MEMS package that has a recess, a seal ring and bond pads disposed thereon, positioning the MEMS die over the MEMS package to align the seal rings and bond pads, inserting the MEMS die and MEMS package into a vacuum chamber and evacuating gasses therefrom to form a controlled vacuum pressure therein, sealing the MEMS package and the MEMS die together at the seal rings to form a package having a hermitically sealed interior chamber and simultaneously forming electrical connections between the corresponding bond pads.

Abstract: A semiconductor substrate includes: a first semiconductor layer; an oxide layer that is formed on the first semiconductor layer; a second semiconductor layer that is formed on the oxide layer; a first recess that is formed in the second semiconductor layer with extending from an upper face of the second semiconductor layer toward the first semiconductor layer, the first recess being formed at a position where an alignment mark for determining a forming position of an element which is to be built in the semiconductor substrate is to be formed; and an etching prevention layer that is inwardly formed from a position of an upper face of the first semiconductor layer, the position corresponding to the recess, the layer comprising a material that is prevented from being etched during etching of the first semiconductor layer.

Abstract: In a semiconductor device having a MEMS according to this invention, a plurality of units having movable portions for constituting a MEMS are monolithically mounted on a semiconductor substrate on which an integrated circuit including a driving circuit, sensor circuit, memory, and processor is formed. Each unit has a processor, memory, driving circuit, and sensor circuit.

Abstract: In one embodiment, a metallic micro-cantilever, comprises a silicon substrate, at least one via plug extending from a surface of the silicon substrate, a metallic layer cantilevered from the at least one via plug, and a metallic probe tip extending from a surface of the metallic layer.

Abstract: A method of forming a circuit includes providing a first substrate; positioning an interconnect region on a surface of the first substrate; providing a second substrate; positioning a device structure on a surface of the second substrate, the device structure including a stack of at least three doped semiconductor material layers; and bonding the device structure to the interconnect region.

Abstract: A method for forming a buried mirror in a semiconductor component includes the steps of forming a structure comprising a semiconductor layer laid on an insulating layer covering a substrate; forming one or several openings in the semiconductor layer emerging at the surface of the insulating layer; eliminating a portion of the insulating layer, whereby a recess is formed; forming a second thin insulating layer against the wall of the recess; and forming a metal layer in the recess against the second insulating layer.

Abstract: An ultrasound monitoring system. In one embodiment, an array of transducer cells is formed along a first plane and an integrated circuit structure, formed along a second plane parallel to the first plane, includes an array of circuit cells. A connector provides electrical connections between the array of transducer cells and the array of circuit cells, and an interconnection structure is connected to transfer signals between the circuit cells and processing and control circuitry. The integrated circuit structure includes a semiconductor substrate and a plurality of conductive through-die vias formed through the substrate to provide Input/Output (I/O) connections between the transducer cells and the interconnection structure. The monitoring system may be configured as an imaging system and the processing and control circuitry may be external to the probe unit.

Abstract: It is realized a high sensitive solid-state imaging apparatus which corresponds to an optical system having a short focal length (an optical system having a large incident angle ?). Each pixel (2.8 mm square in size) includes a distributed refractive index lens (1), a color filter (2) for green, Al wirings (3), a signal transmitting unit (4), a planarized layer (5), a light-receiving element (Si photodiode) (6), and an Si substrate (7). The concentric circle structure of the distributed index lens is made of four types of materials having different refractive indexes such as TiO2 (n=2.53), SiN (n=2.53), SiO2 (n=2.53), and air (n=1.0). In the concentric structure, a radial difference of outer peripheries of adjacent circular light-transmitting films is 100 nm. Furthermore, the film thickness is 0.4 ?m.

Abstract: A nanorobotic apparatus is described consisting of hybrid MEMS and NEMS components. The nanorobot contains sensors for situational awareness. The apparatus has nanofilament components for communications.

Abstract: Here, we demonstrate new material/structures for the photodetectors, using semiconductor material. For example, we present the Tunable Avalanche Wide Base Transistor as a photodetector. Particularly, SiC, GaN, AlN, Si and Diamond materials are given as examples. The desired properties of an optimum photodetector is achieved. Different variations are discussed, both in terms of structure and material.

Abstract: A stacked integrated circuit assembly includes a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC is disposed between the substrate and the SFIC. The stacked integrated circuit assembly includes least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.

Abstract: The present invention provides an electronic device having more than two conductive layers that cross but not in contact with each other. At least one of the conductive layers comprises a width change part, a width of which changes in a length direction of at least one of the conductive layer. The width change part is formed away from a region of at least one of the conductive layers that crosses a neighboring conductive layer. The present invention also provides a flat panel display device that includes the electronic device described above and manufactured in accordance with the principles of the present invention. The electronic device of the present invention may comprise a thin film transistor.

Abstract: The invention relates to an optoelectronic component for converting electromagnetic radiation into an intensity-dependent photoelectric current. The component includes one substrate which is formed especially according to CMOS technology. The substrate has an integrated semiconductor structure and an optically active thin layer structure which is situated upstream in the direction of light incidence. The structure includes a layer of a transparent conductive material and at least one layer of semiconductor material, which are arranged on an isolating layer, inside which connection means are provided for establishing a connection between the optically active thin layer structure and the integrated semiconductor structure arranged on the substrate. The aim of the invention is to develop one such optoelectronic component in such a way that the electrical connection between the layer of transparent conductive material and an electrical potential connection can be established in a technically simple manner.

Abstract: A sensor device includes a sensor chip having a movable portion on one surface, a circuit chip laminated with the sensor chip to be opposite to the movable portion of the sensor chip, and a bump located between the sensor chip and the circuit chip. In the sensor device, the sensor chip and the circuit chip are electrically connected through the bump, and the movable portion of the sensor chip is separated from the circuit chip by a space using the bump. Accordingly, it can effectively restrict parasitic capacity of an electric connecting portion between both the chips from being changed by an impact. For example, the sensor device can be used as an angular velocity sensor device having a vibrator as the movable portion.

Abstract: An imaging apparatus capable of suppressing deterioration of image qualities and output properties is provided having one or more output circuits in series and a buffer circuit 6, and processing luminance signals from photodetectors to output image information, the buffer circuit performing impedance conversion on signals outputted from a final output circuit of the one or more output circuits, the final output circuit being a source follower circuit that has an active element and a current source circuit 5 which is inserted between a source terminal of the active element and a reference voltage terminal, wherein the current source circuit and the buffer circuit 6 are external to a solid-state image sensor 1 having the photodetectors, and a main part of the current source circuit 5 and a main part of the buffer circuit 6 are in a single package.

Abstract: A photoelectric conversion device comprises a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type serving as a photoelectric conversion element together with a part of the first semiconductor region; a gate electrode transferring electric carriers generated in the photoelectric conversion element to a third semiconductor region of the second conductivity type. Moreover, the photoelectric conversion device comprises an isolation region for electrically isolating the second semiconductor region from a fourth semiconductor region of the second conductivity type adjacent to the second semiconductor region. Wiring for applying voltage to the gate electrode is arranged on the isolation region. Here, a fifth semiconductor region of the second conductivity type having an impurity concentration lower than that of the fourth semiconductor region is provided between the fourth semiconductor region and the isolation region.

Abstract: A through hole P of this infrared sensor is formed in a position opposed to an adhesive layer AD. The through hole P, the bottom part thereof and an insulating film Pi formed therein is restrained from being deteriorated and damaged, in order to improve the characteristics of the infrared sensor, since the through hole P and the bottom part thereof are supported by the adhesive layer AD even when a pressure difference is generated between the inside and the outside in the space partitioned by the adhesive layer AD.

Abstract: A semiconductor device, including a first region (100) of semiconductor material of a first conductivity type. The semiconductor device comprises an elongated spatial element (111, 112, 113) of semiconductor material of a second conductivity type protruding into a first region (100) of semiconductor material of a first conductivity type; and a bias voltage supply adjusted in operation to fully deplete the spatial element from majority carriers of the second conductivity type. A semiconductor device according to the invention is resistant to smear, has a fill factor equal to one, and due to low total capacitance provides improved sensitivity.

Abstract: With this semiconductor device, the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained. A semiconductor device 1 has a semiconductor substrate 10, a wiring substrate 20, conductive bumps 30, and a resin 32. A CCD 12 and a thinned portion 14 are formed on semiconductor substrate 10. Electrodes 16 of semiconductor substrate 10 are connected via conductive bumps 30 to electrodes 22 of wiring substrate 20. Wiring substrate 20 has formed therein a groove portion 26a that surrounds a region opposing thinned portion 14 and groove portions 26b that extend to an exposed surface of wiring substrate 20 from groove portion 26a. Insulating resin 32 fills a gap between outer edge 15 of thinned portion 14 and wiring substrate 20 to reinforce the bonding strengths of conductive bumps 30.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: In a microminiature moving device that has disposed, on a single-crystal silicon substrate, movable elements (a movable rod 46, a movable comb electrode 49, etc.) displaceable in parallel to the substrate surface and stationary parts (a stationary part 40a, etc.), the stationary parts are fixedly secured to the single-crystal silicon substrate 61 with an insulating layer 62 sandwiched therebetween, and depressions 64 are formed in those surface regions of the single-crystal silicon substrate 61 where no stationary parts are present, and the movable parts are positioned above the depressions 64. The depressions 64 form gaps 50 large enough to prevent foreign bodies from causing troubles such as malfunction of the movable parts and shoring.