Abstract: A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer and a thick layer. The thick layer includes a plurality of insulating stripes that are separated from each other and that extend across a length between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands that are directly over individual ones of the plurality of insulating stripes.

Abstract: In some embodiments, the present invention is directed to processes for the combination of injecting charge in a material electrochemically via non-faradaic (double-layer) charging, and retaining this charge and associated desirable properties changes when the electrolyte is removed. The present invention is also directed to compositions and applications using material property changes that are induced electrochemically by double-layer charging and retained during subsequent electrolyte removal. In some embodiments, the present invention provides reversible processes for electrochemically injecting charge into material that is not in direct contact with an electrolyte. Additionally, in some embodiments, the present invention is directed to devices and other material applications that use properties changes resulting from reversible electrochemical charge injection in the absence of an electrolyte.

Abstract: An original wafer, typically silicon, has the form of a desired end PV wafer. The original may be made by rapid solidification or CVD. It has small grains. It is encapsulated in a clean thin film, which contains and protects the silicon when recrystallized to create a larger grain structure. The capsule can be made by heating a wafer in the presence of oxygen, or steam, resulting in silicon dioxide on the outer surface, typically 1-2 microns. Further heating creates a molten zone in space, through which the wafer travels, resulting in recrystallization with a larger grain size. The capsule contains the molten material during recrystallization, and protects against impurities. Recrystallization may be in air. Thermal transfer through backing plates minimizes stresses and defects. After recrystallization, the capsule is removed.

Abstract: A transformer comprises a substrate comprising a semiconductor material, a first conductor over the substrate, a second conductor over the substrate, and a magnetic layer over the substrate. The first conductor defines a generally spiral-shaped signal path having at least one turn. The second conductor defines a generally spiral-shaped signal path having at least one turn.

Abstract: A semiconductor device 1 includes a substrate 2 having on a main surface thereof a central area and a peripheral area which surrounds the central area and is exposed, a semiconductor layer 4 which is formed on the main surface of the substrate 2, is made of a material harder than the substrate 2, is in the shape of a mesa, and has a steep side over the exposed peripheral area, and an insulating film 12S provided on a side surface of the semiconductor layer 4.

Abstract: In the invention, a silica sol prepared by hydrolyzing and condensing a silane compound represented by the following formula: Si(OR1)4 or R2nSi(OR3)4-n wherein R1s, R2(s) and R3(s) may be the same or different when a plurality of them are contained in the molecule and each independently represents a linear or branched C1-4 alkyl group in the presence of a hydrophilic basic catalyst and a hydrophobic basic catalyst is used for a conventional porous-film forming composition.

Abstract: Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays.

Abstract: A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal.

Abstract: Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material.

Abstract: A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.

Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: A patterning method is provided. First, a mask layer and a plurality of first transfer patterns are sequentially formed on a target layer. Thereafter, a plurality of second patterns is formed in the gaps between the first transfer patterns. Afterwards, a plurality of third transfer patterns is formed, wherein each of the third transfer patterns is in a gap between a first transfer pattern and a second transfer pattern adjacent to the first transfer pattern. A portion of the mask layer is then removed, using the first transfer patterns, the second transfer patterns and third transfer patterns as a mask, so as to form a patterned mask layer. Further, a portion of the target layer is removed using the patterned mask layer as a mask.

Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. An epitaxial layer is formed on a semiconductor substrate. A semiconductor element is formed in the epitaxial layer. The semiconductor substrate is removed from the epitaxial layer.

Abstract: An isolated CMOS pair of transistors formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract: A method of making a memory device includes forming a first conductive electrode, forming an insulating structure over the first conductive electrode, forming a resistivity switching element on a sidewall of the insulating structure, forming a second conductive electrode over the resistivity switching element, and forming a steering element in series with the resistivity switching element between the first conductive electrode and the second conductive electrode, wherein a height of the resistivity switching element in a first direction from the first conductive electrode to the second conductive electrode is greater than a thickness of the resistivity switching element in second direction perpendicular to the first direction.

Abstract: A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an impurity region when impurities in the impurity region are thermally diffused in a semiconductor substrate. A second photoresist is formed on an insulation film. The second photoresist is formed to have second openings K2 on both sides of a P-type impurity region so that the second openings K2 partially overlap the P-type impurity region. The insulation film is etched off together with an underlying surface of the semiconductor substrate using the second photoresist as a mask so as to remove the P-type impurity region partially. Then, phosphorus ions (P+) are implanted into the surface of the semiconductor substrate in the etched-off regions using the second photoresist as a mask to form N-type impurity regions that are adjacent the P-type impurity region. After removing the second photoresist, the impurities in the P-type impurity region and the impurities in the N-type impurity region are thermally diffused.

Abstract: A semiconductor wafer assembly includes a disk-shaped semiconductor wafer including on a face side thereof a flat area having a plurality of semiconductor devices formed thereon and a beveled surface disposed around the flat surface, and a circular adhesive film bonded to a reverse side of the semiconductor wafer. The adhesive film is bonded only to an area of the reverse side which is coextensive with the flat area.

Abstract: An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse.

Abstract: Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example.

Abstract: Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.

Abstract: Static random access memory cells and methods of making static random access memory cells are provided. The static random access memory cells contain two non-planar pass-gate transistors, two non-planar pull-up transistors, two non-planar pull-down transistors. A portion of a fin of the non-planar pull-up transistor is electrically connected to a portion of a fin of the non-planar pull-down transistor by an assist-bar. The methods involve forming an assist-fin between fins of a non-planar pull-up transistor and a non-planar pull-down transistor and between gate electrodes, and widening a width of the assist-fin to form the assist-bar so that a portion of the fin of non-planar pull-up transistor is electrically connected to a portion of the fin of non-planar pull-down transistor via the assist-bar.

Abstract: A method of programming a transistor-based fuse structure is provided. The fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate.

Abstract: Acid-sensitive, developer-soluble bottom anti-reflective coating compositions are provided, along with methods of using such compositions and microelectronic structures formed thereof. The compositions preferably comprise a crosslinkable polymer dissolved or dispersed in a solvent system. The polymer preferably comprises recurring monomeric units having adamantyl groups. The compositions also preferably comprise a crosslinker, such as a vinyl ether crosslinking agent, dispersed or dissolved in the solvent system with the polymer. In some embodiments, the composition can also comprise a photoacid generator (PAG) and/or a quencher. The bottom anti-reflective coating compositions are thermally crosslinkable, but can be decrosslinked in the presence of an acid to be rendered developer soluble.

Abstract: A semiconductor device is provided that includes a substrate, a static random access memory (SRAM) unit cell formed in the substrate, a first metal layer formed over the substrate, the first metal layer providing local interconnection to the SRAM unit cell, a second metal layer formed over the first metal layer, the second metal layer including: a bit line and a complementary bit line each having a first thickness and a Vcc line disposed between the bit line and the complementary bit line, and a third metal layer formed over the second metal layer, the third metal layer including a word line having a second thickness greater than the first thickness.

Abstract: An apparatus includes a field-effect transistor (FET). The FET includes a region of first semiconductor and a layer of second semiconductor that is located on the region of the first semiconductor. The layer and region form a semiconductor heterostructure. The FET also includes source and drain electrodes that are located on one of the region and the layer and a gate electrode located to control a conductivity of a channel portion of the semiconductor heterostructure. The channel portion is located between the source and drain electrodes. The gate electrode is located vertically over the channel portion and portions of the source and drain electrodes.

Abstract: A method of forming patterns of a semiconductor device comprises providing a semiconductor substrate comprising a first region wherein first patterns are to be formed and a second region wherein second patterns are to be formed, each of the second patterns having a wider width than the first patterns, forming an etch target layer over the semiconductor substrate, forming first etch patterns over the etch target layer of the first and second regions, forming second etch patterns on both sidewalls of each of the first etch patterns, wherein the second etch pattern formed in the second region has a wider width than the second etch pattern formed in the first region, removing the first etch patterns, forming third etch patterns over the etch target layer of the second region, the third etch pattern overlapping part of the second pattern, and etching the etch target layer using the third etch patterns and the second etch patterns as an etch mask, to form the first and second patterns.

Abstract: Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction.

Abstract: A foldable microcircuit is initially a planar semiconductor wafer on which circuitry has been formed. The wafer is segmented into a plurality of tiles, and a plurality of hinge mechanisms are coupled between adjacent pairs of tiles such that the segmented wafer can be folded into a desired non-planar configuration having a high fill-factor and small gaps between tiles. The hinge mechanisms can comprise an organic material deposited on the wafer such that it provides mechanical coupling between adjacent tiles, with metal interconnections between tiles formed directly over the organic hinges, or routed between adjacent tiles via compliant bridges. Alternatively, the interconnection traces between tiles can serve as part or all of a hinge mechanism. The foldable microcircuit can be, for example, a CMOS circuit, with the segmented tiles folded to form, for example, a semi-spherical structure arranged to provide a wide FOV photodetector array.

Abstract: The present invention provides a dual triggered silicon controlled rectifier (DTSCR) including: a semiconductor substrate, an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region; a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second and the third P+ diffusion regions, utilized as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first and the third N+ diffusion regions, utilized as an N-type trigger node to receive a second trigger current or a second trigger voltage.

Abstract: A semiconductor device is made by providing an integrated passive device (IPD). Through-silicon vias (TSVs) are formed in the IPD. A capacitor is formed over a surface of the IPD by depositing a first metal layer over the IPD, depositing a resistive layer over the first metal layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the resistive and dielectric layers. The first metal layer and the resistive layer are electrically connected to form a resistor and the first metal layer forms a first inductor. A wafer supporter is mounted over the IPD using an adhesive material and a third metal layer is deposited over the IPD. The third metal layer forms a second inductor that is electrically connected to the capacitor and the resistor by the TSVs of the IPD. An interconnect structure is connected to the IPD.

Abstract: Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction process, spacer sidewalls formed between adjacent ends of the features come into substantial contact with one another, isolating the spaces between the features. In another embodiment, the features have a single width and an additional feature is located near ends of the features. Spacer sidewalls formed between adjacent features and the additional feature come into substantial contact with one another, isolating the spaces between the features.

Abstract: A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene.

Abstract: Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.

Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.

Abstract: Provided are a resistance random access memory including a resistance layer having a metal oxide and/or a metal ion dopant, which may be deposited at room temperature and which may have variable resistance characteristics, and a method of manufacturing the same.

Abstract: A composition for the organic hard mask includes a polyamic acid compound, and a method for forming a pattern is used in a manufacturing process of semiconductor devices by coating the composition for organic hard mask film on an underlying layer, and depositing a second hard mask film with a silicon nitride SiON film thereon to form a double hard mask film having an excellent etching selectivity, thereby obtaining a uniform pattern.

Abstract: A semiconductor memory device includes a word line interconnect layer having a plurality of word lines extending in a word line direction and a bit line interconnect layer having a plurality of bit lines extending in a bit line direction alternately stacked on a silicon substrate. A variable resistance film is disposed between the word line and the bit line. A first pin diode extending in the word line direction is provided between the word line and the variable resistance film, and a second pin diode extending in the bit line direction is provided between the bit line and the variable resistance film. A region of an upper surface of the pin diode other than an immediately underlying region of the variable resistance film is located lower than the immediately underlying region.

Abstract: In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.

Abstract: A method for fabricating a semiconductor device comprises forming a deposition structure including a first substrate, an insulating layer and a second substrate of a SOI substrate; etching the second substrate located in a boundary of cell and core regions and a peripheral region to form a line-type trench; filling an isolating film in the trench; removing the second substrate and the insulating layer of the peripheral region; performing a selective epitaxial growth (SEG) process using the first substrate exposed in the peripheral region to form an epitaxial layer; and performing a chemical mechanical polishing (CMP) process on the epitaxial layer. As a result, the method has a floating body effect to shorten a developing period and improve a process yield.

Abstract: A programmable anti-fuse element includes a substrate (224), an N-well (426) in the substrate, an electrically insulating layer (427) over the N-well, and a gate electrode (430) over the electrically insulating layer. The gate electrode has n-type doping so that the N-well is able to substantially contain within its boundaries a current generated following a programming event of the programmable anti-fuse element. In the same or another embodiment, a twice-programmable fuse element (100) includes a metal gate fuse (110) and an oxide anti-fuse (120) such as the programmable anti-fuse element just described.

Abstract: A chalcogenide alloy that optimizes operating parameters of an ovonic threshold switch includes an atomic percentage of arsenic in the range of 9 to 39, an atomic percentage of germanium in the range of 10 and 40, an atomic percentage of silicon in the range of 5 and 18, an atomic percentage of nitrogen in the range of 0 and 10, and an alloy of sulfur, selenium, and tellurium. A ratio of sulfur to selenium in the range of 0.25 and 4, and a ration of sulfur to tellurium in the alloy of sulfur, selenium, and tellurium is in the range of 0.11 and 1.

Abstract: Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such devices. Selectively controlling the temperature changes in different devices during a rapid thermal anneal is accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures. Alternatively, it is accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed.

Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-? dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-? dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric and the fully silicided layer.

Abstract: A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.

Abstract: A process for structuring at least one layer as well as an electrical component with structures from the layer are described. The invention states a process to generate at least one structured layer (10A), wherein a mask structure (20) with a first (20A) and second structure (20B) is generated on a layer (10) which is present on a substrate (5). Through this mask structure (20), the first layer (20A) is transferred onto the layer (10) using isotropic structuring processes, and the second structure (20B) is transferred onto the layer (10) using anisotropic structuring processes. The process as per the invention permits the generation of two structures (20A, 20B) in at least a single layer while using a single mask structure.

Abstract: One embodiment of the present invention is a thin film transistor, including: an insulating substrate; a gate electrode, a gate insulating layer and a semiconductor layer including an oxide, these three elements being formed over the insulating substrate in this order, and the gate insulating layer including: a lower gate insulating layer, the lower gate insulating layer being in contact with the insulating substrate and being an oxide including any one of the elements In, Zn or Ga; and an upper gate insulating layer provided on the lower gate insulating layer, the upper gate insulating layer comprising at least one layer; and a source electrode and a drain electrode formed on the semiconductor layer.

Abstract: A semiconductor wafer includes one or more back-illuminated image sensors each formed in a portion of the semiconductor wafer. One or more thinning etch stops are formed in other portions of the semiconductor wafer.

Abstract: Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.

Abstract: The surface of a material is textured and by exposing the surface to pulses from an ultrafast laser. The laser treatment causes pillars to form on the treated surface. These pillars provide for greater light absorption. Texturing and crystallization can be carried out as a single step process. The crystallization of the material provides for higher electric conductivity and changes in optical and electronic properties of the material. The method may be performed in vacuum or a gaseous environment. The gaseous environment may aid in texturing and/or modifying physical and chemical properties of the surfaces. This method may be used on various material surfaces, such as semiconductors, metals and their alloys, ceramics, polymers, glasses, composites, as well as crystalline, nanocrystalline, polycrystalline, microcrystalline, and amorphous phases.

Abstract: A semiconductor device comprises an integrated circuit formed on a substrate with a signal interface and at least one isolator capacitor. The integrated circuit comprises a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate, a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics, and a thick metal layer formed on the thick passivation layer. The thick passivation layer has a thickness selected to be greater than the isolation thickness whereby testing for defects is eliminated. The one or more isolator capacitors comprise the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator.