Abstract: To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms a bonding plane, a barrier layer formed of an insulating material containing nitrogen, a relief layer which is formed of an insulating material that includes nitrogen at less than 20 at. % and hydrogen at 1 at. % to 20 at. %, and an insulating layer containing a halogen, between a supporting substrate and a single-crystal semiconductor layer. The semiconductor device includes the above-described structure at least partially, and a gate insulating layer formed by a microwave plasma CVD method using SiH4 and N2O as source gases is in contact with the single-crystal semiconductor layer.

Abstract: Nanowire-based opto-electronic devices including nanowire lasers, photodetectors and semiconductor optical amplifiers are disclosed. The devices include nanowires grown from single crystal and/or non-single surfaces. The semiconductor optical amplifiers include nanowire arrays that act as ballast lasers to amplify a signal carried by a signal waveguide. Embodiments of the nanowire lasers and photodetectors include horizontal and vertical nanowires that can provide different polarizations.

Abstract: Photovoltaic cells are fabricated in which the compositions of the light-absorbing layer and the electron-accepting layer are selected such that at least one side of the junction between these two layers is substantially depleted of charge carriers, i.e., both free electrons and free holes, in the absence of solar illumination. In further aspects of the invention, the light-absorbing layer is comprised of dual-shell passivated quantum dots, each having a quantum dot core with surface anions, an inner shell containing cations to passivate the core surface anions, and an outer shell to passivate the inner shell anions and anions on the core surface.

Abstract: Methods for manufacturing a semiconductor device with alternating P type and N type semiconductor conductive regions are disclosed. One method includes forming a trench in an N type epitaxial layer; forming carbon-contained silicon layer on sidewalls of the trench; and filling the trench with P type semiconductor layer. In another method, the carbon-contained silicon layer is replaced by a carbon film formed by diffusion process. The carbon-contained silicon layer or the carbon film can effectively inhibit the diffusion of P type impurities into the N type semiconductor layers. Further, a semiconductor device having carbon-contained layer or carbon film formed between P type and N type conductive layers is also disclosed.

Abstract: A substrate configured to support at least one electronic or electromechanical component and one or more nano-elements, formed with a base support, with a catalytic system, with a barrier layer, and with a layer configured to receive the electronic or electromechanical component, in single-crystal Si or in Ge or in a mixture of these materials. The catalytic system lies on the base support without any contact with the layer configured to receive electronic or electromechanical component and the barrier layer is sandwiched between the catalytic system and the layer configured to receive the electronic or electromechanical component. This barrier layer is without any contact with the base support.

Abstract: The present disclosure relates to a semiconductor device that has a first semiconductor structure that is grown to form a non-planar growth surface. The non-planar growth surface is formed from multiple facets and provides a defined contour. The defined contour may include, but is not limited to a corrugated contour or a pyramidal contour. A second semiconductor structure is grown over the non-planar growth surface of the first semiconductor structure, and as such, the second semiconductor structure is non-planar and follows the defined contour of the non-planar growth surface of the first semiconductor structure. The first and second semiconductor structures may form the foundation for various types of electrical and optoelectrical semiconductor devices, such as diodes, transistors, thyristors, and the like.

Abstract: A thermoelectric structure for cooling an integrated circuit (IC) chip comprises a first type superlattice layer formed on top of the IC chip connected to a first voltage, and a second type superlattice layer formed on the bottom of the IC chip connected to a second voltage, the second voltage being different from the first voltage, wherein an power supply current flows through the first and second type superlattice layer for cooling the IC chip.

Abstract: A voltage-controlled switch (100) comprises a first electrode (10), a second electrode (20), a switching junction (30) situated between the first electrode and the second electrode, a conducting channel (60) extending from adjacent to the origin through the switching junction and having a channel end situated near the second electrode, and a layer of dopants (40) situated adjacent to an interface between the switching junction and the second electrode, wherein the dopants are capable of being activated to form switching centers (50).

Abstract: The semiconductor layer structure includes an active layer and a superlattice composed of stacked layers of III-V compound semiconductors of a first and at least one second type. Adjacent layers of different types in the superlattice differ in composition with respect to at least one element. The layers have predefined layer thicknesses, such that the layer thicknesses of layers of the first type and of the layers of the second type increase from layer to layer with increasing distance from an active layer. An increasing layer thickness within the layers of the first and the second type is suitable for adapting the electrical, optical and epitaxial properties of the superlattice to given requirements in the best possible manner.

Abstract: A semiconductor layer (100) according to the present invention includes a top surface (100o), a bottom surface (100u) and a side surface (100s). In a portion of the side surface (100s) which is in the vicinity of a border with the top surface (100o), a tangential line (T1) to the portion is inclined with respect to the normal to the bottom surface (100u). In a certain portion of the side surface (100s) which is farther from the top surface (100o) than the portion in the vicinity of the border, an angle made by a tangential line (2) to the certain portion and a plane defined by the bottom surface (100u) is larger than an angle made by the tangential line (T1) to the portion in the vicinity of the border and the plane defined by the bottom surface (100u).

Abstract: A semiconductor device includes an epitaxial pattern that fills a depression region formed at a semiconductor substrate of one side of a gate pattern. The gate pattern is disposed on a body located at one side of the depression region. The sidewall of the depression region adjacent to the body includes inner surfaces of tapered recesses that taper toward the body, or has an inner surface of a taper recess and a vertical lower sidewall.

Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Abstract: An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed.

Abstract: A reconfigurable device and a method of creating, erasing, or reconfiguring the device are provided. At an interface between a first insulating layer and a second insulating layer, an electrically conductive, quasi one- or zero-dimensional electron gas is present such that the interface presents an electrically conductive region that is non-volatile. The second insulating layer is of a thickness to allow metal-insulator transitions upon the application of a first external electric field. The electrically conductive region is subject to erasing upon application of a second external electric field.

Abstract: A phase modulation waveguide structure includes one of a semiconductor and a semiconductor-on-insulator substrate, a doped semiconductor layer formed over the one of a semiconductor and a semiconductor-on-insulator substrate, the doped semiconductor portion including a waveguide rib protruding from a surface thereof not in contact with the one of a semiconductor and a semiconductor-on-insulator substrate, and an electrical contact on top of the waveguide rib. The electrical contact is formed of a material with an optical refractive index close to that of a surrounding oxide layer that surrounds the waveguide rib and the electrical contact and lower than the optical refractive index of the doped semiconductor layer. During propagation of an optical mode within the waveguide structure, the electrical contact isolates the optical mode between the doped semiconductor layer and a metal electrode contact on top of the electrical contact.

Abstract: A semiconductor device of the present invention has a first-conductivity-type substrate having second-conductivity-type base regions exposed to a first surface thereof; trench gates provided to a first surface of the substrate; first-conductivity-type source regions formed shallower than the base regions; a plurality of second-conductivity-type column regions located between two adjacent trench gates in a plan view, while being spaced from each other in a second direction normal to the first direction; the center of each column region and the center of each base contact region fall on the center line between two trench gates; and has no column region formed below the trench gates.

Abstract: In a method of manufacturing a semiconductor device, an electrode layer is formed on a surface of a semiconductor substrate, and a resin insulation layer is formed on the surface of the semiconductor substrate so that the electrode layer can be covered with the resin insulation layer. A tapered hole is formed in the insulation layer by using a tool bit having a rake angle of zero or a negative value. The tapered hole has an opening defined by the insulation layer, a bottom defined by the electrode layer, and a side wall connecting the opening to the bottom.

Abstract: A circuit board having a graphene circuit according to the present invention includes: a base substrate; a patterned aluminum oxide film formed on the base substrate, the patterned aluminum oxide film having an average composition of Al2-xO3+x (where x is 0 or more), the patterned aluminum oxide film having a recessed region whose surface has one or more cone-shaped recesses therein; a graphene film preferentially grown only on the patterned aluminum oxide film, the graphene film having one or more graphene atomic layers, the graphene film having a contact region that covers the recessed region, the graphene film growing parallel to a flat surface of the recessed region and parallel to an inner wall surface of each cone-shaped recess of the recessed region; and a patterned metal film, a part of the patterned metal film covering and having electrical contact with the contact region, the patterned metal film filling each recess covered by the graphene film.

Abstract: A semiconductor device is provided with a porous structure layer formed by silicone resin between a substrate and a semiconductor element. Alternatively, a porous layer having a density of 0.7 g/cm3 or less, formed by a compound obtained by hydrolyzing and condensing at least one type of alkoxysilane selected from a group consisting of monoalkoxysilane, dialkoxysilane, and trialkoxysilane, and tetraalkoxysilane is provided between the substrate and the semiconductor element. As a further alternative, an adhesion layer formed by a compound obtained by hydrolyzing and condensing an alkoxysilane is provided on a resin substrate, and a porous layer having a density of 0.7 g/cm3 or less, formed by a compound obtained by hydrolyzing and condensing an alkoxysilane, is provided on the adhesion layer.

Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.

Abstract: A virtual substrate includes a handle support and a strain-relieved single crystalline layer on the handle support. A method of making the virtual substrate includes growing a coherently-strained single crystalline layer on an initial growth substrate, removing the initial growth substrate to relieve the strain on the single crystalline layer, and applying the strain-relieved single crystalline layer on a handle support.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.

Abstract: A Zener diode is fabricated on a semiconductor substrate having semiconductor material thereon. The Zener diode includes a first well region having a first conductivity type, formed in the semiconductor material. The Zener diode also includes a first region having a second conductivity type, formed in the first well region (the second conductivity type is opposite the first conductivity type). The Zener diode also includes a second region having the first conductivity type, wherein the second region is formed in the first well region and overlying the first region. An electrode is formed in the first region, and the electrode is electrically coupled to the second region.

Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. This method can include dicing along a predetermined line a laminated substrate which has a first substrate and a second substrate, one of which is made of a semiconductor substrate, mutually adhered with an adhesive layer interposed between them. The dicing process includes irradiating a laser beam to the adhesive layer along the dicing line to form scribe lines corresponding to the dicing line on the first and second substrates. And, the dicing process includes applying an impact to the laminated substrate to divide along the scribe lines.

Abstract: A method for producing a hybrid substrate, including a support substrate, a continuous buried insulator layer and, on this continuous layer, a hybrid layer including alternating zones of a first material and at least one second material, wherein these two materials are different by their nature and/or their crystallographic characteristics. The method forms a hybrid layer, including alternating zones of first and second materials, on a homogeneous substrate, assembles this hybrid layer, the continuous insulator layer and the support substrate, and eliminates a part at least of the homogeneous substrate, before or after the assembling.

Abstract: A memory cell includes a first electrode, a second electrode, and phase-change material including a first portion contacting the first electrode, a second portion contacting the second electrode, and a third portion between the first portion and the second portion. A width of the third portion is less than a width of the first portion and a width of the second portion.

Abstract: A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.

Abstract: Silicon wafers doped with nitrogen, hydrogen and carbon, have a plurality of voids, wherein 50% or more of the total number of voids are bubble-like shaped aggregates of voids; a V1 region having a void density of over 2×104/cm3 and below 1×105/cm3 which occupies 20% or less of the total area of the silicon wafer; a V2 region having a void density of 5×102 to 2×104/cm3 which occupies 80% or more of the total area of said silicon wafer; and a bulk micro defect density which is 5×108/cm3 or more, have excellent GOI characteristics and a high C-mode pass rate. The wafers are cut from a single crystal pulled by a method in which carbon, nitrogen, and hydrogen dopants are controlled, and the crystal is subjected to rapid cooling.

Abstract: A method for processing a sample using an electrically neutral reactive cluster is provided. The surface of a sample is processed by jetting out a mixed gas that is composed of a reactive gas and a gas with a boiling point lower than that of the reactive gas from a gas jetting part of a vacuum process room in which the sample is placed by a pressure in a range in which the mixed gas is not liquefied, in a predetermined direction, while adiabatically-expanding the mixed gas, thereby generating a reactive cluster and jetting the reactive cluster against the sample in the vacuum process room.

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Abstract: A process for production of a silicon ingot, by which a silicon ingot exhibiting a low resistivity even in the top portion can be produced. The process for the production of a silicon ingot comprises includes withdrawing a silicon seed crystal (13) from a silicon melt (11) to grow a silicon single crystal (12), with the silicon seed crystal (13) and the silicon melt (11) containing dopants of the same kind.

Abstract: Provided are a porous nanostructure and a method of manufacturing the same. The porous nanostructure includes a plurality of pores disposed on an exterior surface of a nanostructure, wherein at least a portion of the plurality of pores extend inside the nanostructure.

Abstract: The present disclosure relates to a semiconductor nanostructure. The semiconductor nanostructure includes a substrate and at least one ridge. The substrate includes a first crystal plane and a second crystal plane perpendicular to the first crystal plane. The at least one ridge extends from the first crystal plane along a crystallographic orientation of the second crystal plane. A width of cross section at a position of half the height of the at least one ridge is less than 17 nm. The semiconductor nanostructure is a patterned structure which can lead to generate a quantum confinement effect, such that the impurity scattering phenomenon is reduced.

Abstract: A rectifying antenna device is disclosed. The device comprises a pair of electrode structures, and at least one nanostructure diode contacting at least a first electrode structure of the pair and being at least in proximity to a second electrode structure of the pair. At least one electrode structure of the pair receives AC radiation, and the nanostructure diode(s) at least partially rectifies a current generated by the AC radiation.

Abstract: A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone.

Abstract: Disclosed herein is a quantum dot phosphor for light emitting diodes, which includes quantum dots and a solid substrate on which the quantum dots are supported. Also, a method of preparing the quantum dot phosphor is provided. Since the quantum dot phosphor of the current invention is composed of the quantum dots supported on the solid substrate, the quantum dots do not aggregate when dispensing a paste obtained by mixing the quantum dots with a paste resin for use in packaging of a light emitting diode. Thereby, a light emitting diode able to maintain excellent light emitting efficiency can be manufactured.

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract: The invention provides for a nanostructure, or an array of such nanostructures, each comprising a rough surface, and a doped or undoped semiconductor. The nanostructure is an one-dimensional (1-D) nanostructure, such a nanowire, or a two-dimensional (2-D) nanostructure. The nanostructure can be placed between two electrodes and used for thermoelectric power generation or thermoelectric cooling.

Abstract: A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.

Abstract: A semiconductor device includes first semiconductor zones of a first conductivity type having a first dopant species of the first conductivity type and a second dopant species of a second conductivity type different from the first conductivity type. The semiconductor device also includes second semiconductor zones of the second conductivity type including the second dopant species. The first and second semiconductor zones are alternately arranged in contact with each other along a lateral direction extending in parallel to a surface of a semiconductor body. One of the first and second semiconductor zones constitute drift zones and a diffusion coefficient of the second dopant species is at least twice as large as the diffusion coefficient of the first dopant species. A concentration profile of the first dopant species along a vertical direction perpendicular to the surface of the semiconductor body includes at least two maxima.

Abstract: The present invention provides nanowires and nanoribbons that are well suited for use in thermoelectric applications. The nanowires and nanoribbons are characterized by a periodic compositional longitudinal modulation. The nanowires are constructed using lithographic techniques from thin semiconductor membranes, or “nanomembranes.

Abstract: A hyperbranched polymer synthesizing method employs living radical polymerization of a monomer in the presence of a metal catalyst.

Abstract: Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source region and a drain region. In some embodiments, the dual fins may be formed by forming a trench with fin structures on opposite sides in a protruding region of a substrate. The dual fins may be useful in forming single-gate, double-gate or triple-gate fin-PET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract: A two-terminal ESD protection structure formed by an arrangement of five adjacent semiconductor regions (112, 114, 116, 118, and 120) of alternating conductivity type provides protection against both positive and negative ESD voltages. The middle semiconductor region electrically floats. When the two terminals (A and K) of the ESD protection structure are subjected to an ESD voltage, the structure goes into operation by triggering one of its two inherent thyristors (170 and 180) into a snap-back mode that provides a low impedance path through the structure for discharging the ESD current.

Abstract: Systems and methods of manufacturing wafers are disclosed using a low EPD crystal growth process and a wafer annealing process are provided resulting in III-V/GaAs wafers that provide higher device yields from the wafer. In one exemplary implementation, there is provided a method of manufacturing a group III based material with a low etch pit density (EPD). Moreover, the method includes forming polycrystalline group III based compounds, and performing vertical gradient freeze crystal growth using the polycrystalline group III based compounds. Other exemplary implementations may include controlling temperature gradient(s) during formation of the group III based crystal to provide very low etch pit density.

Abstract: A film comprised of semiconductor nanocrystals having an aspect ratio less than 3:1 and a diameter greater than 10 nanometers, wherein the film has less than 5% by volume of organic material.

Abstract: A key hole structure and method for forming a key hole structure to form a pore in a memory cell. The method includes forming a first dielectric layer on a semiconductor substrate having an electrode formed therein, forming an isolation layer on the first dielectric layer, forming a second dielectric layer on the isolation layer, and forming a planarization stop layer on the second dielectric layer. The method further includes forming a via to extend to the first dielectric layer and recessing the isolation layer and the stop layer with respect to the second dielectric layer, depositing a conformal film within via and over the stop layer, forming a key hole within the conformal film at a center region of the via such that a tip of the key hole is disposed at an upper surface of the second dielectric layer, and planarizing the conformal film to the stop layer.

Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.