Abstract: Insulated gate bipolar conduction transistors (IBCTs) are provided. The IBCT includes a drift layer having a first conductivity type. An emitter well region is provided in the drift layer and has a second conductivity type opposite the first conductivity type. A well region is provided in the drift layer and has the second conductivity type. The well region is spaced apart from the emitter well region. A space between the emitter well region and the well region defines a JFET region of the IBCT. An emitter region is provided in the well region and has the first conductivity type and a buried channel layer is provided on the emitter well region, the well region and the JFET region and has the first conductivity type. Related methods of fabrication are also provided.

Abstract: A power transistor. One embodiment provides a power transistor having a first terminal, a second terminal and a control terminal. A support layer is formed of a first material having a first bandgap. An active region is formed of a second material having a second bandgap wider than the first bandgap, and is disposed on the support layer. The active region is arranged to form part of a current path between the first and second terminal in a forward mode of operation. The active region includes at least one pn-junction.

Abstract: An n-type buffer region 6 is arranged between an n? drift region 1 and a p-type collector region 7, and has a higher impurity concentration than n? drift region 1 Assuming that ? represents the ratio (WTA/WTB) between WTA expressed as: WTA = 2 ? ? s ? ? 0 ? V qNd and the thickness WTB of the drift region held between the base region and the buffer region, the ratio (DC/DB) of the net dose DC of the collector region with respect to the net dose DB of the buffer region is at least ?. Thus, a semiconductor device capable of ensuring a proper margin of SCSOA resistance can be obtained.

Abstract: A semiconductor device has a drift region (20) (third semiconductor region) of an n-type (first conductivity type); a body region (50) (second semiconductor region) of a p-type (second conductivity type) provided on the drift region (20); an emitter region (60) (first semiconductor region) of the n-type formed in the top surface of the body region (50) and separated from the drift region (20) by the body region (50); a trench (14) extending from the top surface of the emitter region (60) through the body region (50) into the drift region (20); a trench gate electrode (13) filled in the trench (14); and a semiconductor region (70) (fourth semiconductor region) of the p-type formed in contact with side faces of the trench protruding into the drift region (20). Therefore, the semiconductor device can suppress a surge voltage at turn-off, and can be produced easily.

Abstract: A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n? drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure.

Abstract: A power semiconductor device having a low loss and a high reliability and a power conversion device using the power semiconductor device are provided. In the power semiconductor device, a plurality of MOS type trench gates are positioned to be spaced by at-least two types of intervals therebetween, a low-resistance floating n+ layer is positioned on a main surface of a semiconductor substrate adjacent to a floating p layer positioned between the adjacent MOS type trench gates having the broad interval to achieve consistency between a low output value and a high breakdown resistance.

Abstract: A power semiconductor device is provided, that realizes high-speed turnoff and soft switching at the same time, includes n-type main semiconductor layer including lightly doped n-type semiconductor layer and extremely lightly doped n-type semiconductor layer arranged alternately and repeatedly between p-type channel layer and field stop layer and in parallel to the first major surface of n-type main semiconductor layer. Extremely lightly doped n-type semiconductor layer is doped more lightly than lightly doped n-type semiconductor layer. Lightly doped n-type semiconductor layer prevents a space charge region from expanding at the time of turnoff. Extremely lightly doped n-type semiconductor layer expands the space charge region at the time of turnoff to eject electrons and holes quickly further to realize high-speed turnoff.

Abstract: A semiconductor power component using flat conductor technology includes a vertical current path through a semiconductor power chip. The semiconductor power chip includes at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a flat conductor chip island of a flat conductor leadframe and the top side electrode is electrically connected to an internal flat conductor of the flat conductor leadframe via a connecting element. The connecting element includes a bonding strip extending from the top side electrode to the internal flat conductor and further includes, on the top side of the bonding strip, bonding wires extending from the top side electrode to the internal flat conductor.

Abstract: A plasma display apparatus which in its driving circuit mounts at least one of IGBTs having diodes built-in which are reverse conducting in a driving device which supplies a light emitting current and IGBTs having diodes built-in which have a reverse blocking function in a driving device which collects and charges the power.

Abstract: SiC-IGBTs, which have an inversion-type channel with high channel resistance and have high on-voltage due to an influence from the surface state of the interface between a gate insulating film and a base layer, are required to decrease the on-voltage. An embedded collector region is partially formed in a base layer which is formed on an emitter layer of a SiC semiconductor. A channel layer is formed on the base layer and the embedded collector region to constitute an accumulation-type channel. Consequently, at on time, holes are accumulated in the upper layer portion of the channel layer so that a low-resistant channel is formed. Current by the holes flows to the emitter layer through a channel from the collector region and becomes a base current for an npn transistor composed of the embedded collector region, the base region and the emitter region.

Abstract: A semiconductor device includes: a collector layer of a first conductivity type; a semiconductor area of a second conductivity type formed on the collector layer; a base layer of the first conductivity type formed on the semiconductor area; an emitter layer of the second conductivity type formed in an island shape on the base layer; an insulation film formed on the semiconductor area, the base layer and the emitter layer; a gate electrode formed on the insulation film; an emitter electrode formed on the base layer and the emitter layer; a collector electrode formed on the collector layer; and a crystal defect area of the first conductivity type locally formed in the collector layer. A position of a defect concentration peak of the crystal defect area is in the collector layer. An edge of the crystal defect area adjoins the semiconductor area or is located in the semiconductor area.

Abstract: A bipolar high voltage/power semiconductor device having a low voltage terminal and a high voltage terminal is disclosed. The bipolar high voltage/power semiconductor is a vertical insulated gate bipolar transistor with injection efficiency adjustment formed by highly doped n+ islands in a p+ anode layer. The device has a vertical drift region of a first conductivity type and having vertical first and second ends. In one example, a region of the second conductivity type is provided at the second end of the vertical drift region connected directly to the vertical high voltage terminal. In another example, a vertical buffer region of the first conductivity type is provided at the vertical second end of the vertical drift region and a vertical region of a second conductivity type is provided on the other side of the vertical buffer region and connected to the vertical high voltage terminal.

Abstract: There is provided a semiconductor device in which an amount of fluctuations in output capacitance and feedback capacitance is reduced. In a trench-type insulated gate semiconductor device, a width of a portion of an electric charge storage layer in a direction along which a gate electrode and a dummy gate are aligned is set to be at most 1.4 ?m.

Abstract: A semiconductor device includes an active region with a vertical drift path of a first conduction type and with a near-surface lateral well of a second, complementary conduction type. In addition, the semiconductor device has an edge region surrounding the active region. This edge region has a variable lateral doping material zone of the second conduction type, which adjoins the well. A transition region in which the concentration of doping material gradually decreases from the concentration of the well to the concentration at the start of the variable lateral doping material zone is located between the lateral well and the variable lateral doping material zone.

Abstract: A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion sticking out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.

Abstract: A semiconductor device has a heavily doped substrate and an upper layer with doped silicon of a first conductivity type disposed on the substrate, the upper layer having an upper surface and including an active region that comprises a well region of a second, opposite conductivity type. An edge termination zone has a junction termination extension (JTE) region of the second conductivity type, the region having portions extending away from the well region and a number of field limiting rings of the second conductivity type disposed at the upper surface in the junction termination extension region.

Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 ?m and no greater than 250 ?m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.

Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*ND*WN=q*NA*WP and a punch through condition of WP<2*WD*[ND/(NA+ND)] where ND and WN represent the doping concentration and the thickness of the N type layers 160, while NA and WP represent the doping concentration and thickness of the P type layers; WD represents the depletion width; and q represents an electron charge, which cancel out. This device allows for a near ideal rectangular electric field profile at breakdown voltage with sawtooth like ridges.

Abstract: An integrated circuit device includes a semiconductor body fitted with a first electrode and a second electrode on opposite surfaces. A control electrode on an insulating layer controls channel regions of body zones for a current flow between the two electrodes. A drift section adjoining the channel regions comprises drift zones and charge compensation zones. A part of the charge compensation zones includes conductively connected charge compensation zones electrically connected to the first electrode. Another part includes nearly-floating charge compensation zones, so that an increased control electrode surface has a monolithically integrated additional capacitance CZGD in a cell region of the semiconductor device.

Abstract: In a vertical semiconductor device including a first base layer of a first conductivity type, second base layers of a second conductivity type, emitter layer of the first conductive type and gate electrodes which are formed at one main surface of the first base layer and including a buffer layer of the first conductivity type, a collector layer of the second conductivity type and a collector electrode which are formed at the other main surface of the first base layer, an electric field relaxing structure selectively formed outside from the second base layers and the collector layer is formed expect the region below the electric field relaxing structure.

Abstract: Insulated gate bipolar conduction transistors (IBCTs) are provided. The IBCT includes a drift layer having a first conductivity type. An emitter well region is provided in the drift layer and has a second conductivity type opposite the first conductivity type. A well region is provided in the drift layer and has the second conductivity type. The well region is spaced apart from the emitter well region. A space between the emitter well region and the well region defines a JFET region of the IBCT. An emitter region is provided in the well region and has the first conductivity type and a buried channel layer is provided on the emitter well region, the well region and the JFET region and has the first conductivity type. Related methods of fabrication are also provided.

Abstract: A semiconductor device includes a semiconductor substrate having a main surface and a semiconductor element having an insulated gate field effect portion formed in the semiconductor substrate. The semiconductor element includes an n? region, an n-type source region, a p-type base region, an n+ region, and a gate electrode. The n? region and the n-type source region are formed in the main surface. The p-type base region is formed in the main surface adjacent to the n-type source region. The n+ region is formed in the main surface adjacent to the p-type base region and opposed to the n-type source region with the p-type base region being interposed, and has an impurity concentration higher than the n? region. The n? region is formed in the main surface adjacent to the p-type base region and to the n+ region.

Abstract: A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and t

Abstract: A vertical and trench type insulated gate MOS semiconductor device includes a plurality of regions each being provided between adjacent ones of a plurality of the straight-line-like trenches arranged in parallel and forming a surface pattern of a plurality of straight lines. A plurality of first inter-trench surface regions are provided, each with an n+-type emitter region and a p+-type body region formed thereon, and the surfaces of regions are alternately arranged along the trench in the longitudinal direction thereof with an emitter electrode being in common contact with both of the surfaces of the n+-type emitter region and the p+-type body region. A plurality of second inter-trench surface regions are provided each of which is formed along the trench in the longitudinal direction thereof with one of the surface of the p base region and the surface of the n-type semiconductor substrate.

Abstract: Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n? drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel.

Abstract: A semiconductor substrate has a trench in a first main surface. An insulated gate field effect part includes a gate electrode formed in the first main surface. A potential fixing electrode fills the trench and has an expanding part expanding on the first main surface so that a width thereof is larger than the width of the trench. An emitter electrode is formed on the first main surface and insulated from the gate electrode electrically and connected to a whole upper surface of the expanding part of the potential fixing electrode. Thus, a semiconductor device capable of enhancing reliability in order to prevent an aluminum spike from generating and a manufacturing method thereof can be provided.

Abstract: A semiconductor device includes: a semiconductor substrate; an IGBT cell; and a diode cell. The substrate includes a first layer on a first surface, second and third layers adjacently arranged on a second surface of the substrate and a fourth layer between the first layer and the second and third layers. The first layer provides a drift layer of the IGBT cell and the diode cell. The second layer provides a collector layer of the IGBT cell. The third layer provides one electrode connection layer of the diode cell. A resistivity ?1 and a thickness L1 of the first layer, a resistivity ?2 and a thickness L2 of the fourth layer, and a half of a minimum width W2 of the second layer on a substrate plane have a relationship of (?1/?2)×(L1·L2/W22)<1.6.

Abstract: In an embodiment, a integrated semiconductor device includes a first Vertical Junction Field Effect Transistor (VJFET) having a source, and a gate disposed on each side of the first VJFET source, and a second VJFET transistor having a source, and a gate disposed on each side of the second VJFET source. At least one gate of the first VJFET is separated from at least one gate of the second VJFET by a channel. The integrated semiconductor device also includes a Junction Barrier Schottky (JBS) diode positioned between the first and second VJFETs. The JBS diode comprises a metal contact that forms a rectifying contact to the channel and a non-rectifying contact to at least one gate of the first and second VJFETs, and the metal contact is an anode of the JBS diode.

Abstract: An SOI device comprises an isolation trench defining a vertical drift zone, a buried insulating layer to which the isolation trench extends, and an electrode region for emitting charge carriers that is formed adjacent to the insulating layer and that is in contact with the drift zone. The electrode region comprises first strip-shaped portions having a first type of doping and second strip-shaped portions having a second type of doping that is inverse to the first type of doping. A first sidewall doping of the first type of doping is provided at a first sidewall of the isolation trench and a second sidewall doping of the second type of doping is provided at a second sidewall of the isolation trench. The first strip-shaped portions are in contact with the first sidewall doping and the second strip-shaped portions are in contact with the second sidewall doping.

Abstract: A punch-through type IGBT generally has a thick p++-type collector layer. Therefore, the FWD need be externally attached to the IGBT when the IGBT is used as a switching element in an inverter circuit for driving a motor load, and thus the number of processes and components increases. In the invention, trenches are formed penetrating through a collector layer and reaching a buffer layer. A collector electrode is formed in the trenches, too. With this structure, a current path is formed between an emitter electrode and the collector electrode without through the collector layer and functions as the FWD.

Abstract: The present invention provides a vertical tapered dielectric high-voltage device (10) in which the device drift region is depicted by action of MOS field plates (30) formed in vertical trenches. The high-voltage device comprises: a substrate (32); a silicon mesa (20) formed on the substrate and having a stripe geometry, wherein the silicon mesa provides a drift region having a constant doping profile; a recessed gate (22) and source (SN) formed on the silicon mesa; a trench (26) adjacent each side of the silicon mesa; and a metal-dielectric field plate structure (12) formed in each trench; wherein each metal-dielectric field plate structure comprises a dielectric (28) and a metal field plate (30) formed over the dielectric, and wherein a thickness of the dielectric increases linearly through a depth of the trench to provide a constant longitudinal electric field.

Abstract: In a nitride semiconductor based bipolar transistor, a contact layer formed so as to contact an emitter layer is composed of n-type InAlGaN quaternary mixed crystals, the emitter layer and the contact layer are selectively removed so that the barrier height with the emitter formed thereon is small, and the ohmic electrode contact resistance can be lowered on the InAlGaN quaternary mixed crystals, for example, so that a WSi emitter electrode becomes an eave. A base electrode is formed by a self-aligned process using the emitter electrode as a mask. By such a configuration, the distance between the emitter and the edge of the base electrode is sufficiently shortened, and the base resistance can be lowered. As a result, a bipolar transistor having favorable high-frequency characteristics can be realized.

Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

Abstract: In an insulated gate semiconductor device (1) having an N? type base region (11), P+ type collector regions (12), P type base regions (13), and N+type emitter regions (14), an N+ type collector-short region (15) which extends toward the N? type base region (11) farther than the P+ type collector regions (12) is formed in the lower surface of the N? type base region (11), and a P+ type semiconductor region (16) is formed between the N+ type collector-short region (15) and the N? type base region (11).

Abstract: The semiconductor device has a collector electrode, a p+ collector region formed on the collector electrode, an n? drift region formed on the collector region, a p? body region formed on the drift region, and a plurality of n+ emitter regions formed within the body region. The emitter regions are connected to an emitter electrode. A plurality of trench gate electrodes is formed within the body region. Each trench gate electrode opposes, via an insulating layer, a portion of the body region separating the drift region and the emitter region. The body region is divided into a plurality of body sections, and the body sections are classified into two groups. One group has the emitter region within the body section, and the other group has no emitter region within the body section. A plurality of first trenches is formed within the body section having no emitter region. A p+ contact region is formed between the first trench and the trench gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor layer on a major surface thereof. The semiconductor layer is formed to extend in the vertical direction of the major surface of the semiconductor substrate. A stress application layer is provided on either side of the semiconductor layer and applies a stress to the semiconductor layer.

Abstract: A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n? drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure.

Abstract: Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body region, a gate insulator region, a plurality of source regions disposed at the surface of the body region proximate to the periphery of the gate insulator region. A first portion of the gate region and the gate oxide region are formed as parallel elongated structures. A second portion of the gate region and the oxide region are formed as normal-to-parallel elongated structures. A portion of the gate and drain overlap region are selectively blocked by the body region, resulting in lower overall gate to drain capacitance.

Abstract: A vertical power semiconductor component, e.g. a diode or an IGBT, in which there are formed, on the rear side of a substrate, a rear side emitter or a cathode emitter and, over that, a rear side metal layer that at least partly covers the latter, is defined by the fact that, in the edge region of the component, provision is made of injection attenuation means for reducing the charge carrier injection from the rear side emitter or the cathode emitter into said edge section.

Abstract: A semiconductor device (10) includes a semiconductor die (20) and an inductor (30, 50) formed with a bonding wire (80) attached to a top surface (21) of the semiconductor die. The bonding wire is extended laterally a distance (L30, L150) greater than its height (H30, H50) to define an insulating core (31, 57). In one embodiment, the inductor is extended beyond an edge (35, 39) of the semiconductor die to reduce loading.

Abstract: A semiconductor substrate used for fabricating vertical devices, such as vertical MOSFET, capable of maintaining low ON-stage resistance and of ensuring a necessary level of OFF-stage breakdown voltage is provided. A heavily-doped arsenic layer of 0.5 to 3.0 ?m thick is inserted between a heavily-doped phosphorus layer 11 composing the drain of a vertical MOSFET and an n?-type drift layer. The heavily-doped arsenic layer functions as a barrier layer which prevents phosphorus from diffusing from the heavily-doped phosphorus layer into the n?-type drift layer. This is successful in maintaining spreading of the depletion layer during OFF time of the vertical MOSFET to thereby improve the OFF-stage breakdown voltage, and in maintaining the low ON-stage resistance.

Abstract: Manufacturing a power transistor by forming a gate structure on a first layer, forming a trench in the first layer, self aligned with the gate structure, and forming part of the transistor in the trench. By forming a spacer next to the gate, the spacer and gate can be used as a mask when forming the trench, to allow space for a source region next to the gate. The self-aligning rather than forming the gate after the trench means the alignment is more accurate, allowing size reduction. Another aspect involves forming a trench in a first layer, filling the trench, forming a second layer on either side of the trench with lateral overgrowth over the trench, and forming a source region in the second layer to overlap the trench. This overlap can enable the chip area to be reduced.

Abstract: An injection enhanced gate transistor includes a drift layer, a collector layer and a base layer divided into main cell regions and dummy cell regions by a plurality of trenches formed to extend from the top surface of the base layer into the drift layer. The main cell has a first emitter layer selectively formed in the surface layer of the base layer, gate electrodes formed in the trenches, and an emitter electrode located over the base layer. The dummy cell has a second emitter layer selectively formed so as to be scattered in the surface layer of the base layer and have a surface area smaller than that of the first emitter layer to prevent waveform vibration associate with negative gate capacitance.

Abstract: A high-breakdown-voltage semiconductor apparatus is provided, wherein when a gate capacitance of that portion of a gate electrode, under which a channel is formed, is Cg [F], a resistance in a channel length direction of that portion of the gate electrode, under which the channel is formed, is Rg [?], a threshold voltage, which is to be applied to the gate electrode and application of which permits flow of a drain current, is Vth [V], a voltage to be applied to the gate electrode to cut off the drain current is Voff [V], and a ratio of increase in the drain voltage per unit time at the time of cutting off the drain current is dV/dt [V/s], the following condition is satisfied: |Vt?Voff|?0.5·Cg·Rg·(dV/dt).

Abstract: A high-breakdown-voltage semiconductor apparatus is provided, wherein when a gate capacitance of that portion of a gate electrode, under which a channel is formed, is Cg[F], a resistance in a channel length direction of that portion of the gate electrode, under which the channel is formed, is Rg [?], a threshold voltage, which is to be applied to the gate electrode and application of which permits flow of a drain current, is Vth [V], a voltage to be applied to the gate electrode to cut off the drain current is Voff [V], and a ratio of increase in the drain voltage per unit time at the time of cutting off the drain current is dV/dt [V/s], the following condition is satisfied: |Vth?Voff|?0.