Abstract: A floating gate transistor, comprising source and drain electrodes covered by a first dielectric separated by a channel, a floating gate electrode on the first dielectric arranged over the channel, an interlayer at least partially comprised of a semiconductor material and an organic material, and a control gate on the interlayer electrically coupled to the gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate having a plurality of isolation regions, a plurality of trenches, where each of the plurality of trenches is formed in a corresponding isolation region, of the plurality of isolation regions, and where the plurality of trenches are arranged, in parallel, along a first direction, a plurality of gate lines formed on the semiconductor substrate in a second direction crossing the plurality of trenches, an insulating layer formed between each of the plurality of gate lines, a first air gap formed in at least one of the plurality of trenches, the first air gap extending in the first direction, and a second air gap formed in at least one of the insulating layers, the second air gap extending in the second direction.

Abstract: An electrically erasable programmable read only memory (EEPROM) cell structure and a method of fabricating the same. The EEPROM cell comprising a substrate comprising two shallow trench isolation (STI) structures separated by a substrate portion; an intermediate patterned layer formed on the substrate such that the patterned layer covers respective portions of each STI structure; a floating gate bridging between the STI structures such that the floating gate extends over the intermediate patterned layer; a dielectric layer formed over the floating gate; and a control gate formed over the dielectric layer.

Abstract: There is provided a semiconductor device in which degradation of reliability originating in the interface between an upper insulating layer and an element isolation insulating layer is suppressed. The semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures.

Abstract: A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.

Abstract: Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.

Abstract: Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes an element region, a gate insulating film, a first gate electrode, an intergate insulating film, a second gate electrode and an element isolation region. The gate insulating film is formed on the element region. The first gate electrode is formed on the gate insulating film. The intergate insulating film is formed on the first gate electrode and has an opening. The second gate electrode is formed on the intergate insulating film and in contact with the first gate electrode via the opening. The element isolation region encloses a laminated structure formed by the element region, the gate insulating film, and the first gate electrode. The air gap is formed between the element isolation region and side surfaces of the element region, the gate insulating film and the first gate electrode.

Abstract: A MONOS type non-volatile semiconductor memory device which is capable of electrically writing, erasing, reading and retaining data, the memory device including source/drain regions, a first gate insulating layer, a first charge trapping layer formed on the first gate insulating layer, a second gate insulating layer formed on the first charge trapping layer, and a controlling electrode formed on the second gate insulating layer. The first charge trapping layer includes an insulating film containing Al and O as major elements and having a defect pair formed of a complex of an interstitial O atom and a tetravalent cationic atom substituting for an Al atom, the insulating film also having electron unoccupied levels within the range of 2 eV-6 eV as measured from the valence band maximum of Al2O3.

Abstract: A semiconductor memory storage device includes first and second doped regions of a first type disposed in a semiconductor substrate. The first and second doped regions of the first type being laterally spaced from one another. A gate dielectric extends over the semiconductor substrate between the first and second doped regions, and a floating gate is disposed on the gate dielectric. An ultraviolet (UV) light blocking material is vertically disposed above the floating gate and has a size that covers the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to UV light.

Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate on which an element isolation groove is formed, memory cells each including a gate electrode having a charge storage layer, an interelectrode insulating film, and a control electrode, that is formed on the semiconductor substrate via a tunnel insulating film, and an insulating film disposed in the element isolation groove. The interelectrode insulating film is formed to have a first portion above the insulating film that is separated from one of the insulating film and the control electrode by an air gap and a second portion above the charge storage layer that is separated from the charge storage layer by a cavity.

Abstract: An embedded flash memory cell and a corresponding method for fabricating the embedded flash memory cell are disclosed. In some embodiments, the flash memory cell comprises a floating gate that has been formed using a metal gate and local interconnect metal. For some embodiments, the embedded flash memory can be fabricated with little-to-no additional processes than what one would normally employ in fabricating a metal-oxide semiconductor field-effect transistor (MOSFET).

Abstract: An electrically programmable read only memory (EPROM) BIT cell structure formed on a semiconductor substrate comprises an N-type epitaxial layer formed on the semiconductor substrate, an N-type well region formed in the epitaxial layer, LOCOS field oxide formed at the periphery of the well region to define an active device region in the well region, a field oxide ring formed in the active region and space-apart from the LOCOS field oxide to define an EPROM BIT cell region, and an EPROM BIT cell formed in the EPROM BIT cell region.

Abstract: A nonvolatile semiconductor storage device includes a semiconductor layer, a first insulating film formed on the semiconductor layer, a charge storage layer formed on the first insulating film and having fine metal grains, a second insulating film formed on the charge storage layer, and a gate electrode formed on the second insulating film. During a write operation, a differential voltage is applied across the gate electrode and the semiconductor layer to place the gate electrode at a lower voltage than the semiconductor layer and cause a positive electric charge to be stored in the charge storage layer.

Abstract: A semiconductor device according to an embodiment, includes a plurality of gate structures; a first dielectric film; and a second dielectric film. The first dielectric film crosslinks adjacent gate structures of the plurality of gate structures so as to form a cavity each above and below in a position between the adjacent gate structures. The second dielectric film is formed as if to cover the cavity above the first dielectric film between the adjacent gate structures.

Abstract: The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an -shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability.

Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

Abstract: According to one embodiment, a semiconductor storage device comprises a memory cell transistor including a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film and a control gate which are sequentially formed on a substrate, and a select transistor including a fourth insulating film, a first electrode layer, a fifth insulating film, a second electrode layer, a sixth insulating film and a third electrode layer which are sequentially formed on the substrate. Openings are provided in at least parts of the fifth insulating film and the sixth insulating film. The first electrode layer, the second electrode layer and the third electrode layer are electrically connected via the openings.

Abstract: Memory cells and methods for programming and erasing a memory cell by utilizing a buried select line are described. A voltage potential may be generated between a source-drain region and the buried select line region of the memory cell to store charge in a storage region between the source-drain and buried select line regions. The generated voltage potential causes electrons to either tunnel towards the buried storage region to store electrical charge or away from the buried storage region to discharge electrical charge.

Abstract: A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes an underlayer and a stacked body. The stacked body includes control gate layers and insulating layers. The device includes a channel body layer penetrating through the stacked body, and the control gate layers and the insulating layers are stacked in the stacking direction, a floating gate layer provided between each of the plurality of control gate layers and the channel body layer. The device includes a block insulating layer provided between each of the plurality of control gate layers and the floating gate layer, and includes a tunnel insulating layer provided between the channel body layer and the floating gate layer. A length of a boundary between the floating gate layer and the block insulating layer is shorter than a length of a boundary between the floating gate layer and the tunnel insulating layer.

Abstract: A semiconductor device includes: a semiconductor substrate; an element isolation insulator; an insulating block; an interlayer insulating film; and a contact. A plurality of active areas extending in one direction and protruding upward are formed at an upper surface of the substrate. The insulating block is disposed directly on the element isolation insulator. The contact is formed in the interlayer insulating film. A lower end of the contact is connected to an upper surface of the active area. A part of a lower surface of the contact located directly on the insulating block is positioned higher than a part of a lower surface of the contact located directly on the active area.

Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.

Abstract: An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate.

Abstract: A semiconductor device includes a substrate; a storage element disposed over the substrate in a first region; a control gate disposed over the storage element; a high-k dielectric layer disposed on the substrate in a second region adjacent the first region; and a metal select gate disposed over the high-k dielectric layer and adjacent to the storage element and the control gate.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a gate pattern formed by patterning a tunnel insulating layer, a conductive film for a floating gate, a dielectric film, a conductive film for a control gate, and a gate metal film sequentially formed on a semiconductor substrate; a first barrier film formed on side walls of the gate metal film; and a second barrier film formed on an upper surface of the gate metal film.

Abstract: A flash memory and a method for fabricating the same are provided. The flash memory comprises: a semiconductor substrate; a storage medium layer formed on the semiconductor substrate and comprising from bottom to top: a tunneling oxide layer, a silicon nitride layer and a blocking oxide layer; a semiconductor layer formed on the storage medium layer and comprising a channel region and a source region and a drain region located on both sides of the channel region respectively; and a gate stack formed on the channel region and comprising a gate dielectric and a gateformed on the gate dielectric.

Abstract: A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.

Abstract: A non-volatile memory having a tunneling dielectric layer, a floating gate, a control gate, an inter-gate dielectric layer and a first doping region and a second doping region is provided. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer, and has a protruding portion. The control gate is disposed over the floating gate to cover and surround the protruding portion. The protruding portion of the floating gate is fully covered and surrounded by the control gate in any direction, including extending directions of bit lines, word lines and an included angle formed between the word line and the bit line. The inter-gate dielectric layer is disposed between the floating gate and the control gate. The first doping region and the second doping region are respectively disposed in the substrate at two sides of the control gate.

Abstract: A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

Abstract: A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

Abstract: A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.

Abstract: According to one embodiment, a semiconductor memory device includes each of memory cells including a floating electrode above a semiconductor substrate via the gate insulator, a control gate electrode above the floating gate electrode via a first inter-gate insulator, first diffusion layers as source or drain, a contact electrode portion including a bottom electrode with an opening and a top electrode on the bottom electrode, the bottom electrode being arranged on the first gate insulator having the opening, the top electrode being electrically connected to the semiconductor substrate via the first opening, and a connection diffusion layer formed in the semiconductor substrate below the first opening.

Abstract: A non-self aligned non-volatile memory structure includes a semiconductor substrate; a first gate insulation layer on said semiconductor substrate; a floating gate on first gate insulation layer; two doped regions in said semiconductor substrate, which are respectively on two sides of said first gate insulation layer, and adjoining said first gate insulation layer; a second gate insulation layer on said floating gate; and a control gate on said second gate insulation layer. Width of said control gate on said floating gate is less than that of said floating gate, and width of said control gate not on said floating gate is equal to or greater than width of said floating gate. Through the two non-self aligned gates, the non-volatile memory does not need to meet the requirement of gate line-to-line alignment, thus reducing complexity and cost of manufacturing process.

Abstract: A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.

Abstract: Thin film transistor memory cells are stackable, and employ bandgap engineered tunneling layers in a junction free, NAND configuration, that can be arranged in 3D arrays. The memory cells have a channel region in a semiconductor strip formed on an insulating layer, a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure having a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region, a charge storage layer disposed above the tunnel dielectric structure, an insulating layer disposed above the charge storage layer, and a gate electrode disposed above the insulating layer.

Abstract: A 3D nonvolatile memory device includes a plurality of channel structures each comprising a plurality of channel layers and interlayer dielectric layers which are alternately stacked, a plurality of channel contacts coupled to the plurality of channel layers, respectively, and a plurality of selection lines vertically-coupled to the plurality of channel contacts and crossing over the plurality of channel structures.

Abstract: A method of forming a semiconductor device is provided. The method includes providing a semiconductor substrate, and forming a first conductive layer over the substrate. In one example, an insulating layer may be formed over the semiconductor substrate, with the first conductive layer being formed over the insulating layer. The method also includes forming an interpoly dielectric layer over the first conductive layer. In this regard, forming the interpoly dielectric layer includes forming a silicon oxide layer, and subjecting the silicon oxide layer to oxide densification to form an oxide-densified silicon oxide layer. And the method includes forming a second conductive layer over the interpoly dielectric layer.

Abstract: A single poly EEPROM (Electrically Erasable Programmable Read Only Memory), which may include at least one of the following: (1) A second conductive type well formed on and/or over a semiconductor substrate. (2) A first conductive type source and drain regions formed in the second conductive type well. The single poly EEPROM may include at least one of: (a) A tunnel oxide layer formed on and/or over the second conductive type well. (b) A floating gate formed on and/or over the tunnel oxide layer and doped with second conductive type impurity ions. (c) A first conductive type impurity region formed in the second conductive type well adjacent to the floating gate. The floating gate may be configured such that a concentration of a region of the floating gate adjacent to the drain region is higher than that of the other region of the floating gate adjacent to the impurity region.

Abstract: A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.

Abstract: A non-volatile memory device includes a first string and a second string that each include a first drain selection transistor, a second drain selection transistor, a plurality of memory cells, and a source selection transistor that are coupled in series in that order, respectively, a first bit line coupled with a node between the first and second drain selection transistors of the first string, and a second bit line coupled with an end node of the second string on the side of the first drain selection transistor of the second string, wherein gates of the first drain selection transistors of the first and second strings are coupled with each other, and gates of the second drain selection transistors of the first and second strings are coupled with each other.

Abstract: A semiconductor device is provided. The semiconductor device includes a memory device, and the memory device includes a substrate, two stacked gates, two spacers, an insulating layer, and a dielectric layer. The stacked gates having a gap therebetween are located on the substrate. The spacers having a pipe or a seam therebetween are respectively located at sidewalls of each of the stacked gates in the gap. The pipe or the seam is filled with the insulating layer. The dielectric layer is located on the substrate and covers the insulating layer and the stacked gates.

Abstract: A non-volatile memory device includes a source region, a drain region, and a channel region therebetween. The channel region has a length extending from the source region to the drain region and a channel width in the direction perpendicular to the channel length direction. The device includes a floating gate positioned between the source and the drain in the channel length direction. The width of the floating gate is less than the channel width. A control gate covers a top surface and a side surface of the floating gate. The control gate also overlies an entirety of the channel region. Erasure of the cell is accomplished by Fowler-Nordheim tunneling from the floating gate to the control gate. Programming is accomplished by electrons migrating through an electron concentration gradient from a channel region underneath the control gate into a channel region underneath the floating gate and then injecting into the floating gate.

Abstract: A single polycrystalline silicon floating gate nonvolatile memory cell has a MOS capacitor and a storage MOS transistor fabricated with dimensions that allow fabrication using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form a floating gate node. The physical size of the MOS capacitor is relatively large (approximately 10 time greater) when compared to a physical size of the storage MOS transistor to establish a large coupling ratio (greater than 80%) between the second plate of the MOS capacitor and the floating gate node. When a voltage is applied to the second plate of the MOS capacitor and a voltage applied to the source region or drain region of the MOS transistor establishes a voltage field within the gate oxide of the MOS transistor such that Fowler-Nordheim edge tunnel is initiated.

Abstract: A nonvolatile memory device, and method of forming the same, discloses a semiconductor device including floating gates that each have a first region that overlaps with a corresponding junction and that each have a second region that does not overlap the corresponding junction. The first region and the second region have different work functions.

Abstract: A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.

Abstract: A semiconductor device includes a plurality of first trenches having a first depth formed in a semiconductor substrate, a plurality of second trenches having a second depth formed in the semiconductor substrate, wherein the second depth is different from the first depth and the second trenches are formed between the first trenches, a plurality of isolation layers formed at the plurality of first trenches and the plurality of second trenches, wherein the isolation layers have upper portions formed above the semiconductor substrate, and a plurality of memory cells formed over the semiconductor substrate between the isolation layers.

Abstract: A vertical NAND string nonvolatile memory device can include an upper dopant region disposed at an upper portion of an active pattern and can have a lower surface located a level higher than an upper surface of an upper selection gate pattern. A lower dopant region can be disposed at a lower portion of the active pattern and can have an upper surface located at a level lower than a lower surface of a lower selection gate pattern.

Abstract: A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.