Abstract: Doped semiconductor ink formulations, methods of making doped semiconductor ink formulations, methods of coating or printing thin films, methods of forming electronic devices and/or structures from the thin films, and methods for modifying and controlling the threshold voltage of a thin film transistor using the films are disclosed. A desired dopant may be added to an ink formulation comprising a Group IVA compound and a solvent, and then the ink may be printed on a substrate to form thin films and conductive structures/devices, such as thin film transistors. By adding a customized amount of the dopant to the ink prior to printing, the threshold voltage of a thin film transistor made from the doped semiconductor ink may be independently controlled upon activation of the dopant.

Abstract: A first insulation film is formed on a semiconductor substrate. A first gate electrode is formed on the first insulation film. A second insulation film is formed on an upper surface and a side surface of the first gate electrode. A second gate electrode is formed on the second insulation film. The entirety of that part of the second gate electrode, which is located above the second insulation film formed on the upper surface of the first gate electrode, is a silicide layer. At least a portion of that part of the second gate electrode, which is located on the side surface of the first gate electrode, is a silicon layer.

Abstract: A flash memory cell is provided. The flash memory cell includes: a substrate with a source line thereon; a word line and a word line dielectric layer on each side of the source line; an isolating dielectric layer which isolates the source line from the word line and the word line dielectric layer on each side of the source line; a gate stack on an outer side of each word line dielectric layer, including a floating gate dielectric layer, a floating gate, a control gate dielectric layer and a control gate; a first spacer, disposed on an outer sidewall of each word line dielectric layer and on each control gate; and a source region in the substrate and in contact with the source line. The space may be saved and the costs may be reduced.

Abstract: A memory device is described, including a gate over a substrate, a gate dielectric between the gate and the substrate, and two charge storage layers. The width of the gate is greater than that of the gate dielectric, so that two gaps are present at both sides of the gate dielectric and between the gate and the substrate. Each charge storage layer includes a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein the edge of the first extension portion protrudes from the sidewall of the second extension portion.

Abstract: A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.

Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.

Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

Abstract: A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.

Abstract: An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip.

Abstract: A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices.

Abstract: A dielectric layer containing a Zr—Sn—Ti—O film and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. In an embodiment, forming the Zr—Sn—Ti—O film on a substrate includes depositing materials of the Zr—Sn—Ti—O film substantially as atomic monolayers. In an embodiment, electronic devices include a dielectric layer having a Zr—Sn—Ti—O film such that Zr—Sn—Ti—O material is configured as substantially atomic monolayers. Dielectric layers containing such Zr—Sn—Ti—O films may have minimal reactions with a silicon substrate or other structures during processing.

Abstract: In some embodiments, an interlayer polysilicon dielectric cap disposed atop a substrate having a first floating gate, a second floating gate and an isolation layer disposed between the first floating gate and the second floating gate may include: a first nitrogen containing layer disposed atop an upper portion and sidewalls of the first floating gate and second floating gate; a first oxygen containing layer disposed atop the first nitrogen containing layer and an upper surface of the isolation layer; a second nitrogen containing layer disposed atop an upper portion and sidewalls of the first oxygen containing layer; and a second oxygen containing layer disposed atop the second nitrogen containing layer and an upper surface of the first oxygen containing layer.

Abstract: A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.

Abstract: A memory cell having a kinked polysilicon layer structure, or a polysilicon layer structure with a top portion being narrower than a bottom portion, may greatly reduce random single bit (RSB) failures and may improve high density plasma (HDP) oxide layer fill-in by reducing defects caused by various impurities and/or a polysilicon layer short path. A kinked polysilicon layer structure may also be applied to floating gate memory cells either at the floating gate structure or the control gate structure.

Abstract: A nonvolatile floating gate analog memory cell (1) comprising a transistor having a source (2) and drain (3) formed inside a substrate or on an insulator body (not shown) and separated by a channel (4). The memory cell comprises at least one floating gate (5) formed on one side of the source and drain. (6) is a control gate formed on one side of the floating gate and connected to a first voltage (7). (8) is a back gate formed on the other side of the source and drain and connected to a second voltage (9). The channel is separated from the floating gate and the back gate by an insulation layer (10). The control gate is separated from the floating gate by an insulation layer (11) and the source and drain are isolated from the back gate, control gate and floating gate(s) by a spacer (12). The second voltage changes the intrinsic threshold voltage linearly during programming so that the programmed threshold voltage corresponds to the second voltage.

Abstract: A non-volatile memory fabrication process includes the formation of a complete memory cell layer stack before isolation region formation. The memory cell layer stack includes an additional place holding control gate layer. After forming the layer stack columns, the additional control gate layer will be incorporated between an overlying control gate layer and underlying intermediate dielectric layer. The additional control gate layer is self-aligned to isolation regions between columns while the overlying control gate layer is etched into lines for contact to the additional control gate layer. In one embodiment, the placeholder control gate layer facilitates a contact point to the overlying control gate layer such that contact between the control gate layers and the charge storage layer is not required for select gate formation.

Abstract: Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate.

Abstract: A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.

Abstract: Non-volatile memory devices, and fabricating methods thereof, include a floating gate over a substrate, a lower barrier layer including a first lower barrier layer on the upper surface of the floating gate, and a second lower barrier layer on a side surface of the floating gate to have a thickness smaller than a thickness of the first lower barrier layer, an inter-gate dielectric layer over the lower barrier layer, and a control gate over the inter-gate dielectric layer.

Abstract: A non-volatile memory device and a method of fabricating the same are provided. The method can include disposing an isolation layer on a semiconductor substrate. The isolation layer may protrude from the main surface of the semiconductor substrate and define an active region. In a recess defined by the protrusion of the isolation layer and the active region, a diffusion-retarding poly pattern and a floating gate may be formed in sequence. A control gate may be disposed on the isolation layer to cover the diffusion-retarding poly pattern and the floating gate.

Abstract: A three-dimensional (3-D) nonvolatile memory device includes channel layers protruded from a substrate, word line structures configured to include word lines stacked over the substrate, first junctions and second junctions formed in the substrate between the word line structures adjacent to each other, source lines coupled to the first junctions, respectively, and well pickup lines coupled to the second junctions, respectively.

Abstract: A semiconductor memory device according to embodiment of the present invention includes a tunnel insulating layer formed over a semiconductor substrate, a floating gate formed over the tunnel insulating layer, a dielectric layer formed over the floating gate, and a control gate including a third silicon layer formed over the dielectric layer, a fourth silicon layer formed over the third silicon layer, and a conductive layer formed over the fourth silicon layer, wherein the fourth silicon layer has a greater width than the third silicon layer.

Abstract: The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an I-shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability.

Abstract: A nonvolatile memory device and a method of manufacturing thereof are provided. The method includes forming a floating gate on a substrate, forming a dielectric layer to conform to a shape of the floating gate, forming a conductive layer to form a control gate on the substrate, the control gate covering the floating gate and the dielectric layer, forming a photoresist pattern on one side of the conductive layer, forming the control gate in the form of a spacer to surround sides of the floating gate, the forming of the control gate including performing an etch-back on the conductive layer until a portion of the dielectric layer on the floating gate is exposed, and forming a poly pad, to which a plurality of contact plugs are connected, on one side of the control gate, the forming of the poly pad including removing the photoresist pattern.

Abstract: A three-dimensional (3-D) nonvolatile memory device includes vertical channel layers protruded from a substrate, interlayer insulating layers and memory cells, which are alternately stacked along the vertical channel layers, and select transistors including planar channel layers, each contacted with at least one of the vertical channel layers and being parallel to the substrate, and gate insulating layers formed over the planar channel layers.

Abstract: A semiconductor device includes a bit line, a first cell string and a second cell string. The first cell string includes a first selecting transistor connected to the bit line in series and having a threshold voltage greater than a first reference voltage, a second selecting transistor having a threshold voltage smaller than a second reference voltage, cell transistors and a ground selecting transistor. The second cell string includes a third selecting transistor connected to the bit line in series and having a threshold voltage smaller than the first reference voltage, a fourth selecting transistor having a threshold voltage greater than the second reference voltage, cell transistors and a ground selecting transistor. A channel region of the first selecting transistor has an enhancement mode and a first conductive type. A channel region of the third selecting transistor has a depletion mode and a second conductive type.

Abstract: An electrical erasable programmable read-only memory (EEPROM) including a floating transistor formed on a semiconductor substrate and a tunneling transistor formed on a semiconductor substrate and configured to erase electrons trapped in the floating transistor. The tunneling transistor has a source junction region and a drain junction region that are integrally joined by lateral diffusion. The EPROM maintains a small cell size without any additional mask process, and is useable as an MTP EEPROM because electrical erasure is enabled. In addition, the adjustment of the width of a gate constituting the tunneling transistor ensures an improved degree of freedom to adjust an erasure voltage can be enhanced.

Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

Abstract: An electrically erasable programmable read-only memory includes a first polysilicon layer, a second polysilicon layer and a third polysilicon layer, the first polysilicon layer and the third polysilicon layer forming a control gate and the second polysilicon layer forming a floating gate. The first polysilicon layer is horizontally disposed in series with the second polysilicon layer and is connected to the third polysilicon layer, so that the control gate encloses all of the floating gate except for a tunnel surface of the floating gate.

Abstract: In one embodiment, a nonvolatile semiconductor memory device includes a substrate, and a well region formed in the substrate. The device further includes device regions formed in the well region and defined by isolation trenches formed in the well region, the device regions extending in a first direction parallel to a principal surface of the substrate, and being adjacent to one another in a second direction that is perpendicular to the first direction. The device further includes isolation insulators buried in the isolation trenches to isolate the device regions from one another. The device further includes floating gates disposed on the device regions via gate insulators, and a control gate disposed on the floating gates via an intergate insulator. The device further includes first diffusion suppressing layers formed inside the respective device regions to divide each of the device regions into an upper device region and a lower device region.

Abstract: The present invention relates to a semiconductor device including nanodots and a capacitor. A semiconductor device includes a channel layer, a tunnel insulating layer formed on the channel layer, a memory layer formed on the tunnel insulating layer and including first nanodots, a charge blocking layer formed on the memory layer, a gate electrode conductive layer formed on the charge blocking layer, and a buffer layer located, at least one of, inside the tunnel insulating layer, inside the charge blocking layer, at an interface between the tunnel insulating layer and the memory layer and at the interface between the charge blocking layer and the memory layer, wherein the buffer layer includes second nanodots.

Abstract: A semiconductor device includes: a semiconductor substrate; an element isolation insulator; an insulating block; an interlayer insulating film; and a contact. A plurality of active areas extending in one direction and protruding upward are formed at an upper surface of the substrate. The insulating block is disposed directly on the element isolation insulator. The contact is formed in the interlayer insulating film. A lower end of the contact is connected to an upper surface of the active area. A part of a lower surface of the contact located directly on the insulating block is positioned higher than a part of a lower surface of the contact located directly on the active area.

Abstract: Dual Conducting Floating Spacer Metal Oxide Semiconductor Field Effect Transistors (DCFS MOSFETs) and methods for fabricate them using a process that is compatible with forming conventional MOSFETs are disclosed. A DCFS MOSFET can provide multi-bit storage in a single Non-Volatile Memory (NVM) memory cell. Like a typical MOSFET, a DCFS MOSFET includes a control gate electrode on top of a gate dielectric-silicon substrate, thereby forming a main channel of the device. Two electrically isolated conductor spacers are provided on both sides of the control gate and partially overlap two source/drain diffusion areas, which are doped to an opposite type to the conductivity type of the substrate semiconductor. The DCFS MOSFET becomes conducting when a voltage that exceeds a threshold is applied at the control gate and is coupled through the corresponding conducting floating spacer to generate an electrical field strong enough to invert the carriers near the source junction.

Abstract: A MONOS type non-volatile semiconductor memory device which is capable of electrically writing, erasing, reading and retaining data, the memory device including source/drain regions, a first gate insulating layer, a first charge trapping layer formed on the first gate insulating layer, a second gate insulating layer formed on the first charge trapping layer, and a controlling electrode formed on the second gate insulating layer. The first charge trapping layer includes an insulating film containing Al and O as major elements and having a defect pair formed of a complex of an interstitial O atom and a tetravalent cationic atom substituting for an Al atom, the insulating film also having electron unoccupied levels within the range of 2 eV-6 eV as measured from the valence band maximum of Al2O3.

Abstract: A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.

Abstract: Flash-to-ROM conversion is performed by converting single transistor flash memory cells to single transistor ROM cells. An S-Flash memory cell is converted to a programmed ROM cell by introducing a threshold voltage implant into the channel region of the S-Flash memory cell. Alternately, an S-Flash memory cell is converted to a programmed ROM cell by introducing a threshold voltage implant into a substrate region in alignment with an edge of the gate electrode of the S-Flash memory cell. The width of the mask through which this threshold voltage implant is performed can be varied, such that the threshold voltage implant region can have different dopant concentrations, thereby allowing multiple bits to be represented by the programmed ROM cell. In another embodiment, a Y-flash memory cell is converted to a programmed ROM cell by adjusting the length of a floating gate extension region of the Y-Flash memory cell.

Abstract: A semiconductor memory device and method of manufacturing the same, the device including string structures, the string structures including two or more adjacent string selection transistors connected in series to each other in a first direction and being spaced apart from one another in a second direction intersecting the first direction, the two or more string selection transistors having different threshold voltages; string selection lines, the string selection lines connecting the adjacent string selection transistors of the string structures in the second direction; and a bit line electrically connecting two or more adjacent string structures, wherein a device isolation layer between the adjacent string selection transistors in the second direction has recessed regions, and profiles of the recessed regions on respective sides of the string selection transistors are different from each other.

Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

Abstract: A semiconductor device includes an interelectrode insulating film formed between a charge storage layer and a control electrode layer. The interelectrode insulating film is formed in a first region above an upper surface of an element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a first stack including a first silicon nitride film or a high dielectric constant film interposed between a first and a second silicon oxide film or a second stack including a second high dielectric constant film and a third silicon oxide film, and a second silicon nitride film formed between the control electrode layer and the first or the second stack. The second silicon nitride film is relatively thinner in the third region than in the first region.

Abstract: A single-gate non-volatile flash memory cell, a memory device including the memory cell, and a manufacturing method thereof are provided. The memory cell includes a semiconductor structure and a movable switch (200), wherein the semiconductor structure includes a floating-gate structure, and an interlayer dielectric layer (130) with an opening (1204) through which the floating-gate structure is exposed; the movable switch (200) includes a support component (210) and a conductive interconnection component (220),the support component (210) is located on the periphery of the conductive interconnection component (220) and connected with the interlayer dielectric layer (130), and the conductive interconnection component (220) is floating over the opening (1024).

Abstract: An array of memory cells has a conductive pillar and a plurality of first and second memory cells coupled in series by the conductive pillar. Each first memory cell has a respective portion of a first charge trap adjacent to the conductive pillar and a respective first control gate adjacent to the respective portion of the first charge trap. Each second memory cell has a respective portion of a second charge trap adjacent to the conductive pillar and a respective second control gate adjacent to the respective portion of the second charge trap. Each first control gate is electrically isolated from each second control gate. A single select transistor may selectively couple the plurality of first memory cells and the plurality of second memory cells to one of a source line and a data line.

Abstract: A flash memory structure includes a semiconductor substrate, a gate dielectric layer on the semiconductor substrate, a floating gate on the gate dielectric layer, a capacitor dielectric layer conformally covering the floating gate, wherein the capacitor dielectric layer forms a top surface and four sidewall surfaces; and an isolated conductive cap layer covering the top surface and the four sidewall surfaces.

Abstract: A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

Abstract: Over the top of a semiconductor substrate, a lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed. Over the top of the semiconductor substrate, a memory gate electrode adjacent to the lamination pattern is formed. Between the control gate electrode and the semiconductor substrate, a third insulation film for gate insulation film is formed. Between the memory gate electrode and the semiconductor substrate, and between the lamination pattern and the memory gate electrode, a fourth insulation film including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film is formed. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a substrate; a memory unit provided on the substrate; and a non-memory unit provided on the substrate. The memory unit includes: a first stacked body including a plurality of first electrode films and a first inter-electrode insulating film, the plurality of first electrode films being stacked along a first axis perpendicular to the major surface, the first inter-electrode insulating film being provided between two of the first electrode films mutually adjacent along the first axis; a first semiconductor layer opposing side surfaces of the first electrode films; a first memory film provided between the first semiconductor layer and the first electrode films; and a first conductive film provided on the first stacked body apart from the first stacked body. The non-memory unit includes a resistance element unit of the same layer as the conductive film.

Abstract: According to one embodiment, a semiconductor memory element includes a semiconductor layer, a tunnel insulator provided on the semiconductor layer, a charge accumulation film provided on the tunnel insulator having a film thickness of 0.9 nm or more and 2.8 nm or less and the charge accumulation film containing cubic HfO2 particles, a block insulator provided on the charge accumulation film, and a control electrode provided on the block insulator.

Abstract: A semiconductor device has a first-conductivity-type-channel MOSFET formed on a semiconductor substrate, wherein the first-conductivity-type-channel MOSFET is typically a P-channel MOSFET, and is composed of a gate insulating film and a gate electrode provided over the semiconductor substrate, the gate electrode contains a metal gate electrode provided over the gate insulating film, a metal oxide film provided over the metal gate electrode, and another metal gate electrode provided over metal oxide film.

Abstract: Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.

Abstract: A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates.

Abstract: A method for fabricating a non-volatile memory device includes forming a gate layer over a substrate having a cell region and a peripheral circuit region, forming a gate pattern corresponding to a region for selection lines and a region between neighboring selection lines in the cell region, where during the forming of the gate pattern, word lines in the cell region and a peripheral circuit gate in the peripheral circuit region are formed by selectively etching the gate layer, forming spacers on sidewalls of the peripheral circuit gate, and forming the selection lines by selectively etching a portion of the gate pattern corresponding to the region between the neighboring selection lines.