Abstract: Described herein is a voltage compensated level-shifter with nearly constant duty cycle and matching rise and fall slopes of the output of the level-shifter, no meta-stability, and nearly constant propagation delay across power supply levels. The voltage compensated level-shifter comprises a first inverter to receive an input signal for level shifting from a first power supply level to a second power supply level, and to generate a first inverted signal, the first inverter operating on the first power supply level; a second inverter to receive the input signal and to generate a second inverted signal, the second inverter operating on the second power supply level; and a NOR logical gate to receive the first and second inverted signals and to generate an output signal, the NOR logical gate operating on the second power supply level, wherein the output signal is level shifted to the second power supply level.

Abstract: A level conversion circuit (10) includes an EFET (11), a diode (12) and resistors (13, 14). The drain of the EFET (11) is connected to an output terminal of the level conversion circuit (10). The drain and the gate of the EFET (11) are in conductive contact with each other. The source of the EFET (11) is grounded via the resistor (13). The drain of the EFET (11) is connected to one end of the resistor (14). The other end of the resistor (14) is connected to the cathode of the diode (12). The anode of the diode (12) is connected to a control voltage input terminal.

Abstract: Disclosed are apparatus and methods to advantageously calibrate a transmitter output swing. One embodiment relates to a method for calibrating the output swing voltage of a transmitter. A fixed value is provided as the data input, and output swing calibration circuitry is connected to the transmitter buffer circuit. A transmitter current is set to an initial level, and the transmitter current is adjusted until the output swing of the transmitter buffer circuit is calibrated. Another embodiment relates to an integrated circuit which includes a transmitter buffer circuit, output swing calibration circuitry, and switches arranged to electrically connect the transmitter buffer circuit to the output swing calibration circuitry during an output swing calibration mode. Another embodiment relates to an output swing calibration circuit which includes comparison circuitry and logic and control circuitry.

Abstract: A voltage level shifter for translating a binary input signal representing a binary sequence to a binary output signal representing the same binary sequence. The voltage level shifter comprises an input port for receiving the binary input signal as an input voltage varying between a first input voltage level and a second input voltage level. An output port is connected to a node for outputting the binary output signal as an output voltage varying between a first output voltage level and a second output voltage level. A supply voltage node connectable to a voltage supply, can provide the second output voltage level. A first switch is arranged to couple the supply voltage node to the node and to decouple the supply voltage node from the node based on a voltage at the node. A feedback voltage loop is connected to the node for providing a feedback voltage based on the voltage at the node.

Abstract: A system and method of shifting a data signal from a first voltage domain having a first logic level to a second voltage domain having a second logic level, the second logic level having a second logical high state greater than a first logical high state in the first logic level and a single power supply logic level shifter circuit having a single power supply source, an input node and an output node, the input node coupled to a sender circuit in the first voltage domain and the output node coupled to a receiver circuit in the second voltage domain, the single power supply source being coupled only to a single power grid in the second voltage domain.

Abstract: In one embodiment, a hybrid output buffer having both an H-bridge mode and a CML mode of operation includes a plurality of transistor switches arranged between an upper rail and a bottom rail. A first pair of the transistor switches couples between the upper rail and respective output nodes. A pair of resistors couples between the output nodes and a central node. During H-bridge mode, the hybrid output buffer controls a potential of the upper rail responsive to a feedback signal proportional to a difference between a potential of the central node and a common-mode voltage.

Abstract: A driving circuit of a schottky type transistor includes an input terminal supplied with an input signal, and an output terminal connected to a gate of the schottky type transistor. The driving circuit outputs a first voltage lower than a breakdown voltage of the schottky type transistor to the output terminal at the time of rising of the input signal, and thereafter supplies a second voltage higher than the breakdown voltage to a resistance connected to the output terminal.

Abstract: The present invention provides a CML to CMOS conversion circuit comprising a first differential unit, a second differential unit, and an output unit. The output unit comprises a series connection of a first inverter and a second inverter, wherein, a resistor is connected with the first inverter in parallel. The CML to CMOS conversion circuit of the present invention omits the amplifier in the conventional circuit and reduces the delay time to 34 ps, which is almost half of the delay time of 64 ps in the conventional circuit, and thus provides more clock delay redundancy for the high speed parallel-serial conversion circuit.

Abstract: A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.

Abstract: A level shift circuit includes a first latch circuit configured to receive a clock signal, a digital data signal, a first supply voltage, and a second supply voltage, and generate a first output signal based on the digital data signal. The first output signal has a first voltage level corresponding to the first supply voltage, and a second voltage level corresponding to the second supply voltage. At least one capacitor is configured to receive the first output signal, and retain a voltage value corresponding to the output signal. A second latch circuit is configured to receive the voltage value, a third supply voltage, and a fourth supply voltage, and generate a second output signal based on the voltage value. The second output signal has a third voltage level corresponding to the third supply voltage and a fourth voltage level corresponding to the fourth supply voltage.

Abstract: The invention provides a semiconductor device having a current input type pixel in which a signal write speed is increased and an effect of variations between adjacent transistors is reduced. When a set operation is performed (write a signal), a source-drain voltage of one of two transistors connected in series becomes quite low, thus the set operation is performed to the other transistor. In an output operation, the two transistors operate as a multi-gate transistor, therefore, a current value in the output operation can be small. In other words, a current in the set operation can be large. Therefore, an effect of intersection capacitance and wiring resistance which are parasitic on a wiring and the like do not affect much, thereby the set operation can be performed rapidly. As one transistor is used in the set operation and the output operation, an effect of variations between adjacent transistors is lessened.

Abstract: Provided is a level shift circuit which includes: a first level shift module; a first signal input terminal for providing a first input signal for the first level shift module; a first signal output terminal for providing output from the first level shift module; a second level shift module; a second signal input terminal for providing a second input signal for the second level shift module; a second signal output terminal for providing output from the second level shift module; a drive module connected to the first signal output terminal and the second signal output terminal; and a drive signal output terminal from the drive module. The level shift circuit of the present invention can be applicable for the requirements of BCD process and prevent damages to the high-voltage device due to the excessively high gate voltage.

Abstract: A floating gate driver circuit includes a level shifter, a pass element, a bistable circuit and a control logic circuit, to shift the voltage level of a control signal from a lower one to a higher one. The level shifter or the pass element has loads dynamically controlled by the control logic circuit to filter malfunction caused by dv/dt noise induced by a floating node.

Abstract: A single supply level shifter circuit for shifting the voltage level of an input voltage includes a voltage translation stage and a driver stage. The voltage translation stage receives the input voltage and a voltage supply and generates a first voltage. When a magnitude of the input voltage is LOW, the first voltage is LOW. The first voltage is provided to the driver stage, which inverts the first voltage to generate an output voltage that is at a voltage supply (Vdd) level, thereby level shifting the input voltage.

Abstract: A level shifting circuit includes a first circuit, a second circuit and an output voltage controlling circuit. The first circuit is coupled to an input node, an output node and a first supply voltage node and configured to pull an output voltage at the output node toward the first supply voltage in accordance with an input voltage applied to the input node. The second circuit is coupled to the first circuit, the output node and the second supply voltage node and configured to pull the output voltage toward the second supply voltage in accordance with the input voltage from the first circuit. The output voltage controlling circuit is coupled to the output node and configured to control the output voltage within a range narrower than a range from the first voltage to the second voltage.

Abstract: A level shifting circuit and methodology involving a switching current generator responsive to switching of an input signal for producing a switching current to switch an output signal, and a holding current generator for producing a holding current to hold the logic level of the output signal in accordance with the logic level of the input signal. The holding current is produced independently of the switching current.

Abstract: Level shifting circuitry is provided for generating an output signal in response to an input signal. The level shifting circuitry includes a pulldown path for pulling the output signal to a lower output voltage level in response to a first transition of the input signal and a pullup path for pulling the output signal to a higher output voltage level in response to a second transition of the input signal. Pullup control circuitry places the pullup path in a non-conductive state in response to the output signal being pulled to the higher output voltage level. A keeper path keeps the output signal at the higher output voltage level while the pullup path is non-conductive until the pulldown path pulls the output signal low. A maximum drive current of the pulldown path is greater than a maximum drive current of the keeper path.

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Abstract: A high speed level shifter is provided for converting a low input voltage into a wide-range high output voltage. By utilizing two switching units to improve the latching speed of the latching unit of the level shifter, the duty cycle of the input signal is nearly equal to the duty cycle of the output signal.

Abstract: In a particular embodiment, an apparatus includes a a dynamic circuit structure that includes a dynamic node coupling a precharge circuit, a discharge circuit, and a gated keeper circuit. The gated keeper circuit is enabled by a signal from a discharge delay tracking circuit.

Abstract: A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the first transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.

Abstract: State definition and retention circuits are described. In one embodiment, a circuit includes two cross-connected PMOS transistors, first, second, and third NMOS transistors coupled to the PMOS transistors, an inverter circuit, and an output transistor connected to the PMOS transistors and to an output terminal of the circuit. The second NMOS transistor is connected to an input terminal of the circuit. A drain terminal and a gate terminal of the third NMOS transistor are connected to gate terminals of the PMOS transistors. The inverter circuit is coupled to the first and second NMOS transistors and to the input terminal. The inverter circuit is connected between a first power supply and a first base voltage. The PMOS transistors, the NMOS transistors, and the output transistor are connected between a second power supply and a second base voltage. Other embodiments are also described.

Abstract: A level shifter is disclosed and includes at least four Type 1 transistors and at least four Type 2 transistors. The sources of several Type 1 transistors are electrically connected to a first voltage terminal while the sources of several Type 2 transistors are connected to a second voltage terminal. The level shifter receive an input signal and outputs a logically equivalent output signal with higher voltage, wherein the voltage of the output signal is between the voltages of the first voltage terminal and the second voltage terminal.

Abstract: The present invention provides embodiments of an apparatus that includes a pad configurable for connection to a voltage source that provides a first voltage and a buffer connected to the pad. The buffer includes a plurality of transistors that have nominal breakdown voltages that are less than the first voltage. The buffer is configured to maintain voltage differentials on the plurality of transistors that are less than the break-down voltage of the plurality of transistors during pull-down of a pad voltage from the first voltage to a selected low voltage level or during pull-up of the pad voltage from the selected low voltage level to the first voltage.

Abstract: Circuits and techniques for operating an integrated circuit (IC) with a level shifter circuit are disclosed. A level shifter circuit with input and output terminals is operable to shift an input signal that ranges from a ground voltage to a first positive voltage to an output signal that ranges from the ground voltage to a second positive voltage. The level shifter circuit further includes a first kicker transistor having a first source-drain terminal operable to receive a buffered version of the input signal and having a second source-drain terminal coupled to the output terminal. The first kicker transistor may receive gate signals that turn on the first kicker transistor when the input signal is at the ground voltage and may pull the output terminal to the first positive voltage as the input signal transitions from the ground voltage to the first positive voltage.

Abstract: A semiconductor device includes a first circuit node supplied with a first signal changing between first and second logic levels, a second circuit node supplied with a second signal changing between the first and second logic levels, a third circuit node, a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level, a fourth circuit node supplied with a voltage level being close to or the same as the second logic level, and a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level.

Abstract: A structure is described having a plurality of electronic devices with the same or different internal CMOS voltages; an interconnection between two or more of the electronic devices; driver and receiver circuits which provide selectable input/output voltage levels for interfacing with several generations of CMOS technology, thus allowing chips fabricated in such technologies to communicate using a signal voltage range most suitable for each chip; Circuitry for selecting or adjusting the type of receiver circuit used, thus allowing either the use of a differential comparator circuit with an externally supplied reference voltage, or alternatively, the use of an inverter style receiver with an adjustable threshold, the selection being accomplished by setting the external reference to a predetermined voltage; Circuitry for selecting or adjusting the switching threshold of the inverter receiver circuit, which enables the threshold to be set appropriately for a given input signal voltage range.

Abstract: A level shifter circuit includes a first voltage conversion circuit and a second voltage conversion circuit. The first voltage conversion circuit receives an input signal having an amplitude ranging between a power supply potential (GND) and a power supply potential (VDDL), a power supply potential (VDDH) which is higher than the power supply potential (VDDL) is supplied. Further, a current limiting circuit is provided that limits a current supplied from a power supply line of the power supply potential (VDDH), and outputs a voltage signal with a larger amplitude than that of the input signal according to the input signal. The second voltage conversion circuit is supplied with the power supply potential (VDDH, and outputs an output signal with an amplitude ranging between the power supply potential GND and the power supply potential (VDDH).

Abstract: A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.

Abstract: A dynamic level shifter is disclosed. In one embodiment, a dynamic level shifter circuit may receive an input signal referenced to a first voltage of a first power domain, and may output a corresponding signal referenced to a second voltage into a second power domain. The dynamic level shifter circuit may include an evaluation node that is precharged during a first phase (e.g., the low portion) of a clock signal. During the second phase (e.g., the high portion) of the clock signal, the evaluation node may be either pulled low or high, depending on the state of the input signal. A corresponding output signal, based on the evaluated level on the evaluation node, may be output into the second power domain.

Abstract: A CMOS logic integrated circuit includes a level shifter and a CMOS logic circuit. The level shifter converts a signal of a first logic level to a signal of a second logic level. The signal of the first logic level changes between a first low potential and a first high potential higher than the first low potential. The signal of the second logic level changes between the first low potential and a second high potential higher than the first high potential. The CMOS logic circuit includes a first N-channel type MOSFET and a second N-channel type MOSFET. The second N-channel type MOSFET is connected in series with the first N-channel type MOSFET. A first signal of the first logic level is input into a gate of the first N-channel type MOSFET. A second signal of the second logic level has an inversion relationship with the first signal.

Abstract: A level shift circuit, for outputting a data output signal with a second level via an output inverter after a data input signal with a first level is stored in a latch, includes a level set circuit, when the output data signal outputs with a low level, setting the output data signal to a low level in response to a change of the input data signal. The level set circuit is connected to an output terminal of the output inverter, and has an NMOS transistor having a drain electrode and a source electrode coupled to a ground, wherein the NMOS transistor turns on in response to the input data signal with a high level.

Abstract: An input circuit includes an inverter, a first path control circuit and a second path control circuit. An input of the inverter is connected with a first node. A target inversion potential is higher than an inversion potential of the inverter. The first path control circuit electrically connects an input terminal and the first node when the input potential is higher than the target inversion potential, and blocks off an electrical connection between the input terminal and the first node when the input potential is lower than the target inversion potential. The second path control circuit electrically connects a ground terminal and the first node when the input potential is lower than a second inversion potential which is lower than the target inversion potential and blocks off the electrical connection between the ground terminal and the first node when the input potential is higher than the second inversion potential.

Abstract: A semiconductor device includes a code generator and a level shifter. The code generator generates a code including one bit that is in a first logic state and at least one bit that is in a second logic state. The level shifter outputs signals that are at a first voltage level or at a second voltage level through a plurality of output terminals in response to the code. The level shifter includes a plurality of voltage controllers and a plurality of voltage converters. All but one of the voltage controllers control first signals output through all but one of the output terminals to be at the first voltage level in response to the at least one bit. One of the voltage converters controls a second signal output through the remaining output terminal to be at the second voltage level in response to the first signals.

Abstract: An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal. The output circuit includes an output pMOS transistor connected at a source thereof to a first power supply. The output circuit includes an output nMOS transistor connected between a drain of the output pMOS transistor and ground. The output circuit includes an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor. The output circuit includes a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor. The output circuit includes a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor.

Abstract: A level shifter is provided. The level shifter includes a signal converter connected to an external power source and a ground, first and second output terminals connected to the signal converter, the first and second output terminals being configured to output a bias voltage applied from the external power source, and a switching unit configured to switch a connection state of the signal converter according to an input signal to adjust output voltage values of the first and second output terminals, the switching unit including first and second transistors, the first transistor being of a type that is different from a type of the second transistor, the first and second transistors being connected to each other in series between an input terminal, to which an input signal is applied, and the external power source, gates of the first and second transistors being commonly connected to the second output terminal.

Abstract: There is provided an output buffer circuit which can reduce the time differences of the rise time and fall time of the output voltages of a differential output signal and, furthermore, can make the rise time and fall time match with a good precision. To the resistance elements R1, R2, PMOS transistors Tr5, Tr6 are connected in parallel. At this time, if designating the resistance components of the resistance elements R1, R2 as r1(?), r2(?), designating the resistance components of the PMOS transistors Tr5, Tr6 as rTr5(?) and rTr6(?), and designating the resistance component of the current source I1 as rI1(?), the conditions of (r1//rTr5)=(r2//rI1) and (r2//rTr6)=(r1//rI1) are satisfied. Due to this, the time differences between the rise time and fall time of the output voltages can be reduced and, furthermore, the rise time and fall time can be made to precisely match.

Abstract: In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations.

Abstract: A level converter circuit is provided for converting an input signal of a digital signal having a first signal level into an output signal having a second signal level higher than the first signal level. An amplifier circuit amplifies the input signal and outputs an amplified output signal, and a current generator circuit generates a control current corresponding to an operating current flowing through the amplifier circuit upon change of the signal level of the input signal. A current detector circuit detects the generated control current, and controls the operating current of the amplifier circuit to correspond to the detected control current. The current generator circuit includes series-connected first and second nMOS transistors as inserted between the current detector circuit and the ground. The first nMOS transistor operates responsive to the input signal, and the second nMOS transistor operates responsive to an inverted signal of the input signal.

Abstract: Some embodiments provide an integrated circuit (‘IC’) that includes at least first and second circuits operating at a first voltage. The IC includes, between the first and second circuits, a direct connection comprising a third circuit for transmitting a signal from the first circuit to the second circuit at a second voltage that is lower than the first voltage. At least one of the first and second circuits is a configurable circuit for configurably performing operations.

Abstract: A voltage level shift circuit in which a difference in response characteristic depending on the signal level of an input signal is suppressed. The voltage level shift circuit generates an output signal VOUT having a voltage amplitude different from that of the input signal. An inverter INV2 generates a voltage V1 in the range of VSS to VDDI according to the input signal. An inverter INV3 generates a voltage V2 in the range of VSS to VPERI according to the input signal. An inverter INV4 generates the output signal VOUT according to V1 and V2.

Abstract: A dual supply bidirectional level shifter performs voltage level shifting in two directions, low to high and high to low. A feedback control branch and a control stage inverter are provided that reduce leakage power and allow for low delay time while also allowing for a small circuit footprint.

Abstract: The present invention provides a CML to CMOS conversion circuit comprising a first differential unit, a second differential unit, and an output unit. The output unit comprises a series connection of a first inverter and a second inverter, wherein, a resistor is connected with the first inverter in parallel. The CML to CMOS conversion circuit of the present invention omits the amplifier in the conventional circuit and reduces the delay time to 34 ps, which is almost half of the delay time of 64 ps in the conventional circuit, and thus provides more clock delay redundancy for the high speed parallel-serial conversion circuit.

Abstract: A digital logic circuit and a manufacture method of the digital logic circuit thereof are provided. The digital logic circuit includes a voltage rail, a ground rail, and a plurality of logic circuit rails, wherein each of the logic circuit rails is electrically connected to the voltage rail and the ground rail. The logic circuit rail includes a logic unit and an auxiliary unit electrically connected to the voltage rail and the ground rail. The logic unit includes a logic voltage end electrically connected to the voltage rail and a logic ground end electrically connected to the ground rail. The auxiliary unit includes an auxiliary voltage end electrically connected to the voltage rail and an auxiliary ground end electrically connected to the ground rail. At least one of the width ratio between the auxiliary voltage end and the logic voltage end and the width ratio between the auxiliary ground end and the logic ground end is greater than 1.

Abstract: Circuitry, operating in a high voltage domain, including a high and low voltage inputs, and including a plurality of devices designed to operate optimally powered in a native voltage domain that is lower voltage than said high voltage domain and some devices arranged in two sets. The circuitry including a further input for receiving the high native voltage level. Each set having at least one device, a first set being arranged to receive an intermediate low reference voltage level as a low voltage level signal and the high voltage level as a high voltage level signal and the second set being arranged to receive the high native voltage level as a high voltage level signal and the low voltage level as a low voltage level signal. The intermediate low reference voltage level includes a voltage level generated by subtracting the high native voltage level from the high voltage level.

Abstract: A device includes first through third logic circuits. Each of first and second logic circuits includes a first circuit portion generating a first output signal in response to a first input signal when a second input signal takes a first logic level, and a second circuit portion transferring the first input signal to output the first output signal when the second input signal takes a second logic level. The third logic circuit includes a third circuit portion generating a second output signal in response to the first output signal supplied from the first logic circuit when the first output signal supplied from the second logic circuit takes a third logic level, and a fourth circuit portion generating the second output signal in response to the first output signal supplied with the first logic circuit when the first output signal supplied from the second logic circuit takes a fourth logic level.

Abstract: In some embodiments, an input/output (I/O) circuit sends and receives a high-level signal and a low-level signal via a coupling capacitance provided on a communication line. The I/O circuit includes a receiving portion including a first detection circuit arranged to detect one of the signals and a second detection circuit arranged to detect the other signal, a transmitting portion including a three-value output circuit configured to output one of signals consisting of a high-level signal, a low-level signal, and a high impedance signal, and a control circuit configured to control the receiving portion and the transmitting portion. The control circuit judges a level of an inputted signal depending on detection results of the first detection circuit and the second detection circuit in a receiving state and controls an output value of the three-value output circuit in a transmitting state.

Abstract: A low-swing receiver includes a sense amplifier including a first transistor having a source connected with a first voltage supply and a gate for receiving a control signal, and a second transistor having a source connected with a second voltage supply, a drain connected to a drain of the first transistor, and a gate coupled to a second control signal via a capacitive element. A switching circuit is operative to selectively couple an input signal supplied to the sense amplifier with the gate of the second transistor as a function of a signal generated at an output of the sense amplifier. The sense amplifier is operative in a first mode to store charge in the capacitive element, and is operative in a second mode to impart a voltage on the gate of the second transistor which is indicative of the charge stored in the capacitive element.