Abstract: An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal.

Abstract: A level shift circuit is disclosed. The circuit includes a series circuit of a resistor and a switching device connected between a high voltage side power supply voltage in a secondary side voltage system and a low voltage side power supply voltage in a primary side voltage system, a series circuit of a resistor and a switching device connected between the high voltage side power supply voltage in the secondary side voltage system and the low voltage side power supply voltage in the primary side voltage system, and a latch malfunction protecting circuit operated in the secondary side voltage system to have voltages at a connection point of the resistor and the switching device and at a connection point of the resistor and the switching device inputted.

Abstract: A level shift circuit includes: a pair of first and second P-channel transistors which are connected in a flip-flop manner and whose sources connected to a first power supply line; a pair of first and second N-channel transistors with the first N-channel transistor provided between the first P-channel transistor and a second power supply line and the second N-channel transistor provided between the second P-channel transistor and the second power supply line, in which input signals complementary to each other are inputted to their gates; and a current supply circuit provided between the first power supply line and a drain of the first N-channel transistor and between the first power supply line and a drain of the second N-channel transistor, respectively.

Abstract: A semiconductor device is provided, which includes a switch having a first transistor and a logic circuit having an output terminal. The logic circuit includes a bootstrap circuit having at least one second transistor. The bootstrap circuit is electrically connected to the output terminal. The first transistor and the second transistor have the same conductivity type. Each of the first transistor and the second transistor includes an oxide semiconductor layer including a channel formation region and a pair of gate electrodes with the oxide semiconductor layer provided therebetween.

Abstract: Level shifting circuits and related methods are disclosed herein. The level shifting circuit includes a cross-coupled pull-up circuit coupled to a higher supply voltage, an output signal, and an inverted output signal. An input signal transitions between a ground and a lower supply voltage and an inverted input signal transitions in a direction opposite from the input signal between the ground and the lower supply voltage. A first n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the output signal, and a source coupled to the inverted input signal. A second n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the inverted output signal, and a source coupled to the input signal. The level shifting circuit may be included in an IC with core logic in a first voltage domain and input/output logic in a second voltage domain.

Abstract: A switching circuit for switching a time-varying input signal, the switching circuit comprising: at least one switch including a N-channel MOSFET and a P-channel MOSFET, each having a gate configured to receive a drive signal to change the ON/OFF state of the switch; and a drive circuit configured and arranged so as to selectively apply a pair of drive signals to change the ON/OFF state of the switch, the drive circuit being configured and arranged to generate the drive signals as a function of (a) a pair DC signal components sufficient to change the ON/OFF state of the switch and (b) a pair of time-varying signal components as at least a partial replica of the signal present on the source terminal of each MOSFET so that when applied with the DC signals to the gates of the n-channel MOSFET and p-channel MOSFET respectively, the drive signals will be at the appropriate level to maintain the ON/OFF state of the switch and keep the gate-source voltages of each MOSFET within the gate-source breakdown limit of the

Abstract: The invention provides a semiconductor device having a current input type pixel in which a signal write speed is increased and an effect of variations between adjacent transistors is reduced. When a set operation is performed (write a signal), a source-drain voltage of one of two transistors connected in series becomes quite low, thus the set operation is performed to the other transistor. In an output operation, the two transistors operate as a multi-gate transistor, therefore, a current value in the output operation can be small. In other words, a current in the set operation can be large. Therefore, an effect of intersection capacitance and wiring resistance which are parasitic on a wiring and the like do not affect much, thereby the set operation can be performed rapidly. As one transistor is used in the set operation and the output operation, an effect of variations between adjacent transistors is lessened.

Abstract: A level shifter having first and second P-type transistors cross coupled at an output port thereof, wherein there are first and second voltage rising circuits coupled at gates of the first and second P-type transistors, respectively. A voltage level at the gate of the first P-type transistor is associated with an output signal of the level shifter. When an input signal, operated by a first power, of the level shifter rises, the first voltage rising circuit couples a second power to the gate of the first P-type transistor to speed up the rising of the output signal. The voltage level at the gate of the second P-type transistor is associated with an inverted output signal. When the input signal falls, the second voltage rising circuit couples the second power to the gate of the second P-type transistor to speed up the rising of the inverted output signal.

Abstract: A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.

Abstract: A receiver for receiving a reduced swing signal from a transmission channel is disclosed, in which the swing of the reduced swing signal is less than the power supply of the receiver and possibly is less than the power supply of the transmitter. The receiver comprises a level shifter for offsetting the reduced swing signal, and an amplifier which receives both the reduced swing signal and its offset to produce a full swing signal output referenced to the power supply of the receiver. The full swing signal can thereafter be buffered, and eventually can be captured by a clock. Optionally, the disclosed reduced swing receiver also contains calibration circuitry for improving the integrity of the full swing signal output, and in particular for countering the effects of process, and in some embodiments temperature, variations, which alter the characteristics of the transistors which make up the receiver circuitry.

Abstract: A single-supply digital voltage level shifter has a first inverter having a first input for receiving an input signal with a first voltage swing, and a first output for outputting a first output signal. A second inverter has a second input for receiving the first output signal, and a second output for outputting a second output signal with a second voltage swing, where the second output signal is a level-shifted version of the input signal. A comparison stage includes a first comparison stage input for receiving the input signal, a second comparison stage input for receiving the second output signal, and a comparison stage output for outputting a comparison stage output control signal. A control stage is connected in a circuit branch of the first inverter and has a control stage switch that assumes a non-conducting state dependent on a logical state of the comparison stage output control signal.

Abstract: A logical level translator includes a first reference voltage provider, a second reference voltage provider, and a switching circuit. The first reference voltage provider provides a first reference voltage signal with a first logic level to a first connection terminal. The second reference voltage provider provides a second reference voltage signal with a second logic level to a second connection terminal. The switching circuit switches on a connection between the first connection terminal and the second connection terminal when a digital signal input to the first connection terminal or the second connection terminal is a logic high level signal. Then switches off the connection between the first connection terminal and the second connection terminal when the digital signals is a logic low level signal.

Abstract: Level shifter and related apparatus are provided. The level shifter has first to sixth transistors, wherein drains of the first and the second transistors respectively are coupled to drains of the fifth and the sixth transistors as two output nodes of the level shifter, gates of the fifth and the sixth transistors are two input nodes of the level shifter. A source, a drain and a gate of the third transistor are respectively coupled to a gate of the first transistor, the drain of the sixth transistor and a first bias voltage, and a source, a drain and a gate of the fourth transistor are respectively coupled to a gate of the second transistor, the drain of the fifth transistor and a second bias voltage.

Abstract: Circuit blocks and respectively convert high-voltage logic signals in which two logical values are expressed by a first signal potential and a second signal potential into low-voltage logic signals in which the two logical values are expressed by a third signal potential at least as large as the first signal potential and a fourth signal potential that is the third signal potential to which a positive voltage has been added and which is no greater than the second signal potential, and outputs the converted logic signals. The transistors in the circuit block are of the form of replacing the respective transistors of the circuit block with elements of opposite polarity, so that when the third signal potential is changed and operation of one of the circuit blocks and becomes difficult, the other operates normally. Consequently, stable level conversion can be accomplished.

Abstract: In one embodiment of the invention, a programmable device, such as an FPGA, has a programmable input buffer with a VCCIO-powered buffer stage for high-voltage signaling and a VCC-powered buffer stage for low-voltage signaling. In addition to a main driver section, the VCCIO-powered buffer stage has a mixed-mode section for handling multiple different over-drive and multiple different under-drive conditions, a hysteresis section for providing multiple different trip-point hysteresis modes of operation, and a level-shifting section with look-ahead circuitry that enables the main driver section to be implemented with low-power, high-threshold devices, while still enabling the VCCIO-powered buffer stage to operate with low skew and high speed.

Abstract: A voltage level shifter with an input transistor pair, a cross-coupled load chain transistor pair and a pair of current sources, effects reduced power consumption through the use of the cross-coupled load chain transistor pair to minimize the DC current component present in known voltage level shifters. In specific embodiments, feedback elements may be used to minimize delays in signal transitions. A reference voltage that corresponds to a current capability of the input transistor pair may be used to regulate the current sources in the load chain. Changes in a swing of the input signal voltage received by the input transistor pair may be reflected in corresponding changes to the reference voltage. The voltage level shifter may be of particular use in a buffer.

Abstract: A nonvolatile semiconductor memory apparatus includes a control unit configured to generate a select signal and a driving control signal in response to a first enable signal and a second enable signal; a level shifting unit configured to enable a first shifting signal or a second shifting signal to a level of a pumping voltage in response to the select signal and the driving control signal; a first switching unit configured to apply a program voltage to a word line when the first shifting signal is enabled to the level of the pumping voltage; and a second switching unit configured to apply a pass voltage to the word line when the second shifting signal is enabled to the level of the pumping voltage.

Abstract: A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the fifth transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.

Abstract: Methods and apparatus provide for voltage level shifting with concurrent synchronization. The apparatus includes level shifting logic that in response to a non-level shifted clock signal from a first voltage domain, provides level shifted concurrently synchronous differential data signals in a second voltage domain based on pre-level shifted differential data signals from the first voltage domain. The first voltage domain may be, for example, a core logic voltage domain in which core logic operates. The second voltage domain may be, for example, an input/output (I/O) voltage domain in which an I/O buffer operates. The voltage level of the level shifted concurrently synchronous differential data signals is shifted from the pre-level shifted differential data signals, and the timing of the level shifted concurrently synchronous differential data signals is concurrently referenced to the non-level shifted clock signal.

Abstract: A level shifter includes first and second NMOS transistors with gates connected to inverted circuit and circuit inputs, respectively, sources connected to the ground, and drains connected to circuit and inverted circuit outputs, respectively. First and second PMOS transistors have their gates connected to the inverted circuit and circuit outputs, respectively, and sources connected to the high voltage supply. A third PMOS transistor of the multiple independent gate type has its source connected to the drain of the first PMOS transistor, drain and back-gate connected to the circuit output, and front-gate connected to the inverted circuit input. A fourth PMOS transistor of the multiple independent gate type has its source connected to the drain of the second PMOS transistor, drain and back-gate connected to the inverted circuit output, and front-gate connected to the circuit input.

Abstract: A level shifter includes a first input circuit, a first load circuit, a second input circuit, and a second load circuit. The first input circuit receives a first input signal and a second input signal that swing between a first high power voltage and a first low power voltage. The first load circuit generates a high voltage, a sub-high voltage, a low voltage, and a sub-low voltage. The second input circuit receives a first voltage pair including the high voltage and the low voltage, and a second voltage pair including the sub-high voltage and the sub-low voltage. The second load circuit generates an output signal that swings between a second high power voltage and a second low power voltage.

Abstract: A leakage current reduction circuit comprising a transmission gate, a feedback channel and a controller is placed between a first device supplied with a first voltage potential and a second device supplied with a second voltage potential. The voltage potential mismatch between the first device and the second device may cause a leakage current flowing through the input stage of the second device. By employing the low leakage power detection circuit, a logic high state generated from the first device can be converted into a logic high state having an amplitude approximately equal to the second voltage potential.

Abstract: Level shifting circuits and related methods are disclosed herein. The level shifting circuit includes a cross-coupled pull-up circuit coupled to a higher supply voltage, an output signal, and an inverted output signal. An input signal transitions between a ground and a lower supply voltage and an inverted input signal transitions in a direction opposite from the input signal between the ground and the lower supply voltage. A first n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the output signal, and a source coupled to the inverted input signal. A second n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the inverted output signal, and a source coupled to the input signal. The level shifting circuit may be included in an IC with core logic in a first voltage domain and input/output logic in a second voltage domain.

Abstract: A digital signal voltage level shifter includes an edge detector that detects assertion of a digital input signal from a first logic circuit in a source voltage domain, and an output module triggered by the edge detector for asserting a digital output signal corresponding to the digital input signal for a second logic circuit in a destination voltage domain. The edge detector and the output module are supplied with power only from a power supply of the destination voltage domain and are not connected to a power supply of the source voltage domain.

Abstract: An integrated circuit (IC) includes an input/output (I/O) circuit supporting high-speed operation and multiple I/O logic-level swings. The I/O circuit includes a first output signal chain to generate outputs with a first logic level swing, and a second output signal chain to generate outputs with a second logic level swing. The outputs of the first output signal chain and the second output signal chain are connected to a same output pad of the IC. Transistors in the first output signal chain and the second output signal chain are fabricated using corresponding gate oxide characteristics. The second output signal chain includes protection circuitry to prevent transistors in the second output signal chain from being subjected to voltage stresses beyond a safe limit. An input circuit in the I/O circuit similarly includes multiple input signal chains to enable reception of input signals of different logic-level swings from a same input pad.

Abstract: A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage. The second switch device is coupled to the first switch device for outputting a first operational voltage as the output voltage according to the first voltage. The first control switch is coupled to the first switch device for receiving the first voltage. The third switch device is coupled between the first control switch and the first operational voltage and controlled by the output voltage. The second level-switching device is coupled to the first level-switching device for receiving the input voltage and accordingly outputting a second operational voltage as the output voltage.

Abstract: A voltage level shifting circuit may include a differential first-stage level shifter that receives a binary input signal and generates a non-inverted first-stage shifted output signal and an inverted first-stage shifted output signal, a second-stage level shifter that receives the first-stage shifted output signals and generates a non-inverted second-stage shifted output signal and an inverted second-stage shifted output signal, and a signal generator that generates a level shifted final output signal corresponding to the binary input signal that is based on the non-inverted second-stage shifted output signal and the inverted second-stage shifted output signal. The voltage swing of the first stage output signals may be limited to swing between a non-zero lower value and an upper value that is less than or equal to a source-to-drain voltage rating of transistors in the differential first-stage level shifter.

Abstract: A programmable integrated circuit having a plurality of individually controlled voltage domains. Each voltage domain includes logic circuitry powered by a respective power network. The voltage magnitude of each power network is independently selectable. Each of a plurality of level shifters couples a first and second one of the voltage domains, couples a first port of the logic circuitry of the first voltage domain to a second port of the logic circuitry of the second voltage domain, and shifts from a first signaling protocol of the first port to a second signaling protocol of the second port. The first signaling protocol is referenced to the voltage magnitude of the first voltage domain, and the second signaling protocol is referenced to the voltage magnitude of the second voltage domain. Means are disclosed for controlling the voltage magnitude of the respective power network of one or more of the voltage domains.

Abstract: A level shifting circuit includes a string of diodes and an active load across which the control voltage is applied. A resistor is coupled across the lowermost diode to develop a switch control voltage. At low control voltage, the diode string allows no current to be developed across the resistor. At higher control voltage, the diodes conduct and the active load takes up the difference between the control voltage and the diode string voltage. A switch responds to the resistor voltage, for switching a load On and OFF. A second active load takes up excess load supply voltage.

Abstract: A transceiver for controlling a swing width of an output voltage includes a transmitter and a receiver for receiving an output voltage of a transmitter. The transmitter includes a first signal converter that outputs changed data generated by changing a voltage level of data in response to a mode control signal for selecting a test mode or a normal mode, an output voltage control circuit for controlling a voltage level of an output node of the transmitter in response to the changed data, and a first termination circuit for supplying a changed power supply voltage generated by changing a voltage level of a power supply voltage of the output node of the transmitter, or is turned off, in response to a test mode enable signal or the changed data. The receiver includes a second termination circuit that operates as a resistor having a resistance value that varies in response to the test mode enable signal or a test mode disable signal.

Abstract: A level shift circuit includes a level shift section for receiving a low potential signal oscillating between a high potential and a ground potential and converting it into a high potential signal oscillating between the high potential and the ground potential, the level shift section being connected to at least a high potential power supply for generating the high potential, a low potential power supply for generating the low potential, and a ground power supply for generating the ground potential, an inverter section for inverting-amplifying the high potential signal from the level shift section, and an N-type MOS transistor for supplying the ground potential to the inverter section, the N-type MOS transistor being connected in series to the inverter section between the high potential power supply and the ground power supply and having its gate electrode connected to the low potential power supply.

Abstract: A level converter for providing an output signal at a circuit output based on an input signal includes an output coupling circuit formed to provide an output signal based on a first partial output signal and a second partial output signal, a driver circuit formed to provide the second partial output signal such that the second partial output signal is switchable between two different signal levels depending on the state of the input signal, wherein an input of the driver circuit is capacitively coupled to the input of the level converter in order to allow for switching between the signal levels of the second partial output signal by the capacitive coupling in response to a change in the state of the input signal, and a holding circuit formed to keep the state of the second partial output signal constant in case of a constant state of the input signal.

Abstract: An integrated circuit structure includes a latch having a first output node and a second output node complementary to each other. A first pre-charge transistor has a source-drain path coupled between a positive power supply node and the first output node. A second pre-charge transistor has a source-drain path coupled between the positive power supply node and the second output node. The integrated circuit structure further includes a delay-inverter coupled between a signal input node and inputs of a first NMOS transistor and a second NMOS transistor in the latch. The delay-inverter is configured to allow one of the first pre-charge transistor and the second pre-charge transistor to pre-charge a respective one of the first output node and the second output node before an input signal at the signal input node arrives at a gate of a respective one of the first NMOS transistor and the second NMOS transistor.

Abstract: A level shifter and method are provided for balancing a duty cycle of a signal. An input circuit receives a differential logic signal with two complimentary logic levels. A level transition balancing circuit balances the rise and fall times of a level shifted version of each complimentary logic level during a transition from a first to a second of the logic levels and a level shift. A logic element stores and provides outputs of the level shifted versions of the logic levels. The level transition balancing circuit can include a capacitor in parallel with a transfer element for each input. The capacitor destabilizes inputs to the logic element and balances the transition using a capacitance and a level previously stored in the logic element.

Abstract: A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current when the first signal transitions from the logic LOW to the logic HIGH.

Abstract: A method and apparatus are disclosed to control one or more input output (I/O) pads. An input signal is translated to an output signal having a desired logic level using a first latch loop. The state of the first latch loop is maintained by a second latch loop, integrated with the first latch loop, when a latching indication is received. The integration between the first latch loop and the second latch loop is such that the second latch loop creates an input-output connection if transmission gates in the second latch loop are conductive, and disables the input-output connection if the transmission gates are not conductive.

Abstract: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.

Abstract: An output stage includes a system input and a system output, a first transistor having a first control input and a first controlled path, and a second transistor having a second control input and a second controlled path. The second controlled path is in series with the first controlled path and the system output. A first current-controlled voltage source has an input that is electrically connected to the system input. The first current-controlled voltage source has an output that is electrically connected to the first control input of the first transistor. A second current-controlled voltage source has an input that is electrically connected to the system input. The second current-controlled voltage source has an output that is electrically connected to the second control input of the second transistor.

Abstract: A multiple supply voltage device includes an input/output (I/O) network operative at a first supply voltage, a core network coupled to the I/O network and operative at a second supply voltage, and a power-on-control (POC) network coupled to the I/O network and the core network. The POC network is configured to transmit a POC signal to the I/O network and includes an adjustable current power up/down detector configured to detect a power state of the core network. The POC network also includes processing circuitry coupled to the adjustable current power up/down detector and configured to process the power state into the POC signal, and one or more feedback circuits. For reducing the leakage current while also improving the power-up/down detection speed, the feedback circuit(s) are coupled to the adjustable current power up/down detector and configured to provide feedback signals to adjust a current capacity of the adjustable current power up/down detector.

Abstract: A buffer circuit includes an input configured to receive an input signal; and a buffer configured to generate an output signal based on the input signal. In an embodiment, the output signal has a linear relationship with the input signal when the input signal is within the input voltage range; and the buffer circuit further includes a level-shifting circuit coupled with the input, wherein the level shifting circuit determines an input voltage range, and wherein one of an upper limit and a lower limit of the input voltage range is within 50 millivolts from a supply rail voltage. In another embodiment, the buffer circuit further includes a programmable chopping module coupled with the buffer, wherein the programmable chopping module is programmable with a selected configuration from a plurality of configurations, and wherein the programmable chopping modulates the input signal based on the selected configuration.

Abstract: A level shifting circuit with a thin gate transistor connected to the input of the output stage is presented. The level shifting circuit has an input stage that receives an input that is at first voltage. A transistor with a thin gate oxide has one terminal connected to the input stage and another terminal coupled to an input of the output stage. The output stage of the level shifting circuit is implemented with thick gate oxide transistors.

Abstract: A level shifter and method are provided for balancing a duty cycle of a signal. An input circuit receives a differential logic signal with two complimentary logic levels. A level transition balancing circuit balances the rise and fall times of a level shifted version of each complimentary logic level during a transition from a first to a second of the logic levels and a level shift. A logic element stores and provides outputs of the level shifted versions of the logic levels. The level transition balancing circuit can include a capacitor in parallel with a transfer element for each input. The capacitor destabilizes inputs to the logic element and balances the transition using a capacitance and a level previously stored in the logic element.

Abstract: A logic circuit includes a logic gate unit, an inverter, and a switching circuit. The logic gate unit receives a power supply voltage and an input signal to output a first signal. The inverter receives the first signal to output a second signal. The switching circuit provides one of first and second power supply voltages as the power supply voltage of the logic gate unit in response to the first and second signals. The first power supply voltage and the second power supply voltage have different voltage levels, thus enabling stable level shifting.

Abstract: An exemplary embodiment of such a system includes: a level shifter operative to transform an input signal into an output signal, the level shifter includes: a voltage distributor operative to receive the input signal and distribute potential levels at a first node and a second node to respectively output a first signal and a second signal, and the voltage distributor includes: a current limiter, operative to provide a limited current passing through the first node; a switch, operative to selectively establish an electrical connection between the first node and the second node; and a first transistor having a first electrode, a second electrode, and a first control electrode, wherein the first electrode is connected to the second node, the second electrode is utilized to receive the input signal, and the first control electrode is coupled to the first node; and an output circuit, operative to generate the output signal.

Abstract: A semiconductor device comprises a floating body type transistor and first and second circuits. The transistor has a floating body and a source-drain path inserted between first and second circuit nodes. The first circuit supplies a first signal to the gate of the transistor, and the first signal changes between a first logic level that holds the transistor in a non-conductive state and a second logic level that directs the transistor into a conductive state. The second circuit supplies a first voltage level near the second logic level to the first circuit node and supplies a second voltage level near the second logic level to the second circuit node, each as a level in a state where the transistor is not utilized. Thereby the gate capacitance of the transistor can be kept small as viewed from the gate, and high-speed operation and a reduction in consumption current can be achieved.

Abstract: A level shifter receives an input signal of either a first lower voltage or a first upper voltage which form a voltage pair, and level-shifts the input signal to output an output signal of either a second lower voltage or a second upper voltage. An SR flip-flop generates an output signal which is switched to the second upper voltage upon receiving a positive edge via its set terminal, and is switched to the second lower voltage upon receiving a positive edge via its reset terminal. An AND gate generates the logical AND of a feedback signal having the inverted logical level of the output signal of the SR flip-flop and the input signal, which is output to the set terminal of the SR flip-flop. A NOR gate generates the logical NOR of the feedback signal and the input signal, which is output to the reset terminal of the SR flip-flop.

Abstract: A level shifter circuit includes an input circuit, an inverter, a pull-up circuit, and a pull-down circuit. The input circuit generates a pull-up signal in response to an input signal using charge from a supply voltage. The inverter inverts the input signal to generate a pull-down signal. The inverter comprises complementary transistors that receive charge from the supply voltage. The pull-up circuit pulls a level shifted output signal of the level shifter circuit to the supply voltage in response to the pull-up signal. The pull-down circuit pulls the level shifted output signal to a low voltage in response to the pull-down signal.

Abstract: A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage.

Abstract: Apparatus and methods efficiently provide compatibility between CMOS integrated circuits and voltage levels that are different from that typically used by modern integrated circuits. For example, backwards compatibility can be desirable. Older signaling interfaces operate at different voltage levels than modern CMOS integrated circuits and conventional circuits to interface with these other signaling interfaces exhibit relatively high power consumption. In the context of a transmitter with a P-type substrate, an output driver is embodied in a deep N-well with retrograde P-wells and is biased with voltage biases that can float with respect to the VDD and VSS supplies provided to the CMOS integrated circuit. In the context of a receiver with a P-type substrate, a portion of a receiver is embodied in a deep N-well and biased with floating voltage biases such that the receiver is compatible with signaling received from a signaling technology with disparate voltage levels.

Abstract: A thin-film logic circuit, which can be fabricated entirely of TFTs of the same conductivity type, includes a logic stage connected to a supply voltage and a level shifter connected to a wider voltage range provided by the supply voltage and ground. The logic circuit produces output signals with full rail-to-rail signal range from ground to the supply voltage and can implement or include a basic logic component such as an inverter, a NAND gate, or a NOR gate or more complicated circuits in which many basic logic components are cascaded together. Such logic circuits can be fabricated directly on flexible structures or large areas such as in flat panel displays.