Abstract: To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. The semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. When the semiconductor device returns to a normal state, the second potential is supplied, so that the potential of a node in the level shifter circuit increases. To utilize the increase in the second potential or suppress malfunction due to the increase in the potential, capacitors are provided in the level shifter circuit. This inhibits unexpected operation of a transistor in the level shifter circuit.

Abstract: A level shifting circuit operates at a high voltage level without stressing the transistors. The circuit has the ability to swing between large supply domains. Multiple output voltage levels are supported for the level shifted signal. Additionally, output nodes are stably driven to supply voltage levels that do not vary with respect to process corner and temperature.

Abstract: An integrated circuit (IC) includes a first circuit that is powered by a first supply voltage, and a second circuit that is powered by a second supply voltage. The second supply voltage has a lower level than the first supply voltage. The IC further includes a power management circuit. The power management circuit includes a switch-mode DC-DC regulator that is coupled to a plurality of pins of the IC in a pre-defined configuration. The power management circuit provides the first and second supply voltages to power up the IC in a default configuration without knowledge of the pre-defined configuration.

Abstract: An oscillator includes an input terminal, an oscillation circuit section configured to cause a resonator to resonate to output an oscillator signal, a digital input section to which a signal for controlling an oscillation frequency of the oscillation circuit section is input via the input terminal, and a first bias circuit section including a constant current source configured to supply a reference current to the digital input section.

Abstract: System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling.

Abstract: A circuit may include an input terminal configured to receive an input signal with a first voltage swing and an output terminal. The circuit may also include a first transistor, a second transistor, a third transistor, and a control circuit. The control circuit may be coupled to the input terminal, a gate terminal of the first transistor, and a gate terminal of the second transistor. The control circuit may be configured to adjust voltages provided to the gate terminals based on the input signal such that the first transistor conducts in response to the input signal being at a first logical level and the second transistor conducts in response to the input signal being at a second logical level to generate an output signal output on the output terminal. The second voltage swing of the output signal may be different from the first voltage swing of the input signal.

Abstract: Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. The output of the OR gate may be coupled with an input of an I/O buffer.

Abstract: There are provided with a strobe driving circuit, a strobe driving method, an array substrate and a display apparatus. The strobe driving circuit includes: a first driving unit for receiving a timing control signal, generating a first strobe driving signal based on the power signal under the control of the timing control signal; a first energy storing unit, storing energy based on the first strobe driving signal; a second driving unit connected to the first energy storing unit, for generating a second strobe driving signal based on the energy stored by the first energy storing unit under the control of the timing control signal. In the technical solution according to the embodiments of the application, the number of required bonding pads is reduced, so that the complexity of semiconductor manufacturing process and the difficulty of the manufacturing procedure are reduced.

Abstract: Various implementations described herein are directed to a keeper circuit coupled to a bitline input path and configured to provide a first voltage source signal to the bitline input path based on a keeper enable signal. The keeper circuit may include an NMOS transistor. Further, a logic device may be coupled to the bitline input path and configured to receive the bitline input signal, receive the first voltage source signal from the keeper circuit, and provide an inverted bitline input signal as an output signal.

Abstract: In some embodiments, a method includes providing an input voltage to a level-shifting circuit, where the input voltage is in a first power domain, shifting the input voltage to an output voltage using the level-shifting circuit, where the output voltage is in a second power domain different from the first power domain, and where the level-shifting circuit is coupled to power supply voltages in the second power domain. The method further includes in response to an electrostatic discharge (ESD) event, turning off a first transistor coupled between a first node of the level-shifting circuit and a reference low voltage level of the second power domain.

Abstract: Apparatus for converting a first input signal from a first voltage domain to an output signal for a second voltage domain, the apparatus configured to operate within the first voltage domain or within the second voltage domain. The apparatus comprising input driver circuitry configured to generate second input signal based on the first input signal and a control signal received by input driver circuitry. The apparatus also comprising selection circuitry configured to generate a selection signal based on the control signal. The apparatus also comprising cross-coupled circuitry configured to generate a level-shifted signal at an intermediate node based on the first input signal, the second input signal, and the selection signal. The cross-coupled circuitry comprises a first pair of parallel transistors and a second pair of parallel transistors. The apparatus further comprising output driver circuitry configured to generate output signal for the second voltage domain based on the level-shifted signal.

Abstract: A low voltage to high voltage level translator that is independent of the high supply voltage. The translator includes first and second transistors with current terminals coupled to a first supply voltage and control terminals that are cross-coupled to one of first and second output nodes. The translator includes first and second input stages each having a first current terminal coupled to a second supply voltage, having a second current terminal coupled to one of the first and second output nodes, and having a control terminal coupled to one of first and second input nodes. The translator further includes first and second resistors, each having a first terminal coupled to the second current terminal of one of the first and second transistors and a second terminal coupled to one of the first and second output nodes. The added resistors enable wider voltage translation and avoid conventional configuration issues.

Abstract: A semiconductor circuit including a level shifter circuit that, in accordance with supply of a power supply voltage, converts a potential of an input signal from a first potential to a second potential that is higher than the first potential and outputs the second potential through an output node; a potential supply circuit, to which a reset signal at a level in accordance with the power supply voltage is supplied, that supplies a predetermined potential in accordance with the level of the reset signal; and a control circuit that controls the potential of the output node of the level shifter circuit in accordance with the level of the predetermined potential supplied from the potential supply circuit.

Abstract: An interface circuit includes a pre-driver that converts the single-ended signal to an intermediate differential signal having a first voltage swing responsive to a first supply voltage supplied to the pre-driver. An output driver is coupled to receive the intermediate differential signal from the pre-driver to convert the intermediate differential signal to an output differential signal coupled to be received by a load coupled to the output driver. The output differential signal has a second voltage swing responsive to a second supply voltage supplied to the output driver. An internal regulator is coupled to receive a variable supply voltage to supply the second voltage to the output driver. The second supply voltage is generated in response to a bias signal. A replica bias circuit is coupled to receive the variable supply voltage to generate the bias signal.

Abstract: Devices and circuits for high voltage switch (HVS) configurations. HVS may pass high voltage without suffering voltage drops. HVS may also guarantee safe operations for p-mos transistors. HVS may not sink current in its steady state. Further, HVS may select between two or more different voltage values to be passed onto the output node even after the high voltage has already been fully developed on the high voltage supply line.

Abstract: A liquid discharging apparatus includes a modulation portion that generates a modulation signal obtained by pulse-modulating a source signal; a switching element that generates an amplification modulation signal obtained by amplifying the modulation signal; a low-pass filter that generates a driving signal by demodulating the amplification modulation signal; a piezoelectric element that is displaced by applying the driving signal; a selection portion that is configured to include a transistor and selects whether or not the driving signal is applied to the piezoelectric element; and a detection portion that detects lowering of a power source voltage supplied to the selection portion. The detection portion performs control for lowering a voltage of the driving signal if lowering of the power source voltage is detected.

Abstract: The number of level shifters is reduced in a decode circuit of a nonvolatile memory. A semiconductor device is configured with an electrically rewritable nonvolatile memory cell array, and a decode circuit which generates a selection signal to select a driver for a memory gate line (word line). The decode circuit includes a level shifter to step up a signal after predecode. The selection signal is generated by decoding predecode signals which are stepped up by the level shifter in the logical operation circuit. A logic gate to invert the logical level of the predecode signal depending on an operation mode is provided in the preceding stage of each level shifter. When decoding the stepped-up predecode signal, the logical operation circuit performs a different logical operation depending on the operation mode.

Abstract: An apparatus includes an input difference determination circuit configured to determine a digital value based on a difference between first and second input signals, and a charge pump configured to provide a supply voltage to the first and second transistors to determine the digital value. The input difference determination circuit includes a first transistor and a second transistor cross-coupled to each other. A method includes generating a voltage using a charge pump, providing the voltage to an input difference determination circuit, and determining a digital value based on a difference between first and second input signals by the input difference determination circuit.

Abstract: A comparator includes an input-stage circuit that sets, in a first operating state, two voltage signals in a first voltage state, and changes, in a second operating state, the two voltage signals from the first voltage state to a second voltage state at different speeds, a latch-stage circuit that includes two field effect transistors and two inverters, the two field effect transistors receiving the two voltage signals at control nodes and disposed between two output nodes and a predetermined potential, the two inverters cross-coupled between the two output nodes and placed in an inactive state in the first operating state and in an active state in the second operating state, and a control circuit that controls current capacities in two paths through which drive voltages are applied to the two inverters, causing the current capacities to be different during at least part of a period of the second operating state.

Abstract: A method for converting data signals from one power supply voltage domain for use in another power supply voltage domain. The method includes receiving the data signal at a first node of the integrated circuit, wherein the first node is within the first power supply voltage domain. The method also includes generating a first intermediate differential signal from the data signal via a first conversion circuit of the integrated circuit. The method further includes communicating the first intermediate differential signal to a first cross-coupled latch, wherein the first cross-coupled latch generates a first output signal based on the first intermediate differential signal. The method also includes outputting the first output signal from a second node of the integrated circuit, wherein the second node is in the second power supply voltage domain. Other embodiments, such as an integrated circuit, and an input device, are also provided.

Abstract: A driving module, for a display device, includes a first transistor comprising a gate coupled to a first node, a drain coupled to an output end, and a source coupled to a first positive voltage source; a second transistor comprising a gate coupled to a second node, a drain coupled to the output end, and a source coupled to a first negative voltage source; and a voltage generating unit, coupled to an input end, a second positive voltage source and a second negative voltage source for generating a first voltage at the first node and a second voltage at the second node; wherein a difference between a first positive voltage of the first positive voltage source and the first voltage is smaller than a first threshold and a difference between a first negative voltage of the first negative voltage source and the second voltage is smaller than a second threshold.

Abstract: Disclosed is an integrated circuit voltage level shifter including: a first set of pull-up transistors to selectively pull an output voltage towards a high voltage source level based on an input; a second set of pull-down transistors adapted to selectively pull the output voltage towards a lower voltage source level based on the input and a third set of transistors to limit current flow through the second set of pull-down transistors and to mitigate snapback of the second set of pull-down transistors using a bias gate voltage.

Abstract: Circuits and techniques for operating an integrated circuit (IC) with a transition accelerator circuit are disclosed. A disclosed circuit includes an inverter with an input, first and second power supply inputs, and an output. The input may receive an input signal from an external component. A first multiplexer, operable to couple either a first voltage level or a second voltage level to the first power supply input based on a control input, is coupled to the first power supply input of the inverter. An input of a delay circuit is coupled to the output of the inverter and an output of the delay circuit is coupled to the control input of the first multiplexer.

Abstract: An electrostatic discharge (ESD) protection device is formed in an integrated circuit (IC) with a DC-DC converter. The DC-DC converter includes a high-side switch and a low-side switch in series. The ESD protection device includes a first ESD protection component coupled to the high-side switch in parallel and a second ESD protection component coupled to the low-side switch in parallel. When an ESD occurs, the first ESD protection component is turned on before the high-side switch functions and the second ESD protection component is turned on before the low-side switch functions.

Abstract: Described is an apparatus which comprises: a pre-driver coupled to a transmitter, the transmitter having a differential output; and a tuning circuit operable to couple to the differential output to tune the pre-driver of the transmitter according to a common mode noise signature of a common mode signal derived from the differential output.

Abstract: A method for voltage level shifting comprises several steps. A data signal in a first voltage domain is received by a voltage level shifter. The received data signal is shifted to a second voltage domain by the voltage level shifter, where the voltage level shifter is configured as a function of the shifted data signal. The shifted data signal is outputted.

Abstract: A level shifter includes: a first cascode portion, including a first transistor of a first conductivity type and a second transistor of a second conductivity type which are cascode-coupled to each other, configured to transmit a first input signal; a second cascode portion, including a third transistor of the first conductivity type and a fourth transistor of the second conductivity type which are cascode-coupled to each other, configured to transmit a second input signal; a latch portion configured to retain a first output signal and a second output signal obtained by changing, based on a first voltage obtained by boosting a power supply voltage, potential levels of the first input signal and the second input signal; and a potential-difference suppression circuit, coupled in parallel to the first cascode portion, configured to control a potential difference between source and drain of each of the first transistor and the second transistor.

Abstract: A receiver circuit including an external terminal, a level shifter, a reset circuit, and an inverting circuit is provided. The external terminal receives the external signal. The level shifter shifts a voltage swing range of the external signal to generate a level shifting signal. The level shifter includes a pull-up unit and a pull-down unit coupled in series. The pull-up unit and the pull-down unit are alternatively switched respectively according to the external signal and the internal signal, and thus a leakage path of the level shifter is cut off for different states of the external signal. The reset circuit couples the external terminal and the level shifter and provides a reset path according to the external signal for assisting the switching of the pull-up unit and the pull-down unit. The inverting circuit couples the level shifter and inverts the level shifting signal to generate the internal signal.

Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell configured to be powered from a first voltage source, a bitline, and a write driver configured to write to the memory cell through the bitline, the write driver comprising a pull-up circuit to pull up bitline voltage towards a second voltage source while using the first voltage source to limit the bitline voltage, the first and second voltage sources being in different voltage domains.

Abstract: A charge pump assist circuit to assist a voltage level shifter to toggle an output based on an input. The charge pump assist circuit may be implemented to toggle the output at a higher rate than the voltage level shifter. The voltage level shifter may be biased with an undivided voltage rail, such as an operating voltage of the charge pump assist circuit, rather than a divided voltage rail, while maintaining or increasing a toggle rate. The charge pump assist circuit may include a non-overlapping control generator to generate non-overlapping differential controls, and may further include first and second charge pump multipliers to increase voltages of the differential controls by a multiple of the operating voltage.

Abstract: Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein at least one chip layer has calibration control circuitry that is dedicated to calibrating/configuring one or more functional chip layers, and/or performance instrumentation control circuitry for testing and collecting performance data of one or more functional chip layers.

Abstract: Dual-voltage detectors and related methods are disclosed that receive control signals from a first supply voltage domain and provide multiple disable outputs within a separate supply voltage domain. The disclosed embodiments detect a power supply status in one supply voltage domain (e.g., 1.2 volts, ground) and then assert low voltage disable or reset signals to downstream circuitry within a different supply voltage domain that is powered with different supply voltages (e.g., 1.8 volts, 0.9 volts, ground). In certain embodiments, the dual-voltage detectors provide two disable signals to stacked output drivers that are used to tri-state the stacked output drivers to place them in a high-impedance (HIGH-Z) state, for example, during power-up or power-down operations.

Abstract: A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.

Abstract: The power consumption of a semiconductor device that can function as a latch circuit or the like is reduced. The semiconductor device includes a first circuit and a switch that controls conduction between an input terminal and the first circuit. The first circuit includes n second circuits (n is an integer of 2 or more) and a variable resistor. An output node of any of the n second circuits is electrically connected to an input node of the second circuit in a first stage through the variable resistor. The variable resistor can be, for example, a transistor whose channel is formed in an oxide semiconductor layer. A reduction in the number of elements or signals leads to a reduction of the power consumption of the semiconductor device.

Abstract: An enable circuit receives an input enable signal that is referenced to a first voltage and generates a level-shifted output enable signal referenced to a second voltage. Bias control circuitry prevents shoot-through currents during ramping of the first voltage and from causing indeterminate logic levels of the level-shifted output enable signal. An enabled level-shifting circuit receives an input logic signal that is referenced to the first voltage and generates a level-shifted output logic signal referenced to the second voltage. Enable circuitry operates in response to the level-shifted output enable signal to enable normal level-shifting operation while the first and second voltages are at normal operating levels and prevents shoot-through currents in the enabled level-shifting circuit from causing indeterminate levels of the level-shifted output logic signal.

Abstract: Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals.

Abstract: The level shifter circuit includes: a first transistor including a gate connected to an input terminal of the level shifter circuit and a source connected to a first power supply terminal; a first resistor including one terminal connected to the input terminal of the level shifter circuit; a second transistor including a gate connected to another terminal of the first resistor, a drain connected to a drain of the first transistor, and a source connected to a terminal for inputting the voltage subjected to the level conversion; and a third transistor including a gate and a drain connected to the another terminal of the first resistor, and a source connected to the terminal for inputting the voltage subjected to the level conversion. Further, the battery device includes the charge/discharge control circuit.

Abstract: A voltage level conversion circuit includes a voltage switch circuit and a level shift circuit. The voltage switch circuit is configured to sequentially output an intermediate voltage and a conversion voltage in response to a switch signal. The level shift circuit is configured to latch a voltage level corresponding to an input signal using the intermediate voltage, and to convert the latched voltage level using the conversion voltage to generate an output signal.

Abstract: An output circuit, between a first power supply terminal and a second power supply terminal, receives a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal and provides a second logic signal, complementary to the first logic signal. A level translator is in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential. The level translator is designed so that it may be implemented using a subset of the transistors that have the shortest channel length and narrowest channel width.

Abstract: A level conversion circuit (10) includes an EFET (11), a diode (12) and resistors (13, 14). The drain of the EFET (11) is connected to an output terminal of the level conversion circuit (10). The drain and the gate of the EFET (11) are in conductive contact with each other. The source of the EFET (11) is grounded via the resistor (13). The drain of the EFET (11) is connected to one end of the resistor (14). The other end of the resistor (14) is connected to the cathode of the diode (12). The anode of the diode (12) is connected to a control voltage input terminal.

Abstract: A decoupling circuit comprises an output buffer that includes a transistor, and a capacitor that has an end thereof connected to an output node of the output buffer and the other end thereof connected to a power supply line, and a logic level outputted by the output node of the output buffer is fixed.

Abstract: A circuit includes a plurality of buffers configured to provide data on a corresponding signal line. Each of the plurality of buffers may be coupled to a power supply voltage through a corresponding diode. A plurality of receiving circuits may be coupled to receive the data provided on a corresponding one of the plurality of signal lines. The plurality of receiving circuits may be directly powered by the power supply voltage.

Abstract: There is provided a multi power supply type level shifter. The provided multi power supply type level shifter includes a first level shifter and a second level shifter in a two-stage architecture so as to selectively receive first to third power supplies and change a signal level, even when the first to third power supplies are applied in a different sequence from a normal power-on sequence. Output voltages are output without a change in level, and short-circuit currents are not generated in the first and second level shifters.

Abstract: A method and circuit for implementing a level shifter with built-in-logic function for reduced delay. The circuit including at least one set of inputs from a first power supply domain. The circuit further including at least two cross coupled field effect transistors (FETs) connected to a second power supply domain. The circuit further including a true logic gate connected to the first power supply domain and the at least two cross coupled FETs. The true logic gate being configured to generate a logic function based on the at least one set of inputs. The circuit further including a complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs. The complementary logic gate being configured to generate a complement of the logic function based on the at least one set of inputs.

Abstract: An integrated level shifting combinatorial circuit receives a plurality of input signals in a first voltage domain and performs a combinatorial operation to generate an output signal in a second voltage domain. The circuit includes combinatorial circuitry includes first and second combinatorial circuit portions operating in respective first and second voltage domains. The second combinatorial circuit portion has an output node whose voltage level identifies a value of the output signal and includes feedback circuitry which applies a level shifting function to an intermediate signal generated by the first combinatorial circuit portion.

Abstract: Disclosed is a voltage level converter that includes: a first conversion unit which receives at least one input signal of a logic 1 signal and a logic 0 signal from a signal input terminal and converts the signal; a second conversion unit and a third conversion unit which alternately output a logic ?1 signal and the logic 1 signal respectively in accordance with the input signal; a fourth conversion unit and a fifth conversion unit which alternately output the logic ?1 signal and the logic 0 signal respectively in accordance with the input signal; and a latch which has a complementary characteristic in which if a first transistor becomes an on-state, then a second transistor becomes an off-state in accordance with the input signal, and performs a positive feedback operation. A drain output of the first transistor is input to the fourth conversion unit. A drain output of the second transistor is input to the fifth conversion unit.

Abstract: Circuitry comprises a high voltage rail providing a high voltage level corresponding to a higher voltage domain, an intermediate voltage source, a low voltage rail, and devices that operate in a lower voltage domain. First devices in an upper voltage region are powered between the high voltage rail and an intermediate voltage rail powered by the intermediate source. Second devices in a lower voltage region are powered between the intermediate and low rails. On power up, the intermediate source is powered before the high voltage rail. An isolating circuit connects the intermediate source to a node when the high voltage rail is powered and isolates the node from the intermediate source when the high voltage rail is not powered to impede current flow from the intermediate source to the high voltage rail.

Abstract: A high speed level shifter interfaces a high speed DAC to the digital information that the DAC processes. The level shifter may convert CMOS level digital representations to, for example, CML level digital representations for processing by the DAC. The level shifter conserves the voltage swing in the CMOS level representations (e.g., about 1V). The level shifter also avoids voltage overstress, using a feedback loop to constrain the voltage amplitude, and thereby facilitates the use of fast thin film transistors in its architecture.

Abstract: Differential receivers are “stacked” and independently calibrated to different common-mode voltages. The different common-mode voltages may correspond to the common-mode voltages of stacked transmission circuits. Multiple stacks of samplers are connected to the same channels. The clocking of each stack of sampler circuits is phased (timed) such that the samplers in a given stack are not resolving at the same time. Samplers in a different stack and receiving a different common-mode voltage resolve at the same time.

Abstract: A dynamic voltage scaling system having time borrowing and local boosting capability, including: a time borrowing circuit and a local boost circuit. The time borrowing circuit connected electrically between a primary stage logic circuit and a secondary stage logic circuit is activated by an all-domain clock signal, and then generates an output data to the secondary stage logic circuit based on input data to the primary stage logic circuit. The local boost circuit is connected to a low working voltage line, when input data of the time borrowing circuit lags behind a positive level of said all-domain clock signal, the time borrowing circuit delays fetching data by a flip flop and changes state to produce a warning signal, so that the local boost circuit disconnects its connection with said low working voltage line, and is connected electrically to a high working voltage line.