Abstract: Transconductor circuits with programmable tradeoff between bandwidth and flicker noise are disclosed. An example circuit includes an input port, an output port, a plurality of transistors, and a switch arrangement that includes a plurality of switches, configured to change coupling between the input port, the output port, and the transistors to place the transconductor circuit in a first or a second mode of operation. An input capacitance of the transconductor circuit operating in the first mode is larger than when the transconductor circuit is operating in the second mode. In the first mode, having a larger input capacitance results in a decreased flicker noise because the amount of flicker noise is inversely proportional to the input capacitance. In the second mode, having a smaller input capacitance leads to an increased flicker noise but that is acceptable for wide-bandwidth applications because wide-bandwidth signals may be less sensitive to flicker noise.

Abstract: A reactor including: an assembly that includes a coil and a magnetic core; a case in which the assembly is accommodated; a sealing resin with which the case is filled; and a pushing plate accommodated in the case, wherein the case includes a bottom, a side wall, and at least one groove that is open in an inner surface of the side wall, and the groove of the case includes an opening end provided in an end surface of the side wall of the case that is located opposite to the bottom of the case, and a closed end provided on the bottom of the case with respect to the opening end.

Abstract: An arrangement, an apparatus, a quantum computing system, and a method are disclosed for reducing qubit leakage errors. In an example, an apparatus includes a qubit having a ground state and a plurality of excited states. The plurality of excited states include a lowest excited state. An energy difference between the ground state and the lowest excited state corresponds to a first frequency, and an energy difference between the lowest excited state and another excited state in the plurality of excited states corresponds to a second frequency. The apparatus also includes an energy dissipation structure to dissipate transferred energy, and a filter having a stopband and a passband. The filter is coupled to the qubit and to the energy dissipation structure. The stopband includes the first frequency and the passband includes the second frequency for reducing qubit leakage errors.

Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.

Abstract: An offset compensation device includes a first bias module and a second bias module. The first bias module includes a plurality of first current control circuits and a plurality of second current control circuits coupled in parallel. Each of the first current control circuits generates a first reference current, and each of the second current control circuits generates a second reference current. The second bias module includes a plurality of third current control circuits and a plurality of fourth current control circuits coupled in parallel. Each of the third current control circuits generates a third reference current, and each of the fourth current control circuits generates a fourth reference current. The second reference current is greater than the first reference current, and the fourth reference current is greater than the third reference current.

Abstract: An electric power converter is configured to perform conversion of power supplied from a power source. The electric power converter includes: a plurality of first capacitors connected in series between two lines to be used for supply of the power; and at least one second capacitor connected between a ground and a connection point between two first capacitors among the plurality of first capacitors.

Abstract: A signal mixing circuit device includes a first mixer, a second mixer and a signal amplifying circuit serially connected to the first mixer; the first mixer includes an RF signal input terminal for receiving an RF signal, LO signal input terminals for sampling a first and second LO signals, a first mixed-signal output terminal for outputting a first mixed signal and a second mixed-signal output terminal for outputting a second mixed signal; the second mixer includes an input terminal connected to a capacitor, two mixed-signal output terminals respectively connected to the first and second mixed-signal output terminals of the first mixer, LO signal input terminals for inversely sampling the first and second LO signals. With the double-balance nature of the second mixer core, the noise at the LO signal input terminals of the first mixer can be cancelled. A receiver includes the signal mixing circuit device is also disclosed.

Abstract: Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc.

Abstract: A method for sliding response acceleration and related products are provided. The method includes the following. A sliding operation of a user on a touch screen is monitored. A first sliding distance of the sliding operation is determined. When the first sliding distance exceeds a first preset distance, launching a sliding acceleration strategy includes: determining a difference between the first sliding distance and the first preset distance, and selecting a target sliding acceleration strategy corresponding to the difference, where the target sliding acceleration strategy includes improving performance of a central processing unit (CPU) and a larger difference corresponds to a higher improved performance of the CPU.

Abstract: A method for sliding response acceleration and related products are provided. The method includes the following operations. A sliding operation of a user on a touch screen is monitored. A first sliding distance of the sliding operation is determined. A sliding acceleration strategy is launched when the first sliding distance exceeds a first preset distance, where the sliding acceleration strategy includes improving performance of a central processing unit (CPU).

Abstract: A double-balanced radio-frequency (RF) mixing digital-to-analog converter (DAC) apparatus includes a load network, a first set of resistive DAC driver circuits and a first mixing core. The first mixing core can receive first RF input signals from the first set of resistive DAC driver circuits and can provide a first mixed signal to the load network. The first mixing core includes a first input differential pair coupled to two first cross-coupled differential pairs. The first input differential pair can receive first RF input signals at respective first input nodes. Each of the two first cross-coupled differential pairs can receive first positive and negative local oscillator (LO) signals at corresponding first input nodes. The first mixing core can mix the first RF input signals with the first positive and negative LO signals.

Abstract: A battery charger controller is configured to add a compensation current in the feedback control loop such that the output voltage varies with the output current to compensate charging cable voltage drop. In some embodiments, the output voltage is also proportional to a compensation resistor. Therefore, cable voltage drop compensation can be adjusted using a resistor that is external to the controller IC. The external resistor may be one of the feedback resistors connected at a voltage feedback pin. In another embodiment, the adjustable resistor is the resistor between the feedback resistors and the voltage feedback pin. In still another embodiment, the adjustable resistor is the resistor in parallel with a compensation capacitor. In embodiments of the invention, adjusting the resistance of the external compensation resistor can change the voltage drop compensation and allow the power supply to meet requirements of different charging cable applications.

Abstract: Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.

Abstract: A desk top alarm or time related or LED lighting device with backup battery for power fail time keep time functions always work, and device has USB-port(s) has built-in or external AC-to-DC circuit to get 1st voltage DC, and 1st DC go through at least one of DC-to-DC (including just conductive-piece) to 2nd or more voltage DC(s). At least one of 1st or 2nd or more voltage DC to supply to at least one of (i) USB-charging port(s), (ii) “8’ light source(s), or optional (iii) IC, (iv) speaker, (v) audio device, (vi) radio, (vii) outlet(s), (viii) surge or other safety protection circuit, (ix) colorful LEDs or LED-bulb for accent light, wake-up light, sleep night light, (x) colorful LEDs for charging status or power on/off or am/pm or, other indicator purpose, (xi). Same AC-to-DC circuit and DC-to-DC circuit also apply to desk top LED light which has built-in plurality of LED(s) inside the LED(s) compartment or replaceable/detachable CFL or LED bulbs for desk top LED lighting device.

Abstract: Disclosed is an N-bit counter including: an N-bit counting circuit starting counting from an initial value to generate a count value composed of N bits, and being loaded with the initial value to restart counting from the initial value when a reload signal changes from a first reload level to a second reload level; a reload signal generating circuit having the reload signal change from the first reload level to the second reload level when the logical conjunction of K bit(s) among the N bits changes from a first value to a second value; and a reset circuit having a reset signal change from a first reset level to a second reset level so as to have the reload signal change from the second reload level to the first reload level and thereby allow the N-bit counting circuit to restart counting.

Abstract: A switching power converter. Example methods include: switching a primary switch of the converter at a switching frequency, the converter having a feedback circuit acting as a low pass filter with a cutoff frequency, and each cycle of the switching frequency including a discharge mode and a charge mode that ends at a peak current through a primary winding of a transformer; generating, during the switching, a jitter signal having a shape and a jitter frequency; and ending a plurality of consecutive charge modes at a plurality of respective peak current values of current through the primary winding, the plurality of peak current values define an average value, and where peak current values higher than the average value define an envelope in the shape of the jitter signal, and peak current values lower than the average value define an envelope in the shape of the jitter signal that is inverted.

Abstract: Aspects of this disclosure relate to a segmented receiver for a wireless communication system. The segmented receiver includes a first receiver segment and a second receiver segment configured to receive respective radio frequency signals. The radio frequency signals can be orthogonally polarized. Branch circuits in each receiver segment can provide a radio frequency signal to different mixers. The different mixers can be included in different receiver segments and receive local oscillator signals from independent local oscillators. Each receiver segment can process a different bandwidth of the radio frequency signal. Two different bandwidths of the radio frequency signal can be processed concurrently by different receiver segments.

Abstract: Circuit for wireless communication are provided, the circuits comprising: a first quadrature hybrid having a first in port, a first iso port, a first cpl port, and a first thru port; a first mixer having a first input coupled to the first cpl port and having an output; a second mixer have a first input coupled to the first cpl port and having an output; a third mixer having a first input coupled to the first thru port and having an output; a fourth mixer having a first input coupled to the first thru port and having an output; and a first complex combiner having inputs coupled to the output of the first mixer, the output of the second mixer, the output of the third mixer, and the output of the fourth mixer that provides first I and Q outputs based the output of the first mixer and the output of the second mixer.

Abstract: A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.

Abstract: A spur cancellation circuit uses low cost multipliers in a correlation circuit. Each low cost multiplier multiplies a value of a sense node by a representation of a sinusoid and supplies a multiplication result. A compare circuit compares the sinusoid to one or more threshold values and supplies a compare indication. A multiplexer selects between two or more inputs including a positive value of the sense node and a negative value of the sense node, based on the compare result. A single threshold at zero converts the sinusoid to a square wave and the multiplexer supplies either the positive value or the negative value, which is equivalent to multiplying the value at the sense node by 1 or ?1 depending on the sign of the sinusoid. Two thresholds may be used to represent the sinusoid with three values, the positive value, the negative value, or zero.

Abstract: In a timing signal generator having a resonator, one or more temperature-sense circuits generate an analog temperature signal and a digital temperature signal indicative of temperature of the resonator. First and second temperature compensation signal generators to generate, respectively, an analog temperature compensation signal according to the analog temperature signal and a digital temperature compensation signal according to the digital temperature signal. Clock generating circuitry drives the resonator into mechanically resonant motion and generates a temperature-compensated output timing signal based on the mechanically resonant motion, the analog temperature compensation signal and the digital temperature compensation signal.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine temperatures of respective components, of an information handling system, housed in a duct of the information handling system and vertically positioned within the duct; may determine that a first temperature of the temperatures associated with a respective first component of the components meets a temperature threshold; may determine that a second component of the components is vertically positioned above the first component; may determine, based at least on a second temperature of the temperatures, associated with the second component, that the second temperature can be increased; and may provide, to the second component, information that causes the second temperature of the second component to increase, causing air to flow from a first end of the duct to a second end of the duct.

Abstract: Systems and methods for providing phase shifting in antenna arrays, such as phased antenna arrays of 5G cellular technology, are disclosed. In one aspect, an example phase shift module may include a phase shifter and a frequency multiplier. The phase shifter is configured to receive an LOcal oscillator (LO) signal and output a signal that is phase-shifted by a desired phase shift with respect to the LO signal. The frequency multiplier may be an enhanced frequency multiplier, configured to use not only the phase-shifted signal but also an inverted version of the phase-shifted signal to generate a frequency-multiplied signal having a frequency that is a multiple of the LO signal frequency. In another aspect, an example phase shift module may be configured to apply to an LO signal a phase shift that takes into consideration variations of phase shift over temperature.

Abstract: A semiconductor apparatus includes an internal clock generation circuit, a receiver, and a sampling circuit. The internal clock generation circuit generates a receiving clock signal and a sampling clock signal based on a reference clock signal, the sampling clock signal having a phase different from the receiving clock signal. The receiver receives an input signal in synchronization with the receiving clock signal and to generate an amplified signal. The sampling circuit samples the amplified signal in synchronization with the sampling clock signal to generate an output signal.

Abstract: The invention relates to a random clock generator comprising an input receiving a master clock signal MCIk, and a clock signal reduction circuit (101) receiving the master clock signal MCIk and a whole number N and supplying an output signal corresponding to a train of N pulses every M clock pulse, M being a whole number higher than 1 and N being a whole number higher than 1 and lower than or equal to M. A number generator (102) and (103) supplies a new number (N) to the clock signal reduction circuit every P pulse of a master clock signal, N and/or P being produced randomly.

Abstract: The subject technology provides for removing a source of delay in a phase-locked loop (PLL) by causing the output rising edge to occur at the same time as the input rising edge. The subject technology replicates the amount of delay experienced along an input reference signal path to the PLL as close as possible using a same circuit configuration and bias circuits as in the input reference signal path. For example, a timing alignment circuit containing a replica circuit adds compensation delay to a negative feedback loop signal to match the feedback loop delay with the reference path delay. The delay of the reference signal path is estimated and added into the replica circuit. The delay characteristics of these two paths negate one another such that the phases of the input reference signal and the feedback loop signal become phase-locked at the input to the PLL.

Abstract: Methods, apparatus, and articles of manufacture to perform fractional-pixel interpolation filtering for media coding are disclosed. A disclosed example method involves applying a finite impulse response (FIR) filter to samples of a source signal to generate an array of values. After applying the FIR filter, an infinite impulse response (IIR) filter is applied to the array of the values to generate fractional-pixel interpolated values. The fractional-pixel interpolated values may be stored in an encoded video data structure or may be output to a display interface.

Abstract: A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.

Abstract: A method involves using one or more software programs to stress a powered electronic device in a test environment to induce controlled electromagnetic emissions from the powered electronic device, using the controlled electromagnetic emissions to generate an emission profile of the powered electronic device operating under stress, monitoring spurious electromagnetic emissions of the powered electronic device in an operational environment, and comparing the spurious electromagnetic emissions of the powered electronic device in the operational environment with the emission profile of the powered electronic device to determine that the powered electronic device is operating under stress in the operational environment.

Abstract: A high definition timing synchronization function is described. In an embodiment, a wireless station generates a time stamp at a higher resolution than can be broadcast within a standard time stamp field in a frame. The generated time stamp is divided into two parts: the first part being included within the time stamp field and the second part being included within a vendor specific field in the same frame. The frame is transmitted by the wireless station and received by other wireless stations in the wireless network. If the receiving wireless station has the capability, it decodes both the time stamp field and the vendor specific field and recreates the higher resolution time stamp. This higher resolution time stamp is then used to synchronize the receiving wireless station and the transmitting wireless station by resetting a clock or by storing time stamps and corresponding clock values.

Abstract: The transmitter includes a phase shifter that shifts a phase of an input signal and outputs a shifted signal; a first control circuit changes a phase shift amount of the phase shifter; a phase difference signal output circuit outputs a phase difference signal between the shifted signal and the reference signal; an extreme value output circuit outputs a value of the phase difference signal when the phase difference signal becomes the extreme value; a target value output circuit outputs a target value based on an output from the extreme value output circuit; and a second control circuit controls the phase shift amount of the phase shifter such that a value of the phase difference signal coincides with the target value. The phase shifter outputs, as a transmission wave, the input signal the phase of which is shifted by the phase shift amount controlled by the second control circuit.

Abstract: Tunable filters, cancellers, and duplexers based on passive mixers. A tunable delay cell includes passive mixers electrically coupled together for receiving an input signal and outputting a delayed signal, each passive mixer comprising a plurality of mixer switches. The tunable delay includes a control circuit for providing, to each passive mixer, a respective plurality of local oscillator (LO) signals, one to each mixer switch of each passive mixer. The control circuit is configured to vary the LO signals to cause a target frequency band of the input signal to be delayed by a target delay time in propagating through the passive mixers.

Abstract: A comb signal generator is provided. The comb signal generator includes a signal generator, which is adapted to successively generate a plurality of continuous wave signals. The comb signal generator is adapted to successively generate a comb signal from each continuous wave signal of the plurality of continuous wave signals, wherein each of the comb signals has a comb signal bandwidth. The comb signal generator is further adapted to successively generate the comb signals so as to cover a comb signal bandwidth range.

Abstract: A radio frequency amplifier comprises a transistor, a transformer and a variable capacitor. The transistor has an input terminal, an output terminal and a control terminal. The transformer has a first coil conductor and a second coil conductor. The first coil conductor magnetically couples to the second coil conductor. The second coil conductor connects to the control terminal. The first coil conductor connects to the input terminal. The variable capacitor connects in parallel with the second coil conductor. The radio frequency amplifier is configured to be an input or output stage of an integrated circuit. An integrated circuit using the radio frequency amplifier is also introduced.

Abstract: A down converter, including first and second biasing circuits, mixer, and transformer coupled to receive amplifier output signal. The first and second biasing circuits each include a biasing transistor and a first and second node, respectively. Mixer includes first and second transistors coupled to first node and third and fourth transistors coupled to second node. The second and fourth transistors are coupled to a third node. The first and third transistors are coupled to a fourth node. Mixer also includes a first resistor coupled to the fourth node and a supply voltage node and a second resistor coupled to the third node and a supply voltage node. Transformer includes a primary winding coupled to receive the amplifier output signal and to a supply voltage and a secondary winding coupled to mixer and first biasing circuit at first node and coupled to mixer and second biasing circuit at second node.

Abstract: An electrocardiogram high pass filter (25) employs a baseline low pass filter (40), a signal delay (44) and a signal extractor (45). In operation, baseline low pass filter (40) includes a finite impulse response filter (41) and an infinite impulse response low pass filter (42) cooperatively low pass filtering a baseline unfiltered electrocardiogram signal (ECGbu) to output a filtered baseline signal (BSEf). Baseline low pass filter (40) further includes a baseline wander estimator (43) dynamically adjusting a corner frequency of baseline low pass filter (40) as a function of an estimation of any baseline wander within the baseline unfiltered electrocardiogram signal (ECGbu).

Abstract: Methods, systems, and devices for wireless communication are described for enhanced broadband operation of an active mixer. In an example, an apparatus may include an active mixer that converts between radio frequency (RF) signals and intermediate frequency (IF) signals based at least in part on an alternating current (AC) local oscillator (LO) signal, wherein a direct current (DC) current generated within the active mixer is dependent in part on a bias voltage and the AC LO signal. The apparatus may include a mixer biasing circuit that generates the bias voltage for the active mixer, a magnitude of the bias voltage having an inverse relationship to an amplitude of the AC LO signal.

Abstract: An integrated electronic circuit is provided. The integrated electronic circuit includes a transconductance cell formed from transconductance cell devices. The integrated electronic circuit further includes active and passive decoupling circuits. The integrated electronic circuit also includes an oscillator having a tank that is direct current decoupled from the transconductance cell devices using the active and passive decoupling circuits to increase voltage swing and decrease phase noise of the oscillator.

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event in based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

Abstract: A front end circuit includes a bypass circuit comprising a first bypass switch and a second bypass switch configured to bypass a signal to a first terminal according to switching operations of the first bypass switch and the second bypass switch; and an amplifier connected in parallel to the bypass circuit and configured to amplify the signal.

Abstract: An alarm system includes a detector positioned to detect when an object experiences an unauthorized removal and which produces an alarm signal when the object experiences an unauthorized removal. The alarm system includes a global positioning system (GPS) and a transmitter in communication with the detector which transmits wirelessly an alarm alert signal with coordinates of the transmitter's location when the transmitter receives the alarm signal. The alarm system includes a power supply control portion in communication with the transmitter which controls power to the transmitter. A method for protecting an object.

Abstract: A method and apparatus for automated detection of a general, non-sinusoidal type of periodicity in ultrasound Doppler signals from pulsatile blood flow is described. The method computes a measure of pulsatility from the power spectrum near the peaks of the fundamental and harmonic frequencies of the Doppler signal information.

Abstract: A pulse generator is disclosed. The pulse generator can include a pulsed switch, such as a diode. The pulsed switched can be connected between an input source, such as an oscillator and a frequency multiplier.

Abstract: A switched mode negative inductance circuit includes an input node responsive to a voltage signal. The circuit also includes first and second voltage sources, first and second controlled switches having first poles coupled to the first and second voltage sources, respectively and an inductor having a first electrode coupled to second poles of the first and second controlled switches and a second electrode coupled to the input node. The input node is coupled to a control electrode of the first controlled switch, and to a control electrode of the second controlled switch through a voltage inverting circuit. The disclosure also illustrates balanced negative inductance circuits and implementation approaches using NMOS transistors.

Abstract: Techniques are generally described related to management of power consumption for a processor. One example method may include identifying a target operating constraint and a first operating parameter; determining a second operating parameter based on the target operating constraint and the first operating parameter; estimating an actual operating constraint; comparing the target operating constraint and the actual operating constraint; and setting up the first operating parameter and the second operating parameter of the processor based on a comparison of the target operating constraint and the actual operating constraint, wherein the target operating constraint is not a worst-case operating constraint. Other examples of methods, systems, and computer programs related to managing power consumption for a processor are also contemplated.

Abstract: Systems, methods, and articles of manufacture, including computer program products, are provided for capacitive passive mixer baseband receivers with broadband harmonic rejection. In some embodiments, an apparatus is provided. The apparatus includes a receiver configured to receive an input signal and generate, based on the input signal, an in-phase portion and a quadrature phase portion. The apparatus further includes a harmonic rejection mixer comprising a plurality of capacitors, the plurality of capacitors encoded with a plurality of capacitance values, the harmonic rejection mixer configured to reduce harmonics in the input signal based on applying a quantity of the plurality of capacitance values to the input signal. The apparatus further includes a plurality of switches configured to activate the plurality of capacitors, the quantity of the plurality of predetermined capacitance values applied to the input signal based on a quantity of the plurality of capacitors that are active.

Abstract: A peak frequency detection device provided with: an n multiplication unit that multiplies each element of a digital data string by n (n is an integer of 2 or more); an FFT unit that derives, as a virtual peak frequency, a frequency that corresponds to the maximum value of a power spectrum that is obtained by performing a fast Fourier transform of a digital data string of N (N is an integer of a power of 2 and is determined in accordance with a sampling frequency (fs), a sampling resolution (ftg), and a time window length (Ttg)) sample frequencies (fs) that are multiplied by n; and a 1/n multiplication unit that outputs the value of the virtual peak frequency multiplied by 1/n as the peak frequency of the digital data string. The peak frequency detection device satisfies n?1/(ftg×Ttg), fs/(n×ftg)?N?fs×Ttg, and fs>2×n×fch.

Abstract: A data communication system for unmanned aerial vehicles includes communication links comprising a low-throughput capacity communication link and a high-throughput capacity communication link. The data communication system can also include a base station, to which the unmanned aerial vehicles send aerial data, and from which the unmanned aerial vehicles receive command signals. As the unmanned aerial vehicles perform missions in an open, distant airspace, the unmanned aerial vehicles can gather large volume data such as aerial images or videos. The data communication system allows opportunistic transfer of the gathered aerial data from the unmanned aerial vehicles to the base station when a high-throughput communication link is established. The data communication system allows constant communication between the base station and the unmanned aerial vehicles to send and receive low volume, operation-critical data, such as commands or on-going flight path changes, using a low-throughput communication link.

Abstract: An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesizer, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.

Abstract: The present disclosure describes current steering phase control for current-mode logic (CML) circuits. In some aspects, a circuit for frequency division comprises a current sink connected to a ground rail. The circuit also includes first and second current-carrying branches of frequency-dividing circuitry operably connected to respective load resistors, which are connected to a power rail. A first switch element of the circuit is connected between the current sink and the first current-carrying branch and a second switch element of the circuit is connected between the current sink and the second current-carrying branch. The first and second switch elements may steer current sank by the current sink between the first and second current-carrying branches effective to alter a phase of a signal provided by the frequency division circuit.