Abstract: In order to output an accurate waveform in which quantization noise has been cancelled out, provided is a signal generating apparatus that outputs an output signal corresponding to a waveform data sequence expressing a waveform, the signal generating apparatus comprising a DA converting section that outputs an analog signal by sequentially performing digital/analog conversion on each piece of data included in the waveform data sequence, at a timing of a sampling clock; and a jitter injecting section that injects jitter decreasing a quantization noise component of the output signal, into the sampling clock supplied to the DA converting section.

Abstract: There are provided a frequency generation apparatus and a frequency generation method. The frequency generation apparatus includes a current generation unit varying an amount of current with respect to a temperature change; a capacitor in which charges are charged by the current generation unit; a discharge circuit unit comparing a charging voltage of the capacitor with a previously set first reference voltage and discharging the capacitor; and an output signal generation unit comparing the charging voltage of the capacitor with a previously set second reference voltage and generating an output signal, wherein the current generation unit varies the amount of current so as to maintain a constant frequency.

Abstract: A semiconductor device includes: a frequency setting information storage unit that stores sets of frequency information indicating setting of a frequency supplied by an oscillation unit and frequency identification information identifying the frequency information and outputs one of a plurality of pieces of the frequency information to the oscillation unit based on frequency identification information inputted thereinto; a speed setting information storage unit that stores speed identification information indicating a speed of the semiconductor device and frequency identification information corresponding to the speed identification information; a frequency identification information count unit that holds a value of the frequency identification information inputted into the frequency setting information storage unit; and a control unit that causes the frequency identification information count unit to increment or decrement the held value of the frequency identification information to approach a value of the

Abstract: A local oscillation generator includes an oscillation circuit, a frequency multiplication circuit, a mixer, and a frequency divider. The oscillation circuit provides a fundamental oscillation signal. The frequency multiplication circuit provides a first oscillation signal according to the fundamental oscillation signal. The mixer provides a mixed oscillation signal according to mixing of the fundamental oscillation signal and the first oscillation signal. The frequency divider frequency divides the mixed oscillation signal so that the local oscillation generator accordingly provides a local oscillation signal.

Abstract: Fractional frequency division is performed by sequentially selecting phase signals for division, where transitioning from a previous phase signal to a next phase signal for division occurs in response to not only the frequency-divided previous phase signal but also a second one of the phase signals. A phase transition that is triggered at least in part in response to a second phase signal having a phase that is greater (with respect to the phase signal sequence) than the phase of the next phase signal can aid minimization of signal glitches. The first frequency-divided signal can be further divided to produce a second frequency-divided signal having a 50-percent duty cycle.

Abstract: An operation clock generation circuit performs a calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.

Abstract: A signal processor includes: a plurality of frequency converters which perform frequency conversion of input signals to output converted signals; and an output section which combines the converted signals output from the plurality of frequency converters and outputs a composite signal, wherein the plurality of frequency converters are formed in a one-chip semiconductor chip, and the plurality of frequency converters perform frequency conversion into converted signals in different frequency bands.

Abstract: A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock.

Abstract: The present invention relates to a clock signal generating circuit and a power supply including the same. The present invention includes: a counter for counting one period of an input clock signal by using a reference clock signal, and generating a count signal; and a clock signal generator for receiving the count signal and the reference clock signal, dividing the count signal to generate a quotient and a remainder, setting the quotient as a reference period of an output clock signal, and distributing and disposing the remainder to the output clock signal with a plurality of periods occurring for one period of the input clock signal.

Abstract: An integrated circuit 2 comprises a functional circuit 4, 6 which is arranged to operate in response to an operational clock signal having an operational clock frequency. To conserve power, the clock signal is distributed across the integrated circuit 2 at a distribution clock frequency which is less than the operational clock frequency. A clock converter 10 is provided to convert the distribution clock signal into the operational clock signal for controlling operation of the functional circuit 4, 6.

Abstract: A method for controlling a temperature of an electronic device which includes a semiconductor chip is provided. The temperature control method includes measuring a temperature of a measurement point using the electronic device, comparing the temperature of the measurement point with a target temperature varying according to a period of time when the semiconductor chip operates using the electronic device, and decreasing a clock frequency of the semiconductor chip using the electronic device when the temperature of the measurement point is higher than the target temperature.

Abstract: A frequency regulation system includes a sensor to detect a power grid signal and a frequency deviation identification module to determine a power grid frequency deviation from the power grid signal. A demand response module identifies an operating schedule for available demand response resources based on frequency deviation set points and ramp rates and a load control module controls the available demand response resources based on the operating schedule.

Abstract: Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.

Abstract: An apparatus comprising a low noise mixer comprising a transconductance amplifier configured to receive a differential voltage and to generate a differential current signal, a passive mixer directly connected to an output of the transconductance amplifier, and a transimpedance amplifier coupled to the passive mixer, wherein the transimpedance amplifier is configured to receive a current signal and convert the current signal to a voltage signal.

Abstract: An apparatus for monitoring timing of a plurality of critical paths of a functional circuit includes a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events. Each canary circuit includes an adjustable delay element and an analyser circuit for receiving a count of the critical timing event output from at least one of the plurality of canary circuits for a predetermined time interval for a plurality of delay values of the adjustable delay elements and for determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values.

Abstract: Embodiments of the present invention disclose a method and an apparatus for controlling chip performance, and relate to the field of communications technologies, which solves a problem in the prior art that a chip is reset or performance is greatly decreased as long as a temperature of the chip is higher than a preset threshold. The method includes: obtaining a working temperature of a chip; when the working temperature of the chip reaches one of multiple preset temperature thresholds, obtaining, according to preset correspondence between a temperature threshold and a chip performance control policy, a chip performance control policy that corresponds to the one of the multiple temperature thresholds; and controlling working of the chip according to the control policy. The present invention is applicable to an electronic device to which a chip is applied, such as a desktop computer or a notebook computer.

Abstract: The present invention relates to a switch controller, a switch control method, and a power supply using the switch controller. A switch controller controls switching operation of a power switch and receives a sense voltage of a sense resistor to which a drain current flowing in the power switch flows. The switch controller generates a sum signal using the sense voltage and a ramp signal having a cycle that is the same as a switching cycle of the power switch. The switch controller determines short-circuit of the sense resistor by detecting slope variation of the sum signal.

Abstract: A center frequency F0 of an IF filter is effectively adjusted. The IF filter filters a down-converted signal centering around the center frequency F0. A pseudo sine wave generation circuit generates a pseudo sine wave having a level change of at least two steps respectively on both positive and negative sides. The pseudo sine wave is made to pass through the IF filter by a switch circuit, and in the state, an F0 adjustment circuit adjusts the center frequency F0 in the IF filter 14 by comparing a phase of the pseudo sine wave with a phase of a signal after passing through the IF filter.

Abstract: A transconductance-enhancing passive frequency mixer comprises a transconductance amplification stage, a frequency mixing stage, and an output transresistance amplifier. The transconductance amplification stage has a pre-amplification transconductance-enhancing structure, so that the transconductance is greatly enhanced, thereby obtaining the same transconductance value at a lower bias current. A radio-frequency current is modulated by the frequency mixing stage to generate an output mid-frequency current signal. The mid-frequency current signal passes through the transresistance amplifier, to form voltage output, and finally obtain a mid-frequency voltage signal. The transresistance amplifier has a transconductance-enhancing structure, thereby further reducing input impedance, and improving current utilization efficiency and port isolation. The frequency mixer has the characteristics of low power consumption, high conversion gain, good port isolation, and the like.

Abstract: Apparatus and methods are disclosed related to using one or more field effect transistors as a resistor. One such apparatus can include a field effect transistor (FET), averaging resistors and a bidirectional current source. The averaging resistors can apply an average of a voltage at the source of the FET and a voltage at the drain of the FET to the gate of the field effect transistor. The bidirectional current source can turn the FET on and off. The FET can operate in the ohmic region when on. Such an apparatus can improve the linearity of the FET as a resistor, for example, at lower frequencies near or at direct current (DC). In some implementations, the apparatus can include one or more current sources to remove an offset introduced by the bidirectional current source at the source and/or the drain of the FET.

Abstract: According to one embodiment, there is provided a DLL circuit including a delay chain, a plurality of phase comparators, and a controller. The plurality of phase comparators receive the reference clocks individually and receive respectively the clocks from the delay elements in mutually different stages, among the delay elements of the plurality of stages. The controller simultaneously receives comparison results of the plurality of phase comparators, determines the number of stages that generate the clock of which a phase is synchronized with a phase of the reference clock from among the delay elements of the plurality of stages, and selects the number of output stages from among the delay elements of the plurality of stages based on the determined number of stages so that a delay clock having a demanded delay amount with respect to the reference clock is output.

Abstract: A clock signal generation circuit includes a clock delay control signal generation unit configured to divide a clock signal to generate a divided clock signal, generate a plurality of periodic signals which have different periods with each other during a half period of the divided clock signal, and output clock delay control signals from the plurality of periodic signals, and a doubler clock generation unit configured to delay the clock signal in response to the clock delay control signals to generate a delayed clock signal, and generate an output clock signal by mixing phases of the clock signal and the delayed clock signal.

Abstract: An asynchronous sampling frequency conversion device includes: a storage unit configured to store input digital signals; a data specifying unit configured to specify first data and second data based on a ratio of a sampling frequency of the input digital signal to a sampling frequency of an output digital signal, the first data being sampled at a sampling timing immediately before an ith (where i is a natural number) sampling timing of the output digital signal among the input digital signals stored in the storage unit, the second data being sampled at the sampling timing immediately after the ith sampling timing of the output digital signal; and an output data value calculator configured to calculate a value of ith data of the output digital signal based on the first data and the second data specified by the data specifying unit and the ratio.

Abstract: A harmonic rejection mixer converts a frequency of a radio frequency signal by using a first to a third local signals (LOs) whose phases are different from each other, and the harmonic rejection mixer includes a phase difference detection circuit for detecting a phase difference between the first LO and the second LO, a phase difference detection circuit for detecting a phase difference between the first LO and the third LO, a phase adjustment circuit for adjusting the phase of the second LO so that the phase difference detected by the phase difference detection circuit becomes a first phase difference, and a phase adjustment circuit for adjusting the phase of the third LO so that the phase difference detected by the phase difference detection circuit becomes a second phase difference. It is thereby possible to achieve high precision harmonic rejection characteristics.

Abstract: A down-conversion module for a heterodyne receiver comprises a first mixer circuit, a second mixer circuit and an interconnection. The first mixer circuit includes first and second differential control terminals and is arranged to produce a first down-converted differential voltage signal at a first down-converted frequency as a function of a first RF differential input signal applied to the first differential control terminals and of a first RF differential reference frequency signal applied to the second differential control terminals.

Abstract: The provision of a technique capable of determining a state where PLL control does not operate normally instantly or in advance in a frequency synthesizer that frequency-divides, A/D converts, and quadranture-detects a frequency signal from a voltage controlled oscillating unit, and extracts a rotation vector rotating at a frequency difference between the frequency signal used for the detection and the A/D converted frequency signal, and integrates a difference between a frequency of the above rotation vector and a set frequency to set an integration result as a control voltage to the voltage controlled oscillating unit. The control voltage to be input to the voltage controlled oscillating unit is monitored, and it is determined whether or not a level of the monitored control voltage deviates from a set range determined in advance, and an unlock detection signal is output.

Abstract: A circuit and a method for removing a frequency offset and a communication apparatus including the circuit, capable of removing the frequency offset by tracking rapidly and accurately in a payload section. A sequence of sample levels is obtained by sampling a frequency level of the baseband signal at every 0.5 symbol interval. Absolute values of differences between the frequency levels adjacent to each other at every 1 symbol are calculated as first difference absolute values. Absolute values of differences between the frequency levels adjacent to each other at every 1 symbol are calculated as second difference absolute values. When the first difference absolute values are greater than a predetermined first determination value or the second difference absolute values are less than a predetermined second determination value, the average value calculated is set as the frequency offset.

Abstract: A frequency generator is used for generating a frequency within a frequency range. The frequency generator includes a variable current source, a voltage drop generation unit, a voltage source, a detection unit, a conversion unit, and an oscillating circuit. The variable current source is used for outputting a current according to a control signal. The voltage drop generation unit is used for generating a voltage drop according to the current. The voltage source is used for outputting a voltage range. The detection unit is used for outputting the control signal to the variable current source according to a relationship between the voltage drop and the voltage range. The conversion unit is used for outputting a digital code according to the relationship between the voltage drop and the voltage range. The oscillator circuit is used for generating the frequency according to the digital code.

Abstract: A switched capacitor type D/A converter receives m-bit (m represents an integer) input data, and outputs an analog signal that corresponds to the input data value. Switch circuits are provided to respective bits of the input data, and are classified into two groups: a first group configured to turn on when the corresponding input data bit is 1, and to turn off when the corresponding input data bit is 0; and a second group configured to turn on when the corresponding input data bit is 0, and to turn off when the corresponding input data bit is 1. Each switch of the first and second switch groups is configured as a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The ground voltage 0 V is applied to the lower power supply terminal of each of the first and second inverters configured to supply a gate signal to each switch.

Abstract: A radio frequency circuit includes a transformer, a local oscillator, a first mixer, a second mixer, a first variable gain amplifier, and a second variable gain amplifier. The first mixer includes a first inductor that is coupled between a positive in-phase input and a negative in-phase input. The second mixer includes a second inductor that is coupled between a positive quadrature input and a negative quadrature input. The first and second inductors provide inductive loads and improve conversion gains of the first and second mixers respectively.

Abstract: A multiphase clock generation circuit includes: a first frequency divider to generate a first intermediate clock and a second intermediate clock; a second frequency divider to generate output clocks of a first group including a first output clock and a second output clock; a third frequency divider to generate output clocks of a second group including a third output clock and a fourth output clock; a selector to supply one of the second intermediate clock and a value to the third frequency divider in response to a switching signal; an error detection circuit to detect an error in a phase relationship between the output clock of the first group and the output clock of the second group; and a re-reset circuit to output the switching signal to the selector based on the error.

Abstract: A signal generator for coupling to a concealed conductor including a first oscillator configured to generate a first waveform having a first frequency, a first terminal coupled to the first oscillator through a first band pass filter configured to pass signals of the first frequency, a second oscillator configured to generate a second waveform having a second frequency, and a second terminal coupled to the second oscillator through a second band pass filter configured to pass signals of the second frequency.

Abstract: The present invention is applied to a frequency converter used for a receiver. The frequency converter according to the present invention includes an LO signal generator (11) that generates an LO signal and outputs the LO signal; and a mixer (10) that multiplies a received signal that has been band-limited in a usable bandwidth of said receiver by the LO signal so as to convert the frequency of the received signal and outputs the resultant signal, wherein said LO signal generator is capable of varying a phase resolution, and said frequency converter is capable of varying a signal gain for each phase value of the LO signal.

Abstract: A microprocessor including a temperature sensor that monitors a temperature of core logic of the microprocessor during operation thereof, and operating point information from which may be determined N operating points at which the microprocessor core may reliably operate at a first temperature. Each of the N operating points has a different combination of operating frequency and voltage. The N operating points comprise a highest operating point, a lowest operating point, and a plurality of operating points intermediate the highest and lowest operating points. The microprocessor also includes a control circuit that transitions operation of the core logic among the N operating points to attempt to keep the operating temperature of the core logic provided by the temperature sensor within a temperature range whose upper bound is the first temperature.

Abstract: A system for generating a frequency reference signal comprising an oscillator, a direct digital synthesizer coupled to the oscillator and configured to receive a signal output from the oscillator, a digital to analog converter coupled to the direct digital synthesizer and configured to receive a sampled signal from the direct digital synthesizer and to convert the sampled signal to an analog waveform, and a bandpass filter coupled to the digital to analog converter and configured to select an aliased output signal from the digital to analog converter at a Nyquist zone other than a first Nyquist zone and to output the frequency reference signal.

Abstract: An injection-locked frequency divider is provided and which includes an injection transistor, an oscillator, a current source and a transformer. The injection transistor is used to receive an injection signal. The oscillator is used to divide the injection signal to generate a divided frequency signal. The current source is coupled to the oscillator to provide a current to the oscillator. The transformer is coupled between the injection transistor and the oscillator to increase the equivalent transconductance of the injection transistor, and thus increasing the locking range of the injection-locked frequency divider.

Abstract: In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.

Abstract: First windings of a first common mode transformer and second windings of a second common mode transformer are connected in series via connection lines. The windings are connected to an AC power supply via connection lines. The first windings are connected to a three-phase motor via connection lines, a converter, and an inverter. High-frequency leakage currents flowing in the connection lines are detected as a common mode voltage by a winding for common mode voltage detection. An output voltage is inputted via a filter to a voltage amplifier unit that amplifies the output voltage, and the amplified voltage is applied to a winding via a capacitor in substantially a same direction as a direction of the common mode voltage. As a result, leakage currents are reduced by induced voltages on the windings.

Abstract: Methods and apparatuses are provided for controlling the state of a qubit. A qubit apparatus includes a qubit and a load coupled to the qubit through a filter. The filter has at least a first pass band and a first stop band. A qubit control is configured to tune the qubit to alter an associated transition frequency of the qubit from a first frequency in the first stop band of the filter to a second frequency in the first pass band of the filter.

Abstract: A system for distributing radio frequency signals using a data cable system includes a method and components that receive a radio frequency (RF) signal, identify at least one unoccupied channel on the data cable system, convert the RF signal to the frequency associated with an unoccupied channel as a converted signal, insert the converted signal into the cable, extract the converted signal from the cable as an extracted signal, convert the extracted signal to a transmission frequency as a transmission signal, and transmit the transmission signal at the transmission frequency.

Abstract: A signal generation device includes: filter banks that perform sampling frequency conversion with respect to an input signal of a predetermined sampling frequency, and generate a signal obtained after the sampling frequency conversion as an output signal; a control-signal generation unit that selects the filter banks to be used based on a sampling-frequency setting value indicating a sampling frequency of the output signal: and a switching unit selects the filter banks based on a result of selection by the control-signal generation unit.

Abstract: In an embodiment, a front-end transceiver may be provided. The front-end transceiver may include a receiver path, including a first receiver frequency converter configured to convert a received signal with a receiver frequency into a first receiver intermediate signal with a first receiver intermediate frequency; and a receiver direct conversion stage coupled to the first receiver frequency converter so as to receive the first receiver intermediate signal.

Abstract: Apparatus and methods for distributing spurious tones through the frequency domain are disclosed. One such apparatus can include a dithering circuit configured to generate a sequence of numbers that exhibit statistical randomness and a variable frequency circuit configured to adjust a frequency of an output based on the sequence of numbers so as to spread energy of spurious tones in a frequency response of the output to lower a noise floor. In one example, spurious tones can be reduced in a negative voltage generator of a radio frequency (RF) attenuator.

Abstract: At very high frequencies, generally above 100 GHz, the performance of traditional radio frequency (RF) circuitry begins to significantly limit performance. An example is the hybrid coupler, which can have a relatively narrow 90° bandwidth in these frequency ranges. Here, however, a branch-line hybrid coupler (which has been integrated into a quadrature downconversion mixer) has been modified. Namely, an adjustable impedance network has been coupled to isolation port (which has traditionally been terminated) to substantially increase the tuning range and expand the bandwidth of the quadrature mixer within these very high frequency ranges.

Abstract: Very low phase noise radio frequency (RF) source having multiple discrete frequency outputs used, for example, to calibrate phase noise measurement systems. The calibrator output frequencies can be tailored for a particular application using a scalable architecture.

Abstract: The present invention realizes low power consumption at the time of an automatic frequency control circuit operation. An automatic frequency control circuit includes a mixing unit that generates a modulated signal from a reception signal according to a frequency of a local signal, a demodulation unit that demodulates the modulated signal supplied by the mixing unit, an error evaluation unit that generates a frequency error signal according to a duty of the demodulated signal supplied by the demodulation unit, a holding unit that holds a frequency setting of the local signal and updates the frequency setting according to the frequency error signal supplied by the error evaluation unit, and an oscillation unit that controls a frequency of the local signal according to the frequency setting supplied by the holding unit.

Abstract: A receiving method and apparatus is disclosed. The method comprising steps of: receiving a plurality of data according to a symbol clock signal, and reading out the plurality of data according to a first clock signal and generating a water level; receiving a second clock signal so as to generate a third clock signal, and adjusting the speed of the third clock signal according to the water level; determining a sampling frequency of the plurality of data according to a data amount of the plurality of data during a unit time period or parameters of the plurality of data; and dividing the third clock signal by a dividing value or multiplying the third clock signal by a multiplying value so as to obtain the first clock signal and adjust the water level by a clock generator.

Abstract: Dead-time detector includes an N-type power switch and a resistor. The N-type power switch includes a first end coupled to the output end of the output-stage circuit for receiving an output voltage, a second end for outputting a dead-time detecting signal, and a control end for receiving a gate-controlling voltage. The resistor is coupled between the second end of the N-type power switch and a voltage source providing a high voltage for keeping the voltage of the dead-time detecting signal when the N-type power switch does not output the dead-time detecting signal representing “ON”. When the output voltage is so lower than the gate-controlling voltage that the N-type power switch is turned on, the N-type power switch outputs the dead-time detecting signal representing “ON”. When the dead-time detecting signal represents “ON”, the output-stage circuit leaves the dead-time state.

Abstract: The present invention relates to an apparatus for frequency conversion, comprising: an analog-to-digital (A/D) converter, receiving and sampling an input signal according to a sampling frequency for producing a first digital signal, and the sampling frequency and the frequency of the input signal having a correspondence; a sign conversion circuit, used for receiving the first digital signal, and performing a sign conversion on the first digital signal and producing a second digital signal; a first switching module, used for selecting one of the first digital signal and the second digital signal as an output signal according to the sampling frequency; a filter, coupled to the first switching module, used for filtering the output signal from the first switching module, and producing a filter signal; and a second switching module, coupled to the filter, used for outputting the filter signal to a first output path or a second output path alternately according to the sampling frequency.

Abstract: A circuit includes first and second frequency divider circuits and first storage circuits. Each of the first and the second frequency divider circuits receives periodic input signals and generates a periodic output signal having a frequency of one of the periodic input signals in a bypass mode. The periodic output signal of each of the first and the second frequency divider circuits has a fraction of a frequency of one of the periodic input signals in a frequency divider mode. Each of the first storage circuits stores an enable signal in response to the periodic output signal of one of the first frequency divider circuits. The enable signals stored in the first storage circuits enable the second frequency divider circuits in the frequency divider mode. The circuit may include second storage circuits storing enable signals that enable a subset of the first frequency divider circuits in the frequency divider mode.