Abstract: The invention relates to a frequency adjusting apparatus and the method therefor comprising an adjusting module, a comparing module, a processing module and an operating module. The adjusting module generates a frequency signal according to a predetermined signal after receiving a trigger signal and generates N adjusting signal according to N processing signal. The comparing module compares the N adjusting signal with the predetermined signal according to a predetermined manner and generates N comparing result. The processing module generates N processing signal according to the N comparing result. The operating module executes a specific operation with M adjusting signal of the N adjusting signal matching the predetermined rule and generates a operation signal, wherein the frequency of the operation signal is approximately equal to which of the predetermined signal. Wherein N and M are natural numbers and N?M?1, the adjusting module adjusts the operation frequency according to the operation signal.

Abstract: In various embodiments, an apparatus for down-converting a first signal having a first frequency to a lower frequency is disclosed. The apparatus can include one or more arrays of N over-damped, bi-stable circuits unidirectionally-coupled from element to element.

Abstract: Methods and apparatus are provided for generating a frequency with a predefined offset from a reference frequency. A spread spectrum generator circuit is disclosed that comprises a voltage controlled delay loop for generating a plurality of signals having a different phase; and at least one interpolator for processing at least two of the signals to generate an output signal having a phase between a phase of the at least two of the signals, wherein the output is varied between a phase of the at least two of the signals to generate the spread spectrum. A spread spectrum having a frequency lower than an applied clock signal is generated using a continuous phase delay increase and a spread spectrum having a frequency higher than the clock signal is generated using a continuous phase delay decrease.

Abstract: According to one exemplary embodiment, a local oscillation generator includes a mixing stage for receiving a primary frequency and one of a number of related frequencies. The local oscillation generator further includes a first transconductance stage to provide a first related frequency to the mixing stage when a first switch selectably enables a first power path in the first transconductance stage. The local oscillation generator further includes a second transconductance stage to provide a second related frequency to the mixing stage when a second switch selectably enables a second power path in the second transconductance stage. The local oscillation generator further includes a number of dividers, where an output of a first divider provides the first related frequency to an input of the first transconductance stage, and where an output of a second divider provides the second related frequency to an input of the second transconductance stage.

Abstract: A system for single path processing identical, substantially identical, close or interfering frequencies with a single analog-to-digital converter. The system receives a plurality of input signals at various frequencies and front end circuits filter out first and second frequencies. A mixer and a front end oscillator are in communication with one of the front end circuits for mixing a front end frequency with one of the first and second frequencies prior to the analog-to-digital converter. A summer combines the output of the mixer with the output of one of the front end circuits. An analog-to-digital converter is connected to the summer for converting the analog input signal to a digital output signal. The first and second frequencies may be separately processed after they have been combined, even if they were identical frequencies.

Abstract: The invention relates to a method for carrying out a frequency change whilst retaining the phase relationship between several devices, in particular, network analyzers. Each device has at least one signal generator for stimulating an object for measurement and at least one local oscillator, connected to at least one mixer, for receiving a measuring signal obtained from the object for measurement by the superposition principle. On changing frequency, in a first step, only the frequency of the local oscillators of all devices is changed and the frequency of the signal generators of all devices remains unchanged. In a second step, only the frequency of at least one signal generator is changed and the frequency of the local oscillators of all devices remains unchanged.

Abstract: Phase detector circuitry for a phase-locked loop frequency synthesizer, the phase detector circuitry comprising a reference input configured to receive a reference signal; a feedback input configured to receive a divided signal from divider circuitry in a feedback path of the phase-locked loop; and pulse generation circuitry configured to generate control pulses for controlling a charge pump in the phase-locked loop in accordance with a frequency and phase relationship between the reference signal and the divided signal; wherein the divided signal comprises a pulse having a length shorter than a half period of the divided signal, and wherein the pulse generation circuitry is configured to generate the control pulses by masking the reference signal using the pulse of the divided signal as a mask, so as to define the edges of the control pulses from the edges of the divided signal and an edge of the reference signal.

Abstract: An apparatus and a method are disclosed wherein a clock generator component converts a received clock signal into a plurality of internal clock signals which are skewed in time, a phase difference component computes phase differences at subsequent clock phases of a received phase signal, an intermediate averaging component receives each phase difference signals and outputs their average, a threshold detection component detects steady phase changes and activates a preamble detect signal which is used to clock an output filter that smoothes the output from the intermediate averaging component. The output is a frequency correction signal that is used by a wireless receiver to correct its reception process. The disclosed invention merges the frequency correction process more quickly and accurately, is less likely to trigger on noise and has a lower packet error rate than conventional systems.

Abstract: An apparatus employing control words to present a synthesized output signal having an output frequency and a delay with respect to an input signal includes: (a) A multiplexer receiving the input signal and having an output and an address input. (b) An output unit generates the output signal in response to a drive signal from the multiplexer. (c) A first register coupled with the multiplexer output. (d) A second register coupled with the multiplexer and the first register. The first register responds to a multiplexer output signal to provide a first control signal to the second register based upon the control words. The second register responds to the multiplexer output signal to provide a second control signal to the address input based upon the first control signal and the control words. The multiplexer presents the drive signal in response to the second control signal.

Abstract: According to one embodiment, a frequency characteristic adjusting circuit includes a cutoff range adjusting module and a control signal inputting module. The cutoff range adjusting module is connected to an AC coupling circuit capacitively coupled with a signal transmission path, and allows an output signal from the AC coupling circuit to pass through such that a low cutoff range in the frequency characteristic of the AC coupling circuit varies. The control signal inputting module receives a control signal to control a zero-point frequency based on a numerator polynomial of a transfer function of the cutoff range adjusting module and a pole frequency based on a denominator polynomial of the transfer function. The numerator polynomial is equalized to a denominator polynomial of a transfer function of the AC coupling circuit by the control signal. A cutoff frequency is determined by the pole frequency according to the control signal.

Abstract: A method of reducing thermal stresses of a semiconductor component in a frequency converter, an arrangement in a frequency converter, and a frequency converter, wherein the semiconductor component is attached to a cooling element for cooling the semiconductor component and one or more resistive elements are attached to the cooling element. In the method, the cooling element is heated by the one or more resistive elements attached thereto by supplying current from the frequency converter through the one or more resistive elements for obtaining an elevated lowest temperature for the semiconductor component and thereby reducing the amount of temperature change between the highest and the lowest temperatures in the semiconductor component during use of the frequency converter.

Abstract: The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.

Abstract: This invention relates to a process for producing a pulsed sampled waveform comprising generating a baseband signal representing the integral of a desired output waveform; sampling and differentiating the baseband signal to produce frequency images of the baseband spectrum at multiples of the sampling rate; employing an analog bandpass filter to pass the spectral image centered at the desired up-conversion frequency band. This invention also relates to an apparatus for creating a high frequency output waveform signal comprising a means for generating a baseband signal representing the integral of a desired output waveform; a means for sampling the baseband signal; a means for generating a time delayed baseband signal by ?t; a means for inverting the delayed baseband signal; a means for summing the inverted the delayed baseband signal with the sampled baseband signal; a means for filtering to pass the high frequency signal.

Abstract: A frequency-mixing device performing voltage multiplying and low-pass filtering operations in addition to frequency mixing is provided. The three operations may be carried out with the same components by designing the frequency mixer appropriately. The frequency mixer comprises a first capacitance connected in series to the input of the frequency-mixing device, a first switch connected in parallel to the first capacitance, a second switch connected in series to the first capacitance, and a second capacitance connected in parallel to the second switching means. The switches are controlled by a local oscillator signal to close and open alternately according to a change in the voltage level of the first oscillator signal.

Abstract: A band converted signal generator includes a low range characteristic application section (16) as a component emphasis means emphasizing only one or more specific frequency components selected from among frequency components of an input signal; and a low pass filter (17) as a component extraction means extracting a signal component of a desired frequency band from an output signal supplied from the low range characteristic application section (16). A band extender (1000) includes the above-mentioned band converted signal generator, and an adder (15) adding the input signal, a certain frequency band of which is suppressed, and a signal including at least one component generated within the certain frequency band which is suppressed.

Abstract: According to one embodiment, a radio frequency receiver includes a quadrature mixer for converting radio frequency signals to baseband signals or intermediate frequency signals. The quadrature mixer includes an in-phase passive mixer and a quadrature-phase passive mixer. Each passive mixer includes a mixer core having a plurality of mixer input switch transistors and a plurality of output switch transistors connected to the mixer input switch transistors. Clock circuitry generates a first set of clock signals and a second set of clock signals. The first set of clock signals has a frequency twice that of the second set of clock signals. The first set of clock signals is arranged to drive the mixer input switch transistors and the second set of clock signals is arranged to drive the output switch transistors.

Abstract: A signal generation apparatus, a frequency converting apparatus and a receiver, in which the signal generation apparatus includes an oscillator, a duty cycle adjusting circuit, and a signal generation circuit. The oscillator generates differential signals. The duty cycle adjusting circuit adjusts duty cycles of differential output signals, in response to at least one of a plurality of control signals, to adjust phases of the differential output signals generated according to a result of amplifying a difference between the differential signals input through a pair of input terminals so as to output duty cycle adjusted differential output signals to a pair of output terminals. The signal generation circuit outputs an in-phase signal and a quadrature-phase signal in response to the duty cycle adjusted differential output signals.

Abstract: An integrated circuit includes a volatile memory, a central processing unit that normally operates on a first clock, and an input-output circuit that transfers data in synchronization with a second clock having a lower frequency than the first clock. The integrated circuit has a power-saving mode in which the volatile memory loses its data and the central processing unit stops operating. The power-saving mode is preceded and followed by transitional periods during which the central processing unit uses the input-output circuit to save data from the volatile memory to an external memory device and restore the data from the external memory device to the volatile memory. During these transitional periods, the central processing unit operates on the second clock to conserve power.

Abstract: An integrated circuit device is provided including a plurality of circuit blocks which operate based on a clock signal. The quartz oscillation circuit outputs a first clock signal. A spectrum spread clock generator outputs a second clock signal having a spread frequency. A clock signal is output to the plurality of circuit blocks and, based on an instruction to output the clock signal from a CPU, a clock signal output to the plurality of circuit blocks is switched from the second clock signal to the first clock signal.

Abstract: A PWM signal generating circuit according to the invention includes a digital PWM signal generating circuit that generates a digital PWM signal having a resolution of 2n based on a clock signal CLK and n-bits (n?1) of digital information; a triangular wave generator that generates a triangular wave (e.g. ramp wave) synchronized with the clock signal CLK; and a comparator that compares the triangular wave with a threshold value. The PWM signal generating circuit increases the resolution of the digital PWM signal based on an output from the comparator.

Abstract: A method for ramping a high-speed clock to control power surge in an integrated circuit when transitioning from a low power holdstate to an operational state where the integrated circuit includes selected logic circuits adapted to be maintained in the holdstate. A core clock signal including a plurality of core clock pulses is gated with a ramping signal. The ramping signal includes a series of staged signals having gating pulses. Each staged signal is separated by a ramp interval, where the series of staged signals successively enables increasing numbers of clocking pulses from the core clock signal to be transmitted to a holdstate output until a predetermined operational core clock frequency is transmitted to the holdstate output bringing the integrated circuit to the operational state.

Abstract: Methods and apparatus for distributing clock signals to an integrated circuit provide for: producing, in a slow mode of operation, a first clock signal having at least first and second on-pulses of differing first and second on-times each period, respectively, where a sum of the first and second on-times is approximately equal to a sum of off-times each period; distributing the first clock signal through a distribution tree and terminating at a plurality of final buffer circuits that produce respective distributed clock signals from which respective second clock signals are produced to supply at least a portion of the integrated circuit; deleting the second on-pulse from each of the distributed clock signals each period to produce the respective second clock signals, the second clock signals each including at least a portion of the first on-pulse, but none of the second on-pulse each period.

Abstract: A high speed divider circuit is disclosed. The circuit contains a plurality of latches and buffers. The maximum input clock frequency of the divider circuit is increased over that implemented with only latches connected in a ring by feed forwarding the output of an early switching latch to the output of a later switching latch through buffers. The feed forward signal aids the later switching latch to complete the next state transition. By choosing the appropriate ratio of the buffer tail current to the latch tail current, the divider circuit can be made into a dynamic divider circuit.

Abstract: A circuit is described that detects high and low frequencies and additional clock frequencies and outputs a signal that indicates a high, a low frequency or an additional mode. When in the low frequency low frequency mode signals are regenerated free of any high frequency signals from appearing on the filtered low frequency clock line. The rising and falling edges of the input clock are low pass filtered separately and then combined to generate a low frequency clock or the additional input clock and that retains the input clock pulse width and duty cycle.

Abstract: An automatic adjustment circuit comprises a replica (1) constituted of either a circuit block of a portion of a filter body (3) or a combination of the circuit block, and fed with a reference signal (2) from the outside, for outputting signals having a phase delays of 90 degrees and 180 degrees with respect to the reference signal (2), and an integrating comparator (4) fed at its input terminal with an output signal, as having a phase delay of 180 degrees, of the replica (1) and the reference signal (2), and at its clock terminal with an output signal, as having a phase delay of 90 degrees, of the replica (1), and having an output terminal connected with a capacity (C1) and a frequency characteristic adjusting terminal of the replica (1). The automatic adjusting circuit is characterized in that the integrating action of the integrating comparator (4) is performed across the two high/low states of the input signal.

Abstract: A frequency conversion apparatus includes a frequency generation circuit, which is based on a first semiconductor material having a first elemental composition and is coupled to generate one or more Local Oscillator (LO) signals. The apparatus further includes a conversion circuit, which is based on a second semiconductor material having a second elemental composition different from the first elemental composition. The conversion circuit is coupled to accept an input signal in a first frequency range and to convert the input signal to an output signal in a second frequency range by mixing the input signal with the one or more LO signals.

Abstract: A frequency adjusting circuit for a central processing unit (CPU) includes a transforming unit for transforming a change of a current signal of the CPU into a voltage signal, an amplifying unit for amplifying the voltage signal from the transforming unit, a switching unit being turned on or turned off by the amplified voltage signal from the amplifying unit, and a basic input/output chip for regulating a frequency of the CPU through a clock generator.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A mixer and calibration method thereof are provided. A direct conversion receiver comprises a differential loading pair utilizing at least one binary weighted resistor. The binary weighted resistor is adjustable to provide a resistance linear to a digital code, comprising a fixed resistor and an adjustable resistor cascaded to the fixed resistor in parallel. Every increment of the digital code induces an equal increment of the resistance. The magnitude of every incremental resistance is below a negligible ratio of the fixed resistor.

Abstract: The invention provides an apparatus for adjusting a working frequency of a VRD by detecting temperature. The apparatus includes a temperature control module, a load module and a controller. The temperature control module is used for detecting a temperature of a CPU, and judging an output load state of the VRD according to the detected temperature of the CPU, so as to output a control signal according the output load state. The load module is connected to the VRD, and is used for providing an external resistance to the VRD. The controller is respectively coupled to the load module and the temperature control module, and is used for receiving the control signal and adjusting a resistance of the load module according to the received control signal, so as to adjust a working frequency of the VRD. A power consumption of the VRD may be reduced based on the present invention.

Abstract: A multiplier circuit includes a bias circuit which outputs a reference voltage and a bias signal, a first delay circuit which inputs an input signal and outputs a first delayed signal according to the reference voltage and the bias signal, a second delay circuit which inputs an inversed input signal and outputs a second delay signal according to the reference voltage and the bias signal, and an OR circuit which outputs an OR logic result generated responsive to the first and second delayed signals.

Abstract: An up-conversion mixer includes a first and a second hybrid couplers and a first and a second traveling-wave mixers is disclosed. The first hybrid coupler receives an input intermediate frequency (IF) signal and produces a first IF signal (IF1) and a second IF (IF2) signal, the second IF signal being 180 degree off-phase compared to the first IF signal. The first traveling-wave mixer mixes the first IF signal (IF1) and a first local oscillator (LO1) signal to produces a first radio frequency signal (RF1). The second traveling-wave mixer mixes the second IF signal (IF2) and a second local oscillator signal (LO2) to produces a second RF signal (RF2). The second hybrid coupler to combines the first RF signal and the second RF signal to produce an output RF signal. The use of the traveling-wave mixers allow for a wide bandwidth operation of the up-conversion mixer.

Abstract: Aspects of a method and system for a distributed transceiver for high frequency applications may include generating a second signal from a first signal by frequency-translating the first signal via a plurality of conversion stages. Each of the plurality of conversion stages may frequency-translate a corresponding input signal by a local oscillator frequency or by a fraction of said local oscillator frequency. The first signal may be the corresponding input signal to an initial stage of a the plurality of conversion stages, an output signal of a previous one of the plurality of conversion stages may be the corresponding input signal to a subsequent one of the plurality of conversion stages, and the second signal may be an output signal of a final stage of the plurality of conversion stages.

Abstract: An image rejection mixer including a first and a second hybrid couplers and a first and a second traveling-wave mixers is disclosed. The first hybrid coupler divides an input radio frequency (RF) signal to a first RF signal and a second RF signal, the second RF signal being in quadrature to the first RF signal. The first traveling-wave mixer mixes the first RF signal and a local oscillator (LO) signal to produces a first intermediate frequency (IF) signal. The second traveling-wave mixer mixes the second RF signal and the local oscillator signal to produces a second IF signal. The second hybrid coupler combines the first IF signal and the second IF signal to produce an upper sideband of the IF signals and a lower sideband of the IF signals. The use of the traveling-wave mixers allow for a wide bandwidth operation of the image rejection mixer.

Abstract: A mixer circuit includes a voltage-to-current converter which converts a positive phase input voltage signal and a reversed phase input voltage signal input to a first input terminal and a second input terminal into a positive phase current signal and a reversed phase current signal, a switching circuit switches over the positive phase current signal and the reversed phase current signal according to a positive phase local signal and a reversed phase local signal, and generates a positive phase output current signal and a reversed phase output current signal, and an impedance element connected between the first common terminal and the second common terminal, having a relatively high impedance to a differential-mode signal between the positive phase current signal and the reversed phase current signal, and having a relatively low impedance to a common-mode signal between the positive phase current signal and the reversed phase current signal.

Abstract: In an exemplary embodiment, a circuit is disclosed comprising a plurality of inputs, each input to receive a radio frequency waveform from a plurality of differential input waveforms having different phases; and an inverter circuit to invert a waveform from the plurality of differential inputs waveforms to a substantially same phase as a non-inverted input waveform. The circuit further comprises a combiner node to combine the inverted and the non-inverted input waveforms into an output waveform.

Abstract: Disclosed is an apparatus and a method for up-converting frequencies of digital Intermediate Frequency (IF) signals input through at least two paths, and then outputting IF signals to which at least two frequencies are allocated in a communication system. The apparatus includes Serializer/Deserializers (SerDeses), down-converters, up-converters, a signal adder, a Digital-to-Analog Converter (DAC), and a Band-Pass Filter (BPF), etc. In relation to digital IF signals respectively input through at least two paths, first, the frequency down-conversion is performed, and then, the up-conversion to relatively low frequencies is performed.

Abstract: The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.

Abstract: A steady state frequency control circuit for a variable frequency regulator including an open loop frequency control circuit, a frequency detector and a comparator circuit. The variable frequency regulator provides a clock signal indicating actual operating frequency and has a frequency control parameter for adjusting steady state operating frequency. The frequency detector receives the clock signal and provides a frequency sense signal which is compared with a steady state frequency reference signal to provide a frequency adjust signal. The frequency control parameter is adjusted by the frequency adjust signal to control steady state frequency.

Abstract: A frequency generator apparatus and a control circuit thereof are provided. The frequency generator apparatus comprises the control circuit and a frequency generator, wherein the control circuit contains an electric fuse (efuse). The control circuit outputs an enabling signal according to the state of the efuse. The frequency generator is coupled to the control circuit, receives the enabling signal, and decides to output a frequency signal or not according to the enabling signal.

Abstract: A communication apparatus and a method for generating a signal thereof are provided. The communication apparatus adjusts a bandwidth or central frequency of an oscillating signal which is generated from a chaotic signal to be used in the modulation, or adjusts both the bandwidth and the central frequency. Accordingly, it is possible to transform the oscillating signal generated from the chaotic signal more diversely and thus to modulate an information signal more diversely and more adaptively.

Abstract: Transmitter and transmission circuit. For realizing a differential transmitter, a switch circuit is connected between two load transistors of two complementary MOS pairs. The switch circuit can have two inductors. When the two complementary MOS pairs are conducting current to drive signal transition at output nodes, the inductors open to make the load transistors stop draining current. Also, the switch circuit can have switch transistor controlled by an edge detector for detecting raising and falling edges of the input signals, such that the switch circuit can make the load transistors stop draining current accordingly. In this way, raising and falling edges of the output signals are emphasized to improve signal propagation.

Abstract: A detection device for detecting an oscillator is provided. The detection device includes an oscillator control circuit, a frequency-decreasing circuit and a display circuit. The oscillator control circuit is used for outputting the oscillator signal of the oscillator. The frequency-decreasing circuit is connected to the output of the oscillator control circuit and has a capacitor suitable for charging and discharging and a resistor, which can adjust the time constant of the oscillator signal. The display circuit is connected to the frequency-decreasing circuit for showing the output signal of the frequency-decreasing circuit. The detection device can decide whether the oscillator is normal or broken by observing a component of the display circuit, for example, the twinkling of a light emitting diode of the display circuit.

Abstract: Described herein are techniques for providing a mixer circuit having a mixer core. The mixer circuit includes a variable current block that is arranged to feed the mixer core with an amplified input signal.

Abstract: A mixer system includes a multi-phase signal generator, a mixer, and a mixer control circuit. The multi-phase signal generator generates a plurality of mixer input signals, where each has a frequency equal to the others, and a phase, and where the phases are distributed between 0 to 360 degrees. The mixer control circuit generates a plurality of mixer control voltages which are controlled by digital state control input signals. Each mixer control voltage controls the influence of a corresponding mixer input signal on the mixer output signal. In a preferred embodiment, the mixer control voltage is generated by storing a charge on a capacitor, and said charge is increased or decreased through the combined action of the digital state control input signals and the mixer control voltages by means of interconnected mixer control subcircuits.

Abstract: A high performance phase detector includes a local digital oscillator for generating a digital reference signal of programmable frequency and phase. The phase detector accumulates a difference in phase between the digital reference signal and a sampled input signal to produce a measure of phase error. The phase detector can be advantageously used in a frequency synthesizer to produce signals with low phase noise and accurate phase control. Synthesizers of this type can further be used to as building blocks in ATE systems and other electronic systems for generating low jitter clocks and waveforms.

Abstract: According to an embodiment of the invention, there is provided a frequency converter including: an input circuit converting a voltage signal to a current signal; a load circuit supplying a constant current to an input circuit; a first switch circuit configured to output a current signal from the first output terminal in accordance with a switching made in accordance with a first oscillation signal; a second switch circuit configured to output the current signal from the second output terminal in accordance with a switching made in accordance with a second oscillation signal being 180 degrees out of phase with the first oscillation signal; a control circuit generating a control current based on a predetermined reference voltage and an average voltage of the voltages at the first and second output terminals and adding the control current to the current signal of the input circuit.

Abstract: A frequency conversion device, which may include a radiofrequency (RF) mixer device, includes a substrate and a ferromagnetic film disposed over a surface of the substrate. An insulator is disposed over the ferromagnetic film and at least one microstrip antenna is disposed over the insulator. The ferromagnetic film provides a non-linear response to the frequency conversion device. The frequency conversion device may be used for signal mixing and amplification. The frequency conversion device may also be used in data encryption applications.

Abstract: A digital circuit generates very precise varying clock frequencies for applications that can tolerate a small degree of jitter but require exact longer term frequencies, e.g. a video clock for a laser printer. Some subpixel jitter is acceptable, but the overall pixel rate remains exact and consistent. In some applications, the jitter may be desirable to smear the EMI spectrum. For example, if the high frequency input clock is modulated, the edges of the video clock will also be modulated yet remain within the jitter and frequency specification.

Abstract: An integrated semiconductor image-rejection mixer having high linearity and high gain. In addition to the components of a classic image-rejection architecture, the present mixer has a high-frequency current-diverting stage that permits the operation of the output stage with high conversion gain and sufficient headroom for good linearity, even in cases where the supply voltage is relatively low (such as 3 V). The conversion gain of the mixer and its image-rejection performance can be changed by changing the load resistances and the elements of the output polyphase network, with minor effects on linearity and no change in power consumption or DC levels. The power consumption of the image-rejection mixer is low because no additional DC current is required for buffers or amplifier stages.