Abstract: An apparatus for adaptive thermal management of a device with user configuration capability, including a secure memory configured to store a thermal management policy; thermal monitoring circuitry configured to monitor thermal states associated with one or more sensor sub-systems of the device; and policy enforcement circuitry configured to implement the stored thermal management policy in response to the monitored thermal state violating a thermal threshold.

Abstract: A computer system for use in determining the minimum and/or maximum value of a specified subsequence of a sequence of values is disclosed. The computer system comprises a database that is configured to store a sequence of values, to identify a minimum and/or maximum value of the sequence of values, and to define at least a first subsequence of values and a second subsequence of values immediately following the first subsequence of values, wherein the boundary between the first and second subsequences is located at the position of either the minimum or maximum value of the sequence.

Abstract: A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes one or more processing units each of which operates with respective operating parameters. One or more temperature sensors are included to measure a temperature of the one or more processing units during operation. When the measured temperature exceeds a threshold, a power manager on the chip determines a temperature headroom utilizing temperature values based on worst-case ambient temperature. When the measured temperature does not exceed the threshold, the power manager determines the temperature headroom utilizing at least one temperature value based on room ambient temperature. Following, the power manager adjusts the respective operating parameters based on at least the temperature headroom.

Abstract: A power harvesting circuit for use in an open drain transmitter circuit is configured to generate two distinct harvested supply voltages at different voltage levels along with two distinct cascode voltages at different voltage levels. The harvested supply voltages are used to power circuitry in the transmitter circuit. The cascode voltages are used to bias cascode transistors in the open drain circuitry for different channels.

Abstract: Techniques for reducing electromagnetic (EM) emission in a wager-based gaming machine. A gaming machine includes one or more processors configured to generate a bus clock signal having a fundamental frequency and fundamental spectral components at harmonics of the fundamental frequency. The fundamental spectral components each have a fundamental amplitude. A signal processor is configured to generate a spread spectrum clock signal having a nominal frequency substantially equivalent to the fundamental frequency of the bus clock signal as well as nominal spectral components at harmonics of the nominal frequency. However, the nominal spectral components each have a nominal amplitude less than the fundamental amplitude of a fundamental spectral component at the same harmonic. A bus connects the signal processor with one or more elements and carries the spread spectrum clock signal to the one or more elements, thereby reducing EM emissions from the bus.

Abstract: A spin modulator with phase tuning means which comprises, a spin array which consists of m×n matrix spin-transfer torque oscillators, a selection control means which selectively operates the spin-transfer torque oscillators according to an operation condition of the spin array, and a phase tuning array which includes m×n matrix phase tuning means, wherein the m×n matrix phase tuning means tune a phase synchronization operation of the spin-transfer torque oscillators according to the operation condition.

Abstract: Techniques are described for increasing the speed of a resistor-based charge pump for an active loop filter-based phase-locked loop (PLL). The techniques may include placing a low-resistance discharge path between respective nodes of a current source and sink in a charge pump, and selectively activating the low-resistance discharge path when the charge pump is turned off. The low-resistance discharge path may have a resistance that is lower than the resistance of other current paths between the respective nodes in the charge pump (e.g., current paths formed by the resistors included in the current source and sink of the charge pump), thereby reducing the amount of time needed to reset the charge on the respective nodes when the charge pump is turned off. In this way, the speed of a resistor-based charge pump may be increased, thereby allowing the overall speed of an active filter-based PLL to be increased.

Abstract: An overshoot compensation circuit for an input signal, having a slew rate detection circuit configured to detect a slew rate of the input signal; a run time circuit configured to initialize a predetermined run time when an absolute value of the slew rate of the input signal is greater than or equal to a predetermined threshold; and a low pass filter configured to decrease the slew rate of the input signal only during the predetermined run time.

Abstract: There is provided a reception circuit that includes a local signal generation section, a duty-cycle correction section, an oscillation signal generation section, and a mixture section. The local signal generation section is configured to generate a local signal, the local signal being different in frequency from a modulated reception signal. The duty-cycle correction section is configured to correct a duty cycle of the generated local signal to be a predetermined value. The oscillation signal generation section is configured to generate a plurality of oscillation signals, the oscillation signals being generated using the duty-cycle-corrected local signal to vary in phase. The mixture section is configured to mix the reception signal with each of the oscillation signals.

Abstract: A bypass module including a plurality of P-Channel MOSFETs connected in parallel to form a P-Channel MOSFET array, a plurality of N-Channel MOSFETs connected in parallel to form a N-Channel MOSFET array, and a control module to control switching of the P-Channel MOSFET array and the N-Channel MOSFET array is disclosed. A battery or load management device used to switch higher current and low voltages is disclosed. A battery bypass and bypass method for charge, discharge, and charge limiting control for various types of batteries is disclosed.

Abstract: A frequency doubling device suitable to generate an output terminal voltage oscillating at a differential frequency double the frequency of the input differential voltage, includes a first differential pair of P-type transistors and a second differential pair of N-type transistors controlled by the differential input voltage, as well as an LC oscillator including a LC resonant dipole through which the absorbed current is forced by two differential pairs of transistors.

Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.

Abstract: A broadband linear amplifier including an input, a first distributed amplifier coupled to the input and having a bias for one of Class A or Class AB operation, the first distributed amplifier including a first plurality of field effect transistors and having a first output, a second distributed amplifier coupled to the input and having a bias for Class C operation, the second distributed amplifier including a second plurality of field effect transistors and having a second output, and a summed output coupled to the first output and the second output, wherein gate widths of the first plurality of field effect transistors monotonically decrease from the input to the first output, and wherein gate widths of the second plurality of field effect transistors monotonically decrease from the input to the second output.

Abstract: Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).

Abstract: A method of providing multiple voltage references to a radio-frequency device using a single analog line includes the steps of setting the analog line voltage level to be a first reference voltage signal; instructing a first voltage reference device to memorize the first reference voltage signal by sending a first digital control signal to a digital line; providing the first reference voltage signal to the RF device via the first voltage reference device; re-setting the analog line voltage level to be a second reference voltage signal; instructing a second voltage reference device to memorize the second reference voltage signal by sending a second digital control signal to the digital line, the second digital control signal being different from the first digital control signal; and providing the second reference voltage signal to the RF device via the second voltage reference device.

Abstract: A data bus synchronizer includes a plurality of registers arranged in a cascade, configured to generate a synchronized output in response to sampling an asynchronous bus without an enable signal, where the plurality of registers receive a value on the asynchronous bus. A last register of the plurality of registers is configured to generate the synchronized output in response to a load enable signal. The data bus synchronizer further includes a logic block configured to generate the load enable signal on satisfaction of a logic condition.

Abstract: A frequency generation device is provided. The frequency generation device includes a voltage generation unit configured to receive an input signal having an input frequency and to generate a feedback voltage based on the input signal, wherein the feedback voltage is proportional to the input frequency; and a feedback unit connected to the voltage generation unit and a reference voltage source, wherein the feedback unit is configured to receive a reference voltage from the reference voltage source and the feedback voltage from the voltage generation unit, so as to generate a feedback signal having a feedback frequency.

Abstract: A multiplier circuit and wireless communication apparatus that adjust an output level of a desired multiple wave to a desired range is provided. The multiplier circuit includes a multiple wave output unit configured to receive an input signal of a predetermined frequency, to output a multiple wave that is a predetermined multiple of the input signal, and control harmonic distortion associated with the output of the multiple wave based on a gate-source voltage; and a controller configured to adjust the gate-source voltage.

Abstract: Systems and methods which utilize low performance circuitry to provide received signal power detection without unacceptably impacting operation of a receiver circuit are shown. Circuitry utilized to provide received signal power detection according to embodiments comprises circuitry dedicated for use with respect to received signal power detection. Performance of the circuitry of the detection path may be lower than that required of circuitry of the signal processing path. However, performance parameters are selected to provide power detection of desired accuracy (e.g., flat gain) and to meet other performance metrics. Embodiments provide a low performance power detection circuit comprising a low performance tuner configuration. Further embodiments provide a low performance power detection circuit comprising a low performance data converter configuration.

Abstract: A frequency mixer is disclosed. In an implementation, the multi-LO band switched-core includes a single field-effect transistor (FET) ring having a first mixer core and a second mixer core. The first mixer core and the second mixer core configured to connect to a radio frequency (RF) port and an intermediate frequency (IF) port. The frequency mixer also includes a first local oscillator (LO) transformer and a second LO transformer. The first LO transformer is configured to furnish a first LO signal occurring in a first limited range of frequencies to the first mixer core, and the second LO transformer is configured to furnish a second LO signal occurring in a second limited range of frequencies to the second mixer core.

Abstract: There is provided an integrated circuit having a plurality of circuit blocks. An acquisition unit acquires a request of a reset operation for at least one of the plurality of circuit blocks. A determination unit determines, based on constraining condition information indicating whether or not a reset target circuit block can perform the reset operation simultaneously with another circuit block in which the reset operation is underway, whether or not to instruct the reset target circuit block to perform the reset operation according to the request. An instruction unit instructs the reset target circuit block to start the reset operation according to the request when the determination unit determines to instruct the reset target circuit block to perform the reset operation.

Abstract: A frequency compensation apparatus includes a first counter setting a reference period using a main clock, a second counter sensing a change in the frequency of a sub clock using the reference period, and a frequency compensator providing a compensated frequency using information on the changed frequency of the sub clock. Related methods are also described.

Abstract: A frequency tripler device is disclosed. The frequency tripler device includes a first graphene based field effect transistor (FET) of a first dopant type, having a gate, a drain, and a source, and a second graphene based FET of a second dopant type, having a gate, a drain, and a source, the gate of the first FET coupled to the gate of the second FET and coupled to an input signal having an alternating current (AC) signal of a first frequency, the combination of the first and second FETs generates an output signal with a dominant AC signal of a frequency of about three times the first frequency.

Abstract: Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering frequency range of at least one victim circuit in an IC are disclosed. In an embodiment, a signal interference mitigation circuit is configured to be associated with the aggressor circuit and includes a clock divider circuit and a control circuit. The clock divider circuit is configured to generate the first clock signal based on a second clock signal and a division factor pattern. The control circuit is coupled with the clock divider circuit and configured to determine the division factor pattern and provide the division factor pattern to the clock divider circuit. The division factor pattern comprises a plurality of division factors selected randomly based on a plurality of random numbers, and is configured to control a throughput frequency associated with the signal interference mitigation circuit.

Abstract: A received is disclosed that is capable of improving reception sensitivity while avoiding an increase in circuit scale. The receiver includes: a multi-phase local oscillation signal generating section that generates a plurality of local oscillation signals of different phases; a phase selection signal generating section that generates a phase selection signal used to select a baseband signal of a predetermined phase based on a detection result of a reception level of a high-frequency signal; and a frequency converter that frequency-converts the high-frequency signal based on the plurality of local oscillation signals, that generates a plurality of baseband signals of different phases, and that selects a baseband signal from among the plurality of baseband signals based on the phase selection signal.

Abstract: A spectrum analyzer for measuring an RF signal over a selected frequency span configured to use multiple Intermediate Frequencies (IFs) for residual, spurious and image signal reduction. The spectrum analyzer has both a primary IF path and a secondary IF path configured to provide band pass filtering of the IF signals. A master clock synthesizer is configured to reduce residual noise by providing from a single Voltage Controlled Oscillator, a master clock signal and a Local Oscillator (LO) signal. The spectrum analyzer has a microcontroller configured to change the frequency of the master clock signal and the LO signal if the center frequency of the selected span is sufficiently close to a known spurious signal.

Abstract: A system and method for efficient detection of Low Frequency Periodic Signaling (LFPS) input signals. A receiver receives two input differential signals that are LFPS input signals. The receiver increases the common-mode voltage for each of the two input differential signals and determines two polarity opposite differences between the level shifted intermediate differential signals. The differences are used to generate two series of relatively narrow pulses by comparisons with a given threshold. A wide continuous pulse is asserted when an initial pulse among the two series of pulses is detected. The wide continuous pulse is deasserted when a final pulse among the two series of pulses is detected. While the wide continuous pulse is asserted, control logic is awakend and performs a Universal Serial Bus (USB) protocol for processing data on the input differential signals.

Abstract: An arrangement which includes two or more energy storage units for electrical energy connected in series, and two or more balancing resistor units. Each balancing resistor unit is connected in parallel with one of the energy storage units. The arrangement also includes means for determining a voltage over all of the series-connected energy storage units and means for determining the energy storage unit voltages between poles of the energy storage units. One or more of the balancing resistor units include a base resistor unit and a control resistor unit connected in series and a switching device connected in parallel with the control resistor units.

Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.

Abstract: This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.

Abstract: A circuit to generate a sweep frequency signal that includes a reference frequency source to generate a reference frequency signal, a first frequency combination circuit coupled to the reference frequency source, and operative to generate a sweep frequency signal in a first frequency band based on the reference frequency signal, a second frequency combination circuit coupled to the reference frequency source, and operative to generate a sweep frequency signal in a second frequency band different from the first frequency band based on the reference frequency signal, a multiple-level switch coupled to outputs of the first frequency combination circuit and the second frequency combination circuit, and a control circuit controlling the first and second frequency combination circuits and the multiple-level switch to output the sweep frequency signal in the first frequency band and the sweep frequency signal in the second frequency band at an output of the multiple-level switch alternately.

Abstract: Exemplary embodiments are related to a clock doubler. A device may include a duty cycle correction circuit configured to receive an input clock signal and convey a corrected clock signal. The duty cycle correction circuit may include a first circuit to convey an output voltage during a first cycle of the input clock signal and correct a current mismatch of the first circuit during a second cycle of the input clock signal. The duty cycle correction circuit may also include a second circuit to convey the output voltage during the second cycle and correct a current mismatch of the second circuit during the first cycle. Further, the device may include a clock generator for receiving the corrected clock signal and generating an output clock.

Abstract: A device reduces its energy consumption using a relatively lower frequency and lower power secondary oscillator to maintain timing information when a higher frequency and higher power primary oscillator is inactivated. The secondary oscillator maintains timing information at a higher resolution than the period of the oscillator, so as to conserve synchronization when the higher frequency, higher power primary oscillator is inactivated. In some embodiments, a microsequencer is programmably configured to control an integrated radio receiver and transmitter using less power than an associated microprocessor would use to perform the same functions. In other embodiments, flexible event timing facilitates the merging of wake-up events to reduce the energy consumed by wake-up operations in the device.

Abstract: A transconductance-enhancing passive frequency mixer comprises a transconductance amplification stage, a frequency mixing stage, and an output transresistance amplifier. The transconductance amplification stage has a pre-amplification transconductance-enhancing structure, so that the transconductance is greatly enhanced, thereby obtaining the same transconductance value at a lower bias current. A radio-frequency current is modulated by the frequency mixing stage to generate an output mid-frequency current signal. The mid-frequency current signal passes through the transresistance amplifier, to form voltage output, and finally obtain a mid-frequency voltage signal. The transresistance amplifier has a transconductance-enhancing structure, thereby further reducing input impedance, and improving current utilization efficiency and port isolation. The frequency mixer has the characteristics of low power consumption, high conversion gain, good port isolation, and the like.

Abstract: Methods and systems to control an output frequency relative to a reference frequency. A frequency control system includes a dual-input bias generator to separately receive management and operational controls. The bias generator includes a first bias generator circuit to generate a bias control based on a difference between the management control and a bias feedback reference during a first mode of operation, a second bias generator circuit to generate the bias control based on a difference between the operational control and the bias feedback reference during a second mode of operation, and a bias feedback reference circuit to generate the bias feedback reference based on the bias control. The first mode may include a characterization and/or a start-up mode. The second mode may include an operational mode, such as a feedback-controlled mode.

Abstract: Apparatus and methods for distributing spurious tones through the frequency domain are disclosed. One such apparatus can include a dithering circuit configured to generate a sequence of numbers that exhibit statistical randomness and a variable frequency circuit configured to adjust a frequency of an output based on the sequence of numbers so as to spread energy of spurious tones in a frequency response of the output to lower a noise floor. In one example, spurious tones can be reduced in a negative voltage generator of a radio frequency (RF) attenuator.

Abstract: Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.

Abstract: An apparatus for monitoring timing of a plurality of critical paths of a functional circuit includes a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events. Each canary circuit includes an adjustable delay element and an analyzer circuit for receiving a count of the critical timing event output from at least one of the plurality of canary circuits for a predetermined time interval for a plurality of delay values of the adjustable delay elements and for determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values.

Abstract: The present invention relates to a clock signal generating circuit and a power supply including the same. The present invention includes: a counter for counting one period of an input clock signal by using a reference clock signal, and generating a count signal; and a clock signal generator for receiving the count signal and the reference clock signal, dividing the count signal to generate a quotient and a remainder, setting the quotient as a reference period of an output clock signal, and distributing and disposing the remainder to the output clock signal with a plurality of periods occurring for one period of the input clock signal.

Abstract: A frequency converter includes a comparator, an error computation unit and a calibration unit. The comparator receives a reference voltage signal and a triangle wave signal, and outputs a switching signal. The switching signal is fed back to the error computation unit to calculate an error signal by computing the reference signal and the switching signal. The calibration unit calibrates the triangle wave signal or the reference voltage signal according to the error signal.

Abstract: A signal generating circuit for generating a fan driving signal includes a phase adjusting circuit, a direct digital frequency synthesizer, a first operating circuit, a driving signal generator and a second operating circuit. The phase adjusting circuit receives a hall signal and adjusts a phase of the hall signal to generate a synchronization signal. The direct digital frequency synthesizer generates a modulating signal according to the synchronization signal. The first operating circuit receives a load current and generates a modulated signal according to the load current. The driving signal generator generates an original driving signal according to the synchronization signal. The second operating circuit generates a control signal according to the modulating signal and the modulated signal. The original driving signal is selectively outputted as the fan driving signal in response to the control signal.

Abstract: An operation clock generation circuit performs a calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.

Abstract: A frequency compensation apparatus includes a first counter setting a reference period using a main clock, a second counter sensing a change in the frequency of a sub clock using the reference period, and a frequency compensator providing a compensated frequency using information on the changed frequency of the sub clock. Related methods are also described.

Abstract: A frequency tunable signal source (100) with first (105) and a second (115, 315) oscillators, each of which outputs a signal at a fundamental frequency (f1, f2) and at least one signal at a harmonic frequency (f1?, f2?) and a mixer (120) with first (121) and second (122) input ports and an output port (124), and a control unit (110) which controls switches (S1, S2, S3, S4), by means of which two of said signals (f1, f2, f1?, f2?) are switchably connected to the first input port. The other two signals are switchably to the other input port, with one switch (S1, S2, S3, S4) for each signal (f1, f2, f1?, f2?). There is also comprised a third oscillator (125), with an output signal connected to a third input port (123) of the mixer (120). At least one of the oscillators (105, 115, 315, 125) is a VCO, a Voltage Controlled Oscillator.

Abstract: A dual mode frequency synthesizer circuit including: a DDS or PLL (204) for receiving an input clock (202) and generating an output clock (206), in a high resolution mode; and an RF switch (210) having its output (208) coupled to the output of the DDS or PLL, a first input (216) for receiving a first injection low phase-noise clock (F1), a second input (218) for receiving a second injection low phase-noise clock (F2), and a control input (222) for selecting one of the first or second injection low phase-noise clocks for a low phase-noise mode.

Abstract: A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter arranged to provide a shifted reference clock by changing phase of a frequency reference clock, and a time-to-digital converter (TDC) for producing a digital TDC output by quantizing a time difference between said RF clock and said shifted reference clock; wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.

Abstract: An apparatus and method for multiplying frequency of a clock signal are provided, wherein the apparatus provides an initial oscillator signal, compares the initial oscillator signal with a reference signal to generate a first control signal, selectively outputs one of at least one lower threshold value and at least one upper threshold value from a threshold value generation circuit to a clock output circuit according to at least the first control signal, and updates an output clock signal through a digital and logical module processing the comparison of the initial oscillator signal and the selected one of the at least one upper and lower threshold values and the comparison of the initial oscillator signal and a low level signal.

Abstract: Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.

Abstract: A frequency divider arrangement for providing a quadrature output signal with a quadrature output signal frequency, includes a signal source for providing a base signal with a base signal frequency at the output side. Further, the frequency divider arrangement includes a first integer number quadrature divider with a first divider ratio for receiving the base signal on the input side and for providing a first quadrature signal with a first quadrature signal frequency according to the first divider ratio of the first integer number quadrature divider.

Abstract: In order to output an accurate waveform in which quantization noise has been cancelled out, provided is a signal generating apparatus that outputs an output signal corresponding to a waveform data sequence expressing a waveform, the signal generating apparatus comprising a DA converting section that outputs an analog signal by sequentially performing digital/analog conversion on each piece of data included in the waveform data sequence, at a timing of a sampling clock; and a jitter injecting section that injects jitter decreasing a quantization noise component of the output signal, into the sampling clock supplied to the DA converting section.