Abstract: A jittering frequency control circuit and method for a switching mode power supply enlarge the uttering frequency range of the switching frequency of the switching mode power supply when the switching mode power supplier enters a frequency reduction mode, to improve the electro-magnetic interference of the switching mode power supply operating with the frequency reduction mode.

Abstract: A mechanical frequency generator has a first mechanical resonator and a second mechanical resonator and a circuit connected with the first and second mechanical resonators. The first and second mechanical resonators having substantially the same resonator frequency coefficients as a function of an environment of the first and the second mechanical resonators. The first mechanical resonator differing in size from the second mechanical resonator. The circuit adapted to generate a difference frequency signal responsive to the first and second mechanical resonator frequency signals and based on the first and the second predetermined resonant frequencies.

Abstract: Device for providing electrical signals with high immunity to noise. The invention develops a device for processing electrical signals (100) coming from a measurement sensor (60), said sensor (60) being subjected to noise disturbances caused by radio interference and lightning effects, such that said device uses a single current-loop cable (70), through which passes the electrical signal (100) encoded according to the signal time (Ta) and repetition time (Tr) of the current wave of said signal (100), such that said signal (100) contains an upper current state (10) and a lower current state (20) whose values are outside the decision window that activates a reading device (4) in the device, which reads the electrical signal (100) coming from the sensor.

Abstract: A method for dividing a frequency includes the steps of receiving a first signal having a first frequency as a clock input to a first digital counter and outputting a second signal as a clock input to a second digital counter having a higher counting capacity than the first counter. The output occurs when the first counter reaches a first number of count cycles. The method also includes generating a third signal having a high cycle and a low cycle, which are determined at least as a function of the first number of count cycles. Depending on a desired division ratio, the high and low cycles may also be a function of a second number of count cycles associated with the second counter. The third signal has a frequency lower than the first frequency.

Abstract: Here, an apparatus is provided. The apparatus comprises a first supply rail, a second supply rail, a first ambipolar transistor (which is coupled to the first supply rail at its drain and which receives a reference voltage at its gate), a second ambipolar transistor (which is coupled to the first supply rail at its drain and which receives an input signal at its gate), a current source (which is coupled between the sources of the first and second ambipolar transistors and the second supply rail), and an output circuit (which is coupled to drain of the first ambipolar transistor). In operation, the output circuit provides an output signal having a frequency that is about twice the frequency of the input signal.

Abstract: An integrated circuit 2 comprises a functional circuit 4, 6 which is arranged to operate in response to an operational clock signal having an operational clock frequency. To conserve power, the clock signal is distributed across the integrated circuit 2 at a distribution clock frequency which is less than the operational clock frequency. A clock converter 10 is provided to convert the distribution clock signal into the operational clock signal for controlling operation of the functional circuit 4, 6.

Abstract: A system timer including a divider unit configured to fractionally divide a first clock signal and output a second clock signal having an asymmetric duty ratio and an interrupt generation unit configured to count a cycle of the second clock signal and output an interrupt signal according to the count.

Abstract: A device (100) for generating an output signal (So) having substantially same or increased output frequency compared to an input frequency of an input signal (Si), the device (100) comprising: a bipolar transistor (102) having a base (B), a collector (C), and an emitter (E); a control unit (104) adapted for controlling application of the input signal (Si) to the base (B) and adapted for controlling application of a collector-emitter voltage between the collector (C) and the emitter (E) in a manner for operating the bipolar transistor (102) in a snap-back regime to obtain a non-linear collector current characteristic to thereby generate the output signal (So) having the substantially same or increased output frequency resulting from a steeply rising collector current.

Abstract: A clock dividing circuit includes a control logic unit and a flip-flop. The control logic unit outputs an enable signal and a data signal according to a clock signal and a division ratio. The flip-flop outputs a divided clock signal based on the clock signal, the enable signal and the data signal. The clock signal can be directly outputted as the divided clock signal through the flip-flop.

Abstract: Embodiments of the present invention include methods for wide bandwidth synthesizer circuits and methods. In one embodiment, the present invention includes a frequency synthesizer comprising a multiplexer and a band group selector. The multiplexer is coupled to receive a plurality of sinusoidal signals. Each sinusoidal signal has a unique frequency. The band group selector selects between a plurality of band groups. The band group selector is coupled to receive a first signal from the multiplexer. The multiplexer multiplexes between the plurality of sinusoidal signals and provides the first signal. The band group selector includes a band mixer. The band mixer mixes the first signal with a band signal having a band frequency. The band signal corresponds to a band group selected from the plurality of band groups. The band group selector provides a transmitter mixer signal and a receiver mixer signal.

Abstract: A portable terminal device includes a supplying unit for supplying, to a CPR, an operating frequency of a clock signal used to operate the CPU, a setting unit for setting one clock level out of a plurality of clock levels assigned with the operating frequency in accordance with an operating state of the CPU and changing an operating frequency stepwise at the clock levels to set the clock level of the operating frequency, a control unit for controlling the operating frequency supplied to the CPU at the clock levels based on settings made by the setting unit, and an input accepting unit for accepting a key input. If the input accepting unit accepts the key input, the setting unit sets the clock level to a predetermined level irrespective of an operating state of the CPU.

Abstract: A system includes at least a first array connected to a second array. The first array includes an odd number, greater than one, of unidirectionally-coupled non-linear first array elements. The second array includes an odd number, greater than one, of unidirectionally-coupled non-linear second array elements. The second array elements are unidirectionally-coupled in a direction opposite the coupling direction of the second array elements. The first array is configured to receive an input signal and down-convert the input signal. The second array is configured to receive the down-converted input signal, further down-convert the down-converted input signal, and output a down-converted output signal. The down-converted output signal is down-converted to a multiple of the frequency of the input signal proportional to the number of arrays of the system. The system may operate at frequencies greater than 1 GHz and may be contained in a microchip or on a printed circuit board.

Abstract: A receiving method and apparatus is disclosed. The method comprising steps of: receiving a plurality of data according to a symbol clock signal, and reading out the plurality of data according to a first clock signal and generating a water level; receiving a second clock signal so as to generate a third clock signal, and adjusting the speed of the third clock signal according to the water level; determining a sampling frequency of the plurality of data according to a data amount of the plurality of data during a unit time period or parameters of the plurality of data; and dividing the third clock signal by a dividing value or multiplying the third clock signal by a multiplying value so as to obtain the first clock signal and adjust the water level by a clock generator.

Abstract: A frequency error detecting circuit includes: an oscillator; a frequency converting unit for a received signal on the basis of the oscillation output and output the received signal; a time-to-frequency converting unit configured to convert the output of the frequency converting unit into a frequency domain signal; a frequency shift determining unit configured to determine presence or absence of a frequency shift between an output frequency of the frequency converting unit and a predetermined carrier frequency; and a control unit configured to repeat frequency conversion processing and time-to-frequency conversion processing while controlling an oscillation frequency of the oscillator on the basis of a determination result of the frequency shift determining unit and cause the output frequency of the frequency converting unit to converge on a predetermined value to thereby detect a frequency error between the frequency of the received signal and the predetermined carrier frequency.

Abstract: It is an object of the present invention to provide a sampling mixer and a receiver, capable of optimizing a sampling rate of an output signal in response to a fractional band of a modulation band with respect to an RF frequency of the received signal. A sampling mixer of the present invention, includes a history capacitor 6 for integrating a received signal that is converted in terms of current in a continuous time, rotation capacitors 7 to 14 for repeating an integration and a discharge of an input signal, a digital controller 104 for controlling integration periods of the rotation capacitors 7 to 14, and a controlling portion 105 for controlling discharges of the rotation capacitors 7 to 14, wherein the number of the rotation capacitors 7 to 14 connected at a time to a buffer capacitor 15 is switched in answer to a fractional band of the modulation band with respect to a RF frequency.

Abstract: An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution manager coupled to the system controller. The system controller monitors a processing demand in a processing system. The clock domain manager provides one or more clock frequencies and, in response to the processing demand, switches between a first set of clock frequencies and a second set of clock frequencies without halting the processing system. The power distribution manager provides one or more operating voltages and, in response to the processing demand, switches between a first set of voltages and a second set of voltages without halting the processing system.

Abstract: A measurement circuit that has particular application for detecting a high impedance measurement signal from a liquid water sensor. The measurement circuit includes a high impedance resistance-to-frequency conversion circuit that is coupled to the sensor and receives a resistance signal therefrom. The resistance-to-frequency conversion circuit includes an oscillator that converts the resistance signal to a representative frequency. The measurement circuit also includes a frequency-to-voltage conversion circuit that receives the frequency signal from the resistance-to-frequency conversion circuit, and converts the frequency signal to a representative voltage that provides an indication of water on the sensor.

Abstract: In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.

Abstract: The present invention discloses a mixer comprising with an input stage (100) for receiving and amplifying input signals (VINP, VINN) and an output stage (300) for outputting output signals (Voutp, Voutn). A switching stage (200) is coupled between the input stage (100) and the output stage (300), the switching stage (200) mixing the amplified input signals with a local oscillator signal (vlop, vlon) to produce the output signals (Voutp, Voutn) at the output stage (300). An RC circuit (cop, rop; con, ron) is connected to the output stage (300) and adapted to move the pole of the output signals.

Abstract: A circuit includes: a first line to which input and output signal terminals are connected; a first transistor having a first terminal connected to the first line, a second terminal connected to a ground potential, and a control terminal supplied with a first oscillation signal, the first transistor outputting the first signal and its harmonic component; a second transistor having a first terminal connected to the first line, a second terminal connected to the ground potential, and a control terminal supplied with a second oscillation signal, the second transistor outputting the second signal and its harmonic component; a first harmonic generator connected to the control terminal of the first transistor and generates a harmonic component including the harmonic component by the first transistor; and a second harmonic generator connected to the control terminal of the second transistor and generates a harmonic component including the harmonic component by the second transistor.

Abstract: A synchronizing apparatus, which controls, by a PLL circuit, a sampling clock to be used to sample input data and synchronizes a phase of the sampling clock with a target phase that is desirable for sampling the input data, includes: phase error detection means for detecting a phase error from sampling data and the sampling clock, the sampling data being sampled from the input data at timing of the sampling clock; frequency error detection means for detecting, based on a differential coefficient obtained as a result of detecting the phase error, a frequency error; and frequency correction means for correcting a frequency of the sampling clock such that the detected frequency error becomes close to zero by adding a frequency correction value to an integral term of a loop filter of the PLL circuit, the frequency correction value being calculated based on the frequency error.

Abstract: A device (100) for generating an output signal (So) having substantially same or increased output frequency compared to an input frequency of an input signal (Si), the device (100) comprising: a bipolar transistor (102) having a base (B), a collector (C), and an emitter (E); a control unit (104) adapted for controlling application of the input signal (Si) to the base (B) and adapted for controlling application of a collector-emitter voltage between the collector (C) and the emitter (E) in a manner for operating the bipolar transistor (102) in a snap-back regime to obtain a non-linear collector current characteristic to thereby generate the output signal (So) having the substantially same or increased output frequency resulting from a steeply rising collector current.

Abstract: A frequency synthesizer is provided, including a voltage-controlled oscillator (VCO), a frequency prescaler, a divide-by-2.5 circuit, and a selector. The VCO determine the frequency of a first signal according to an input voltage. The frequency prescaler determines the frequency of a second signal to be the frequency of the first signal divided by 3, 3.5, or 4 according to a first selection signal, and the frequency prescaler also determines the frequency of a third signal to be the frequency of the first signal divided by 6, 7, or 8 according to the first selection signal. The divide-by-2.5 circuit generates a fourth signal, wherein the frequency of the fourth signal is the frequency of the first signal divided by 2.5. The selector selects one of the second signal, the third signal, and the fourth signal as a fifth signal according to a second selection signal.

Abstract: A band converted signal generator includes a low range characteristic application section (16) as a component emphasis means emphasizing only one or more specific frequency components selected from among frequency components of an input signal; and a low pass filter (17) as a component extraction means extracting a signal component of a desired frequency band from an output signal supplied from the low range characteristic application section (16). A band extender (1000) includes the above-mentioned band converted signal generator, and an adder (15) adding the input signal, a certain frequency band of which is suppressed, and a signal including at least one component generated within the certain frequency band which is suppressed.

Abstract: A data transmission network having at least two devices to transmit and receive data with the devices connected via a passive transmission device so that the data is transmitted between the devices using the passive transmission device. Each of the devices includes a converter to control data transmission using the passive transmission device.

Abstract: A semiconductor apparatus includes a signal source 7 that outputs a signal of predetermined frequency, a frequency divider 15 that receives the output signal of the signal source and is capable of switching the output signal to two or more frequency division ratios, a delta-sigma modulator 16 that controls the frequency division ratio of the frequency divider, and a bandpass filter 17 that receives an output of the frequency divider. The frequency of the input signal of the frequency divider is divided by the frequency division ratio controlled by the delta-sigma modulator, and quantization noise appearing in the output of the frequency divider generated by the delta-sigma modulator is attenuated with the bandpass filter. The semiconductor apparatus easily can convert a signal output by a single signal source to a signal of predetermined frequency and supply a plurality of signals of predetermined frequency using a simple configuration with reduced chip size.

Abstract: A signal receiving device is provided which can prevent the imbalance occurring between in-phase and quadrature signals. A polarity of a local oscillator output signal to be outputted from a local oscillator 13 is switched by a polarity switching unit 14 in a time division way. Each of signals outputted from the polarity switching unit 14 is frequency divided by a frequency divider 16. The frequency-divided local oscillation signal is supplied to a mixer 34. Frequency conversion of a receiving signal is performed by the mixer 34 which receives the signal and local oscillation signal to demodulate received data.

Abstract: Provided is a frequency conversion mixer. The frequency conversion mixer includes a transconductance stage, a switching stage, a load stage, a current bleeding circuit, and a bias stage. The transconductance stage receives an RF signal, and outputs a current corresponding to a voltage of the RF signal. The switching stage switches the current which is outputted from the transconductance stage in response to a local oscillation signal, for frequency conversion the RF signal into an intermediate frequency (IF) signal. The load stage is connected between the switching stage and a supply voltage terminal. The current bleeding circuit is connected parallel with the switching stage, especially, embodying inverter structure with transconductance stage to get not only current bleeding effect but also current reuse effect, and one resonant inductor for reducing noise which is generated in parasitic capacitance at node between transconductance stage and switching stage.

Abstract: The present invention relates to a device and a method for educing harmful effects to people of a first alternating electromagnetic field that is characterised by a first frequency. According to the invention, the device comprises extraction means for extracting electric power from the first alternating electromagnetic field and transmission means for transmitting a second alternating electromagnetic field that is characterised by a second frequency. During operation, the transmission means are supplied with the electric power extracted by the extraction means, and the first and the second frequency are different.

Abstract: A method for controlling a supply current for a circuit comprises setting a target value of a quantity related to a supply current, said target value being different from a presently established value of the quantity, and adjusting the quantity until a value of the quantity corresponds to the target value. A method for controlling a supply current to a plurality of circuit blocks comprises providing a plurality of partial supply currents to the plurality of circuit blocks, setting at least one target value of a quantity related to at least one of the partial supply currents, checking whether a predetermined condition which depends on the at least one set target value is achieved, and if the predetermined condition is not achieved, changing at least one among the at least one target values and the at least one partial supply currents to achieve the predetermined condition.

Abstract: A semiconductor device that includes transmitter circuits and receiver circuits that share a common data line and method is disclosed. Each transmitter circuit may include a frequency modulator that receives a stream of data and provides a frequency modulated data output at a predetermined carrier frequency. Each receiver may include a band pass filter that allows a corresponding frequency modulated data output from a corresponding transmitter circuit to pass through to a demodulator while essentially excluding the other frequency modulated data. In this way, a plurality of transmitter circuits can simultaneously transmit data with each one of the plurality of transmitter circuits transmitting data to a predetermined receiver circuit.

Abstract: A system for testing radio frequency (RF) communications of a device capable of such communications is provided. The system includes a chamber for isolating the device from RF interference, an antenna that is suitable for RF communications with the device wherein the antenna is capable of communications over a range of frequencies, the antenna being located within the chamber, and a digital communication link for providing non-RF communications with the device.

Abstract: Second-order intermodulation distortion can be suppressed in a direct conversion radio receiver having a downconversion mixer by calibrating resistors and a current source in the mixer. A test signal is applied to the signal inputs of the mixer transconductor. The resistances of first and second variable resistor circuits connected to the switching quad are then varied while also varying a variable current source. Each time the resistances and current are set to new values, the resulting mixer output signal is measured. When the measured output signal is determined to be at a minimum, the variable resistors and current source are left at the corresponding values to which they have been set. Adjusted in this manner, the current source counteracts the DC offset voltage at the mixer output.

Abstract: An automatic adjustment circuit comprises a replica (1) constituted of either a circuit block of a portion of a filter body (3) or a combination of the circuit block, and fed with a reference signal (2) from the outside, for outputting signals having a phase delays of 90 degrees and 180 degrees with respect to the reference signal (2), and an integrating comparator (4) fed at its input terminal with an output signal, as having a phase delay of 180 degrees, of the replica (1) and the reference signal (2), and at its clock terminal with an output signal, as having a phase delay of 90 degrees, of the replica (1), and having an output terminal connected with a capacity (C1) and a frequency characteristic adjusting terminal of the replica (1). The automatic adjusting circuit is characterized in that the integrating action of the integrating comparator (4) is performed across the two high/low states of the input signal.

Abstract: A novel clock splitter that has a local internal clock frequency-divider is presented. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses in the C clock to generate a slower C clock signal that is slower than the oscillator clock; and a B/C clock order logic, wherein the B/C clock order logic phase shifts the C clock relative to a B clock. The clock frequency-divider may selectively suppress pulses in the B clock to generate a slower B clock signal. The slower B and C clock signals may have a same or different frequency. In one embodiment, the clock splitter is located at a terminal leaf of a clock tree.

Abstract: Implementations related to circuits including an oscillator and a switch-mode DC/DC converter are presented herein.

Abstract: Electro-mechanical oscillating devices designed to convert the frequency of electrical signal(s) and methods associated with the same are described. One example of such a frequency converting device is a mixer.

Abstract: A system for generating a frequency reference signal comprising an oscillator, a direct digital synthesizer coupled to the oscillator and configured to receive a signal output from the oscillator, a digital to analog converter coupled to the direct digital synthesizer and configured to receive a sampled signal from the direct digital synthesizer and to convert the sampled signal to an analog waveform, and a bandpass filter coupled to the digital to analog converter and configured to select an aliased output signal from the digital to analog converter at a Nyquist zone other than a first Nyquist zone and to output the frequency reference signal.

Abstract: A frequency synthesizer includes first and second frequency dividers for receiving and frequency-dividing a signal generated by a voltage-controlled oscillator, a frequency mixer for mixing output signals of the first and second frequency dividers, and a third frequency divider for receiving and frequency-dividing a signal having one frequency of two frequencies that are output by the frequency mixer. The first, second third and frequency dividers and the frequency mixer are provided in a feedback loop within a PLL circuit between the voltage-controlled oscillator and the phase comparator. The phase comparator has a first input terminal to which a signal to which a signal that is output by the third frequency divider is input and a second input terminal to which a reference clock signal that is output by a reference signal generator is input. A loop filter supplies the voltage-controlled oscillator with a voltage that is based upon result of the phase comparison by a phase comparator.

Abstract: A signal frequency change circuit is presented. The signal frequency change circuit includes a delay line, a detector, a controller, a multiplexer, and an output unit. The delay line delays a clock signal by a first delay time corresponding to a delay control signal to generate a delay signal and delays the clock signal by a second delay time shorter than a first delay time to generate a pre-frequency change clock signal. The detector generates a phase locked completion signal. The controller sequentially shifts the delay control signal and a multiplexing control signal. The multiplexer selects and outputs one of the pre-frequency change clock signals. The output unit generates a frequency change clock signal.

Abstract: An embodiment is directed to a zero IF down converter circuit. The circuit comprises a voltage-to-current converter, a mixer, and a suppression circuit. The voltage-to-current converter converts an RF voltage signal to an RF current signal. The mixer changes the frequency of the current signal to a lower frequency current signal. The suppression circuit removes a lower frequency distortion component from the RF current signal before sending the RF current signal to the mixer.

Abstract: A frequency-control unit is used for controlling an external controllable reference-frequency source. The frequency-control unit includes a filter unit with a controllable filter parameter, which is configured to derive, using the filter parameter, from a frequency-error signal a frequency-control signal for minimizing the frequency error of the reference frequency; and a correlation unit, which is configured to determine from frequency errors of the reference frequency at different points in time a correlation measure indicative of a correlation between the frequency errors at the different points in time. The frequency-control unit is configured to adapt the controllable filter parameter of the filter unit in dependence on the determined correlation measure. The value of the filter parameter can depend also on a receiver path strength, such as an RSCP value.

Abstract: A digitally controlled frequency generator includes an oscillator module for generating a first clock signal having an oscillating frequency, a programmable control module operable so as to generate a control signal corresponding to a desired frequency, and a direct digital frequency synthesizer coupled to the oscillator module and the programmable control module for receiving the first clock signal and the control signal therefrom, and for generating a second clock signal having the desired frequency based on the first clock signal from the oscillator module and the control signal from the programmable control module.

Abstract: A highly linear and very low-noise down-conversion mixer for extracting weak signals in the presence of very strong unwanted signals is disclosed. Aspects of an embodiment may include a source follower circuit in a transmitter front end of a mobile terminal. The source follower circuit may receive RF signals prior to the RF signals being amplified by a power amplifier for transmission. The RF signals may comprise in-phase and quadrature components. The source follower circuit may generate output RF voltage signals, and communicate the output RF voltage signals to a switching circuit via a coupling capacitor. The switching circuit may down-convert the communicated output RF voltage signals to generate differential baseband signals. The capacitance of the coupling capacitor may be changed to change gain and/or linearity of the differential baseband signals. Each of the differential baseband signals may be low-pass filtered to attenuate higher frequencies.

Abstract: A method of generating an output signal from an input signal includes a step of generating a set of n signals, n being an integer greater than or equal to 3, by generating a signal for each integer i such that 0?i?(n?1), each signal within the set having the same frequency and approximately equal amplitude and a phase equal to (360/n)i degrees. The method also includes a step of inputting each of the set of n signals to a gate terminal of a corresponding one of a set of n transistors. Each of the transistors has a source terminal electrically connected to a common voltage drain and each of the transistors has a drain terminal electrically connected to a coupling. The coupling is electrically connected to a common voltage source. The output signal at the coupling has a frequency equal to the frequency of the input signal multiplied by n.

Abstract: Techniques for minimizing signal loss in transit are described. Data signals lose their strengths while traveling across conductive passages such as cooper wire, cooper strip, Printed Circuit Board (PCB), etc. There are two major factors that affect the signal loss: the distance and the speed. To minimize signal loss while maintaining higher rate data signals for I/O, substantially lower rate data signals are used in transit between two interfaces over a signal path.

Abstract: To provide a frequency conversion device which uses a magneto-resistive device and thereby can correspond to a Si-based MMIC and a GaAs-based MMIC. A frequency conversion apparatus according to the present invention includes: a frequency conversion device made of a magneto-resistive device including a magnetic free layer, an intermediate layer, and a magnetic pinned layer; a magnetic field applying mechanism for applying a magnetic field to the frequency conversion device; a local oscillator for applying a local oscillation signal to the frequency conversion device; and an input terminal electrically connected to the frequency conversion device, and used to input an external input signal.

Abstract: A frequency divider including at least one frequency divider cell having an adjustable circuit configuration which may be selected adaptively according to properties of an oscillator signal to be frequency-divided in the frequency divider. Accordingly, the circuit configuration of the frequency divider may be changed on the fly during the operation.

Abstract: A microprocessor control circuit continuously monitors core logic operating temperature and detects it has risen above a first temperature and responsively iteratively controls a system voltage source to output a next lower one of its N output voltage levels and controls clock generation circuitry of the microprocessor to output a lower one of its M core clock signal frequencies as necessitated by a transition to the next lower output voltage level until the temperature drops below the first temperature. The control circuit detects that the temperature has dropped below a second temperature and responsively iteratively controls the voltage source to output a next higher output voltage level and controls the clock generation circuitry to output a higher core clock signal frequency as permitted by the next higher output voltage level until the operating temperature rises above the second temperature. The M frequencies comprise a highest, lowest, and plurality of intermediate frequencies.

Abstract: A frequency error detecting circuit includes: an oscillator; a frequency converting unit for a received signal on the basis of the oscillation output and output the received signal; a time-to-frequency converting unit configured to convert the output of the frequency converting unit into a frequency domain signal; a frequency shift determining unit configured to determine presence or absence of a frequency shift between an output frequency of the frequency converting unit and a predetermined carrier frequency; and a control unit configured to repeat frequency conversion processing and time-to-frequency conversion processing while controlling an oscillation frequency of the oscillator on the basis of a determination result of the frequency shift determining unit and cause the output frequency of the frequency converting unit to converge on a predetermined value to thereby detect a frequency error between the frequency of the received signal and the predetermined carrier frequency.