Abstract: The present invention relates to improved ADC buffers and AFEs for high frequency applications, such as VDSL. The present invention can also be programmably configured for other xDSL applications. In this regard, a buffer circuit for a high-bandwidth analog-to-digital converter (ADC) includes a first unity-gain buffer configured to receive an analog input signal. The first unity-gain buffer includes a MOSFET differential amplifier with a current mirror load and a transient-reduction network electrically interconnected with the MOSFET differential amplifier and configured to reduce transient energy emitted by the ADC. The buffer circuit also includes a second unity-gain buffer cascaded to the first unity-gain buffer and configured to provide the analog input signal from the first unity-gain buffer to the ADC.

Abstract: A circuit for reducing leakage current in an ESD overvoltage protection circuit is described. Specifically, the circuit uses a semiconductor controlled rectifier or a semiconductor controlled switch to minimize the leakage.

Abstract: A substrate pump circuit and method for I/O ESD protection including NMOS fingers connected to the interconnection between an I/O pad and an internal circuit comprises a MOS device connected to the interconnection between the I/O pad and the internal circuit and the substrate under the control of a switch to turn it on to conduct a pumping current through the substrate resistor when the I/O pad is under ESD stress, so as to pull up the potential of the substrate adjacent to the NMOS fingers, resulting in the reduction of the triggering voltage of the NMOS fingers.

Abstract: Electrostatic discharge protection is provided to an integrated circuit in which, for a particular embodiment, the integrated circuit comprises a switched capacitor circuit having a plurality of groups of voltage reference input ports; and a plurality of electrostatic discharge resistors coupled to a pad, wherein each electrostatic discharge resistor is coupled to a unique group of voltage reference input ports.

Abstract: An off-leak current cancel circuit includes an input protection circuit having a first protection transistor connected between a terminal and a high power potential, and a second protection transistor connected between the terminal and a low power potential. The first and second protection transistors flow first and second off-leak currents. A current cancel circuit has a first monitor transistor for flowing a third off-leak current that is smaller than the first off-leak current, and a cancellation circuit for flowing the first off-leak current to the low power potential responsive to the third off-leak current. A current providing circuit has a second monitor transistor for flowing a fourth off-leak current that is smaller than the second off-leak current, and a providing circuit for providing the second off-leak current from the high power potential responsive to the fourth off-leak current.

Abstract: Systems and methods are disclosed for localized electrostatic discharge protection of integrated circuit input/output pads. The localized clamp is isolated from the main supply voltage clamp and coupled to the input/output pad through low-capacitance diodes.

Abstract: Systems and methods are disclosed for localized electrostatic discharge protection of integrated circuit input/output pads. The localized clamp is isolated from the main supply voltage clamp and coupled to the input/output pad through low-capacitance diodes.

Abstract: Described is an apparatus and a method for pulling an integrated circuit I/O pad to a known state and providing a current path between the pad and a source of potential during periods when an I/O voltage is likely to be floating. At least one I/O transistor coupled between the I/O pad and a source of potential is provided. Also provided is a combinatorial circuit connected to the I/O transistor to turn on the I/O transistor during periods that the I/O voltage is likely to be floating.

Abstract: A semiconductor device malfunction preventive circuit S is disposed in a macrocell logic cell 1 of a semiconductor device 50 used in an electronic device 100. A signal in an output pin 3 or in a signal line 6 is returned to the semiconductor device malfunction preventive circuit S as a pin feedback and monitored. When a predetermined state is detected, an abnormality detecting signal SIGAB for resetting the operation of the electronic device 100 is outputted.

Abstract: An ESD protection circuit utilizes a trigger network to allow the user to select the breakdown voltage of an avalanche transistor. By implementing the trigger network as a string of diodes coupled between the collector and base of the avalanche transistor, the trigger voltage can be programmed between BVCEO and BVCBO by adjusting the number of diodes. When the voltage across the trigger network reaches a predetermined value at which the diodes are conducting under forward biased conditions, but the transistor is below BVCBO, base charge supplied to the transistor caused the transistor to avalanche. A base-emitter resistor prevents false triggering by removing leakage charge from the base of the transistor, and another resistor coupled in series with the base of the transistor limits the removal of charge, thereby causing the avalanche to be self-sustaining once initiated by the trigger network.

Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.

Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.

Abstract: In an over current protection circuit of a semiconductor switching device, a change in a main current of a semiconductor switching device with respect to a change in the detected voltage of the resistor for current detection connected to the current detection terminal of the semiconductor switching device becomes gentle in the vicinity of a location where the semiconductor switching device is turned off. With the provision of the current protection circuit, the variation in the cut-off level of the over current with respect to the variation in the detected voltage of the resistor for current detection connected to the current detection terminal of the semiconductor switching device is suppressed so that the semiconductor switching device can be protected from being breakdown due to the over current flow.

Abstract: A high-frequency integrated transistor module includes a bipolar transistor having at least one emitter finger, which is internally connected in series with a resistor to provide a DC current path for the circuit, and is internally connected in series with a capacitor to provide an RF current path for the module separate from the DC current path. The capacitor may be coupled to an RF ground connection, and the value of the capacitor may be selected to resonate with the value of the RF ground connection inductance in order to provide gain enhancement at a selected operating frequency range. In order to provide gain enhancement over a broader frequency bandwidth, two or more emitter fingers can be connected in series with respective capacitors of different values in order to provide at least two RF current paths having different resonant frequencies.

Abstract: An ESD (electrostatic discharge) protective circuit is connected to a node which is branching a high frequency signal input/output line connected to a high frequency input/output pad. A high frequency internal circuit is connected as a succeeding stage via a DC blocking capacitor such as a PIP (Polysilicon Insulator Polysilicon) capacitor, MIM (Metal Insulator Metal) capacitor, or comb capacitor to implement high ESD tolerability without significantly degrading high frequency characteristics.

Abstract: An ESD protection circuit protecting an internal circuit from ESD damage. The internal circuit is connected to a voltage interface and powered by a first and second power supply. A first signal with a first amplitude received from a pad is transformed to a second signal with a second amplitude by the voltage interface. The second signal is input to the internal circuit. A first and second diode are serially but inversely connected between the pad and the first power supply.

Abstract: A protection device includes a switching transistor (M11), connected between the gate of the output transistor (TS1) and ground, and a control circuit (CM), connected to the gate of the switching transistor (M11), which are capable of ensuring that the switching transistor (M11) is off when there is no electrostatic discharge at the drain of the output transistor (TS1) and capable of turning the switching transistor (M11) on when there is an electrostatic discharge at the drain of the output transistor (TS1).

Abstract: A method for reducing noise in an I/O system has been developed. The method includes powering up the I/O supply and activating or inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the I/O power supply, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.

Abstract: The present invention provides a buffer for voltage ringing and overshooting suppression that improves the ESD protection. The buffer comprises a transistor and a resistance modulator. The resistance modulator is connected in series between an IC pad and a power node. The resistance modulator provides a first resistance during normal circuit operation, and provides a second resistance that is lower than the first resistance during an ESD event.

Abstract: Disclosed is a circuit for driving a gate of an IGBT (insulated gate bipolar transistor) inverter. The present invention includes a first IGBT of which collector is connected to a DC voltage, a second IGBT of which collector is connected to an emitter of the first IGBT, wherein an output signal is outputted from a connection point between the collector of the second IGBT and the emitter of the first IGBT, and of which emitter is connected to a ground, first and second driving circuits supplying gates and the emitters of the first and second IGBTs with DC driving voltages, respectively, through first and second gate resistors, and first and second noise interruption circuits connected between the gates-emitters of the first and second IGBTs and the first and second driving circuits, respectively, so as to interrupt noises.

Abstract: Electronic devices having voltage variable capacitances are formed using CMOS fabrication processes. The devices are capable of decreasing noise of one polarity and amplifying noise of the opposite polarity. For one embodiment, a transistor having a gate oxide layer is operated in the depletion region to form a capacitive device. In an alternate embodiment, a CMOS transistor having an n-type substrate, all p-type polysilicon gate, an n-type source and drain, and a gate oxide layer is operated in the depletion region to form a capacitive device. For one embodiment, the disclosed devices are used in circuits for decoupling multiple voltage power supplies. In an alternate embodiment, the devices are used in circuits for damping power supply grid network resonances. In still another alternate embodiment, the devices are used in circuits for decoupling noise in power supply signals operating at low voltages.

Abstract: An integrated circuit including a transistor having a first electrode coupled to an output bond pad and a second electrode coupled to a reference potential, such as ground bond pad. A degeneration device is coupled between the second electrode and the reference potential. A diode is coupled between the second electrode of the transistor and the reference potential with the anode of the diode coupled to the second electrode reference potential and the cathode of the diode coupled to the reference potential for an NPN transistor.

Abstract: A MOS-type power device having a drain terminal, a source terminal, and a gate terminal; and a protection circuit having a first conduction terminal connected to the gate terminal, via a diffused resistor, and a second conduction terminal connected to the source terminal. The protection circuit has a resistance variable between a first value and a second value according to the operating condition of the power device. In a first embodiment of the protection circuit, an ON-OFF switch made by means of a horizontal MOS transistor has a control terminal connected to the drain terminal of the power device. In a second embodiment of the protection circuit, the ON-OFF switch is replaced with a gradual-intervention switch made by means of a P-channel JFET transistor having a control terminal connected to the gate terminal of the power device.

Abstract: A multichip configuration in which a plurality of semiconductor chips in a module are connected together in such a way that the voltage drop across internal gate resistors is minimized, in order in the event of a short circuit to prevent the short circuit current rising with the gate voltage.

Abstract: An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. Consequently, digital active voltage regulator circuit smooths the local power supply voltage by greatly ameliorating the ripple voltages associated with parasitic inductances and resistances. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits.

Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.

Abstract: A noise limiter of a semiconductor integrated circuit device includes a diode-connected N channel MOS transistor between a bus line and a line of a potential lower than the power supply potential by a threshold voltage, and a diode-connected P channel MOS transistor between a line of a potential higher than the ground potential by a threshold voltage and the bus line. The potential of the bus line is limited between the level of the power supply potential and the ground potential, so that the noise level of the bus line is reduced.

Abstract: An ESD clamping circuit arranged in a darlington configuration and constructed from SiGe or similar type material. The ESD clamping circuit includes additional level shifting circuitry in series with either the trigger or clamping device or both, thus allowing non-native voltages that exceed the BVCEO of the trigger and/or clamp devices.

Abstract: In an ESD protection circuit for an analog bipolar circuit, the avalanche breakdown voltage of a reverse-coupled NPN BJT acting as an avalanche diode is adjusted to comply with breakdown voltage and latchup requirements by including a resistor between the base and collector of the BJT.

Abstract: A digital driver circuit with one or more CMOS inverters intended as input stages, whereby for the MOS FETs of the inverters the channel width/length (W/L) ratio increases from stage to stage. The digital driver circuit includes an intermediate stage with two further CMOS inverters, connected between a supply voltage Vcc and ground. The driver circuit also includes an output stage having two MOS FETs with the drain terminals of both the MOS FETs of the output stage connected both to each other and to the output of the circuit, the W/L ratio of both MOS FETs exceeding that of the MOS FETs of the intermediate stage. The switch-over of the two MOS FETs of the output stage, occurring with changes of the digital input signal at the input of the circuit, is offset in time with respect to each other, thereby reducing current peaks.

Abstract: An apparatus for finely adjusting the input capacitance of a semiconductor device and a method of fabricating the apparatus are disclosed. The invention adjusts finely the input capacitance without increasing a layout area of the device by using a capacitor constructed with a poly layer/device isolation layer/P-type substrate. The poly layer is formed on an unnecessary space provided by the device isolation layer under an input pad.

Abstract: A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the low potential side power supply terminal, and an internal circuit to which power is supplied from the first and second wirings. Further the semiconductor device is provided with a first and a second resistance elements whose one end is connected to a first node, a first protection element having a first terminal connected to the first wiring and a second terminal connected to the other end of the first resistance element, a second protection element having a third terminal connected to the other end of the second resistance element and a fourth terminal connected to the second wiring, and a third protection element having a fifth terminal connected to the first wiring and a sixth terminal connected to the second wiring.

Abstract: An electrostatic discharge protective circuit can receive a pre-stage driver output and involve a first PMOS transistor, a first NMOS transistor and a second NMOS transistor and all connect in series. More particularly, a source region of the first PMOS transistor connects to a system power source; and a drain region connects to a conductive pad, and a gate receives the pre-stage driver output. A gate of the first NMOS transistor connects to a first node A, a gate of the second NMOS transistor connects to a third node C and a source region connects to a grounded node. The third node C also can receive the pre-stage driver output. There is a first resistor between the first node A and the system power source. There is a second PMOS transistor in between the first node A and the third node C and connect with two source/drain regions. And the substrate of the second PMOS transistor also connects with the first node A. Also, a gate of the second PMOS transistor connects with a second node B.

Abstract: A ramp loading circuit for slowing current change in a circuit block. The circuit may include a plurality of load circuits placed in parallel with the circuit block and a control circuit. Each load circuit may provide a path for current flow when the load circuit is activated. Each load circuit may also be configured to allow a gradual decrease in current flow through the path when the load circuit is deactivated. The control circuit may be configured to deactivate each load circuit before the circuit block enters the sleep mode.

Abstract: An ESD protection circuit layout. The ESD protection circuit layout has a first ESD protection device, a second ESD protection device, a first CDM ESD protection device, a second CDM ESD protection device, a first charge flow prevention device, a PMOS transistor, an input resistor, an NMOS transistor, a second charge flow prevention device and a substrate resistor. Charges within an integrated circuit device are discharged through a discharging loop comprising of the first CDM ESD protection device and the second CDM ESD protection device. Ultimately, the integrated circuit device is protected against CDM ESD and electrical latch-up within the integrated circuit is also minimized.

Abstract: A circuit in accordance with the invention includes an output driver, where the output driver includes a pull-up device and a pull-down device, the pull-up device having a first control terminal coupled with an RC-timer so as to bias the pull-up device on in response to an electrostatic discharge (ESD) event, and the pull-down device having a second control terminal coupled in the circuit so as to be in a substantially indeterminate state during said ESD event.

Abstract: An importance matching circuit for a semiconductor memory device includes an impedance detector for generating a voltage divided by a medium resistance value between a maximum resistance value and a minimum resistance value and an external resistance during a predetermined cycle as a first comparison voltage, and for generating a voltage divided by a resistance value varied in response to a counting output signal and the external resistance after the predetermined cycle as the first comparison voltage; a first comparator for comparing the first comparison voltage with a reference voltage to generate a first comparing output signal; a second comparator for comparing the first comparison voltage with the reference voltage to generate a second comparing output signal; a counter for generating the counting output signal in response to the first comparing output signal; and a plurality of output drivers for establishing an initial resistance value in each of the output drivers in response to the second comparing o

Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.

Abstract: A shunt and shunt control circuit are connected to the wires of an on-chip terminated I/O bus. Each instance monitors the wire that it is connected to. If the wire has been pulled low by any device on the bus, the circuit does nothing. If, however, the wire was not pulled low, then current is shunted from the termination voltage supply to ground. The turn on and turn off rates for this shunt are matched to the ramps of current through the termination impedance of the bus. This makes the variability in current drawn from the termination voltage supply less data dependent.

Abstract: An offset cancel circuit for an operational amplifier comprises a capacitive element for storing a voltage to be amplified by an operational amplifier section and containing an offset, and for feedback-controlling a voltage value of the operational amplifier section based on the stored voltage, and switching elements for switching operation between the storage of the voltage in the capacitive element and the feedback control based on the value of the voltage stored in the capacitive element. The capacitive element and the switching elements can be used to cancel accurately an offset in the operational amplifier section without increasing the gate areas of transistors in the operational amplifier section.

Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.

Abstract: A stress-driver circuit for providing a constant voltage (Vce) and a constant current (I=Vin/R) to a bipolar transistor under test. The circuit includes a power source, an op-amp, a FET, and the bipolar transistor. The power source is connected to the bipolar transistor collector. The op-amp has a positive input biased at input voltage (Vin) and a negative input having a feedback loop connected to the bipolar transistor emitter. The op-amp output is connected to the FET gate, the FET drain is connected to the power supply, and the FET source is biased to ground through a first resistor and connected to the base of the bipolar transistor. The second resistor is connected at one end to the bipolar transistor emitter and biased to ground at the other end. An automatic trip circuit may be provided to cut off power to the bipolar transistor if the current at the bipolar transistor collector exceeds a predetermined value.

Abstract: The reliability and operability of semiconductor devices is improved using a circuit arrangement that protects the device against malfunction and harm during operation. According to an example embodiment of the present invention, a semiconductor device includes a protection circuit that is adapted to discharge excess current and/or voltage in response to the voltage level at an input pad and to the operating condition of the device. The circuit protection circuit is configured to a first configuration during a power-up mode and to a second configuration during a power-down mode. When the voltage at the input pad reaches a selected threshold, the input voltage is discharged.

Abstract: A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the low potential side power supply terminal, and an internal circuit to which power is supplied from the first and second wirings. Further the semiconductor device is provided with a first and a second resistance elements whose one end is connected to a first node, a first protection element having a first terminal connected to the first wiring and a second terminal connected to the other end of the first resistance element, a second protection element having a third terminal connected to the other end of the second resistance element and a fourth terminal connected to the second wiring, and a third protection element having a fifth terminal connected to the first wiring and a sixth terminal connected to the second wiring.

Abstract: An input-output (I/O) buffer and a method of biasing an I/O buffer that avoids inadvertent conduction of a pull-up transistor included in the buffer when an input signal having a voltage greater than the supply voltage is applied to the I/O buffer in an input mode. Inadvertent conduction of the pull-up transistor is avoided during an input mode by biasing the gate and the body of the pull-up transistor with a supply voltage until the voltage of the input signal exceeds the voltage of the voltage supply, at which time the voltage of the input signal is applied to the gate and the body of the pull-up transistor instead. The I/O buffer includes a driver circuit having a pull-up transistor and an I/O node to receive an input signal. The I/O buffer also includes a pull-up transistor bias circuit to provide the voltage to the gate and the body of the pull-up transistor.

Abstract: A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the low potential side power supply terminal, and an internal circuit to which power is supplied from the first and second wirings. Further the semiconductor device is provided with a first and a second resistance elements whose one end is connected to a first node, a first protection element having a first terminal connected to the first wiring and a second terminal connected to the other end of the first resistance element, a second protection element having a third terminal connected to the other end of the second resistance element and a fourth terminal connected to the second wiring, and a third protection element having a fifth terminal connected to the first wiring and a sixth terminal connected to the, second wiring.

Abstract: A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the low potential side power supply terminal, and an internal circuit to which power is supplied from the first and second wirings. Further the semiconductor device is provided with a first and a second resistance elements whose one end is connected to a first node, a first protection element having a first terminal connected to the first wiring and a second terminal connected to the other end of the first resistance element, a second protection element having a third terminal connected to the other end of the second resistance element and a fourth terminal connected to the second wiring, and a third protection element having a fifth terminal connected to the first wiring and a sixth terminal connected to the second wiring.

Abstract: In an ESD protection circuit for an analog bipolar circuit, the avalanche breakdown voltage of a reverse-coupled NPN BJT acting as an avalanche diode is adjusted to comply with breakdown voltage and latchup requirements by including a resistor between the base and collector of the BJT.

Abstract: An I/O ESD protection circuit is provided utilizing a driver circuit, an ESD protection circuit, a Vcc/Vss protection circuit, and a clamping circuit. The driver circuit and the ESD protection circuit each comprise a NMOS cascode circuit. NMOS transistors and biasing resistive means comprise the Vcc/Vss protection circuit. The clamping circuit is a diode coupled between the I/O pad of the protection circuit and the gate of that NMOS transistor. In an ESD event the diode turns on the NMOS transistor of the Vcc/Vss protection circuit , thus clamping off the first transistor of both NMOS cascode circuits. The clamping inhibits the gate of those first two transistors to be coupled up by an ESD voltage and creates a parasitic bipolar transistor in each cascode circuit. The parasitic bipolar transistors provide a uniform current flow in the buried area of the P-well of both NMOS cascode circuits.

Abstract: In a semiconductor device in which an analog section to which power source lines Vdd1 and Vss1 are supplied and a digital section to which power source lines Vdd2 and Vss2 are supplied are mounted in an N-type semiconductor substrate and connected to each other by a signal line S11, a protection circuit HK1 is located between the power source line Vdd1 and Vdd2, the protection circuit becoming conductive when a potential difference between the power source lines Vdd1 and Vdd2 exceeds a prescribed value irrespectively of the direction of a surge input, thereby placing the power source lines Vdd1 and Vdd2 at substantially the same potential.