Abstract: A novel PNP driven NMOS (PDNMOS) protection scheme is provided for advanced nonsilicide/silicide submicron CMOS processes. The emitter of a PNP transistor and the drain of protection NMOS device are connected to an I/O pad for which ESD protection is provided by the PDNMOS. The collector of the PNP transistor and the gate of the protection NMOS transistor are connected to ground through a resistor. The source of the protection NMOS transistor is grounded. The base of the PNP transistor is connected to either a capacitor or the parasitic capacitor of the integrated circuit.

Abstract: A current output circuit comprises a current driver that is switchably connected across two output nodes by a switching assembly and having a switchable shunt resistor connected across the current driver. The switchable shunt resistor may be switched between a non-conducting state and a resistive conducting state. In a first data state, the current driver is connected to the output nodes by the switching assembly and the switchable shunt resistor is non-conducting so that the supplied current will flow through a load attached to the output nodes. In a second data state, the current driver is disconnected from the output nodes and the switchable shunt resistor is in a resistive conducting state. In this state the current bypasses the load and is diverted through the switchable shunt resistor. Several current drivers with appropriate switching arrangements and one or more switchable shunt resistors may be provided to allow for asymmetric current outputs in various data states.

Abstract: Reflections on bus stubs are reduced by sensing when transition occurs on the bus. When a transition is detected, an impedance matched clamp device is activated that clamps the signal to the new (post-transition) voltage for a short period of time. This clamping action reduces the energy in the reflected wave which reduces the ability of the reflected wave to change the voltage on the bus. A receiver detects when a transition occurs on the bus. The output of the receiver is coupled to a delay device. Logic gates combine the output of the delay device with the output of the receiver to produce two pulsed outputs. One pulsed output is pulsed in response to a low-to-high transition on the bus, the other pulsed output is pulsed in response to a high-to-low transition on the bus. These pulsed outputs control the clamp devices so that the clamp devices are only turned on for a short period of time.

Abstract: Bias circuits which define control terminal voltages in a cascoded nMOS ESD protection circuit, such that the circuit is in high impedance state (OFF) during normal operation, and low impedance (ON) during an ESD event. G1 and G2 are the driver circuits which define V3 and V4 during an ESD event at the pad. During normal operation, V3 and/or V4 are high and no current flows between the pad and V.sub.SS. During an ESD event, V3 and V4 are high and both devices conduct MOS current as the lateral NPNs turn on. Diode D1 conducts current to charge C.sub.c, the chip capacitance, raising V.sub.DD, enabling G1 and G2 to turn on and raise V3 and V4 to levels greater than the nMOS threshold voltage.

Abstract: The present invention provides a method and apparatus for improving immunity to common mode noise. The present invention prevents common mode noise from exceeding acceptable limits. The present invention is also useful to prevent common mode noise from being converted to differential mode noise by the action of parasitic diodes. One embodiment of the present invention bleeds charge off two differential lines such that the relative voltage differential is maintained, for example during a memory read, until at least one of the lines is low enough that the maximum possible upward noise (common+differential) is insufficient to turn on the parasitic diodes coupled to the positive voltage supply, leaving enough margin on the differential signal to allow a sensing circuit to accurately sense the differential signal.

Abstract: An integrated circuit (10) provides analog and digital circuitry on a common substrate (12). A first digital circuit (14) operates in combination with an analog circuit (18) to perform a useful function. A second duplicate digital circuit (26) is disposed adjacent to the first digital circuit and operates out-of-phase with respect to the first digital circuit. The second duplicate digital circuit introduces voltage spikes equal and opposite to the voltage spikes introduced into the substrate by the first digital circuit. The equal and opposite voltage spikes tend to cancel and thereby minimize cross-talk between the digital and analog circuits. A guard ring (16,28) surrounds each of the first and second digital circuits and the analog circuit to reduce voltage spikes into the substrates. By minimizing cross-talk, the analog circuit operates without interference from the digital circuits.

Abstract: An output driver for high speed integrated circuits includes a static driver portion and a transient driver portion. The static driver size can be adjusted to satisfy the minimal requirements for maintaining output DC voltage levels. The transient drivers include a feed-back control from the output voltage node. During a transition, the transient buffer control will sense the output level and feedback to turn off the transient driver whenever the output level rises/falls across the trip point. Accordingly the di/dt noise will drop quickly once the output has reached the trip point. The transient drivers can be larger to speed up switching speed. The buffer can use single power and ground pins or multiple power/ground pins.

Abstract: The present invention relates to a device for detecting the locking of an automatic gain control circuit, the automatic gain control circuit receiving a signal to be regulated, a check signal and a sampling control signal for driving the operation of the circuit. The detection device includes a comparator receiving the check signal and the signal to be regulated or a signal representative of the signal to be regulated. The comparator generates two logic signals, the states of which form a specific combination of logic states when the value of the signal to be regulated is in a range of values including the value of the check signal. A logic comparator circuit generates a logic comparison signal, the state of which is representative of the presence or absence of this specific combination, and a storage means, driven by the sampling control signal, stores the state of the signal provided by the logic circuit.

Abstract: A semiconductor unit is composed of an analog unit, a digital unit, a signal line through which a signal is transmitted from the analog unit to the digital unit, an electric source line Vdd1 through which a high voltage is applied to the analog unit, an electric source line Vdd2 through which the high voltage is applied to the digital unit, an electric source line Vss1 through which a low voltage is applied to the analog unit, an electric source line Vss2 through which the low voltage is applied to the digital unit, and a protective circuit arranged between the electric source lines Vss1 and Vss2. The protective circuit functions to electrically connect the electric source line Vss1 and the electric source line Vss2 in cases where an electric potential difference between the electric source lines Vss1 and Vss2 exceeds a prescribed value. Similar protection can be provided between the high voltage source lines Vdd1 and Vdd2 or between the signal line and the second source lines Vdd2 and Vss2.

Abstract: An electrostatic protection circuit in a internal circuit isolated from a substrate bias which protects the internal circuit from static electricity with regard to any of three different sources of bias voltage. An electrostatic protection circuit is constructed for each source of bias voltage so that the internal circuit is protected from static electricity flowing through bonding pads of the isolated circuit. The protective circuit comprises a plurality of NMOS or PMOS transistors for protecting input/output buffers and drivers from the static electricity flowing through the bonding pads. The respective NMOS or PMOS transistors are connected to the respective source voltage terminals and the input/output drivers.

Abstract: In a sense amplifier circuit, a CMOS inverter is connected to a power supply voltage and inverts and amplifies a voltage on a digit line connected to a selected memory cell of a memory cell section to generate a gate control signal. The first transistor is connected to the digit line and controls current flowing through the digit line in response to the gate control signal. A data of the selected memory cell is outputted from an output of the first transistor. A stabilizing section stabilizes an operation of the CMOS inverter such that a same operation of the CMOS inverter can be performed independent from change of the power supply voltage.

Abstract: The present invention is aimed at providing a method and a circuit for protecting the output stage of a power actuator against voltage transients of the surge type. In particular, it provides protection against voltage surge transients of the kind described by International Standard IEC 801-5, for a power transistor contained in the output stage of the actuator.The method of this invention provides for:the utilization of the power transistor (PW) intrinsic diode (DP) for dumping the transient energy to one of the supply generator terminals during a positive transient; andthe utilization of the power transistor (PW) restoration feature to the on state for dumping the energy thereinto during a negative transient, while simultaneously inhibiting the current limiting function.

Abstract: A circuit suppresses an additive transient disturbance in an input signal. A main signal path transmits the input signal, and a switchable signal path is switchable into the main signal path during a portion of the disturbance. A positive envelope detector and a negative envelope detector detects, respectively, a positive envelope signal and a negative envelope signal. In response to these signals, positive and negative envelope signals are subtracted from the main signal path only during the portion of the disturbance.

Abstract: Disclosed is a novel circuit technique that will significantly improve the noise margin of a passgate latch design. The circuit technique consists of a passgate latch with additional circuitry for sensing the occurrence of coupled noise and then turning on a current mirror that injects current into the latch internal node to stabilize the latch. The circuit further includes a disabling system for disabling the additional circuitry during normal operation of the passgate latch.

Abstract: An input protection circuit which protects a first-stage inverter circuit against an electrostatic surge. The input protection circuit includes n-channel MIS type punch-through transistor for discharging the electrostatic surge to a ground terminal and a p-channel MIS type load transistor coupled between a signal input pad and the n-channel MIS type punch-through transistor, the p-channel MIS type load transistor having a gate and a back-gate concurrently applied with the electrostatic surge so that a dielectric breakdown hardly takes place in a gate insulating film.

Abstract: An apparatus and method for recovering packet data with unknown delays and error transients is disclosed that includes a received waveform containing a desired information signal relative to a fixed reference, for eliminating an undesired error in the received waveform where the error is localized in time relative to the received waveform to a transient interval, and recovering the desired information signal. Included also is a sampler, responsive to the received waveform, providing a series of time samples representative of the received waveform. A buffer, responsive to the time samples, for providing a plurality of representations of the received waveform at different instants of time, where the length of time is an appreciable duration of a transient interval. A reference slicker, responsive to the plurality of representations, for providing an estimate of a fixed reference.

Abstract: A driver circuit for transmitting data via an output node thereof to a transmission line includes a first driving device coupled to the output node and a second driving device coupled to the same output node. The driver circuit further includes a slew rate controller coupled to the first and second driving devices. The slew rate controller includes a first reference device coupled to the first driving device. The first reference device generates a first current. The slew rate controller also includes a second reference device coupled to the second driving device. The second reference device generates a second current. The slew rate controller further includes a summing device, coupled to the first and second reference devices. The summing node is also coupled to the output node, via an integrating device, to the output node. The summing device generates at the output node a slew rate proportional to the first current when the first driving device is substantially conducting.

Abstract: The present invention concerns a method and apparatus that generally prevents an output glitch in a sense amplifier during a transition from a strong zero to a weak zero. When multiple cells are turned on, a virtual ground node is raised high due to the current flowing through the virtual ground device. A recover node is generally held close to the read product term line RPT. When a transition from a strong zero occurs, the recover node swings to VCC and provides conductance on the virtual ground node which generally eliminates the glitch.

Abstract: A terminating circuit including a pair of diodes connected to have polarities opposite to each other is provided across a magnetic head. When the potential difference across the magnetic head is drastically changed to be equal to or higher than the breakdown voltage of the diodes at the time of switching of a writing current, either one of the diodes breaks down, so that a part of the writing current flows out through the terminating circuit. As a result, ringing due to the drastic change is removed. When the potential difference across the magnetic head is lower than the breakdown voltage of the diodes, since either one of the diodes is reversely biased, the resistance of the terminating circuit is maintained high. Consequently, within this range, the writing current flowing to the magnetic head never flows out to the terminating circuit. As a result, the deterioration of the reading and writing characteristics is prevented.

Abstract: An apparatus for diminishing supply and ground bounce in integrated circuits. Two separate techniques are used simultaneously to diminish the problem of ground bounce. First impedance is placed between a power source bus on the integrated circuit and an external power source; and between a ground bus on the chip and an external ground. This effectively dampens ground bounce oscillations in the power and ground leads of the chip. Secondly, capacitance is dynamically added to the pre-drive of an output buffer with a capacitance node. Dynamic digital sizing is utilized in both techniques, therefore both techniques are responsive to the changing performance variations within the chip.

Abstract: A method and apparatus for removing low frequency noise and any offsets common to a plurality of samples of a signal, for calibrating an offset level to be added to the signal to reference the signal to a desired reference level at an output of the apparatus, and for clamping an input voltage level to the apparatus to a desired voltage within an operating range of the apparatus. The apparatus includes a correlated double-sampling circuit which takes a first sample and a second sample of the analog signal, takes a difference between the first sample and the second sample to remove low frequency noise and any offsets common to both samples and which outputs a difference signal. In addition, the apparatus includes a black level correction circuit which adds an offset level to the difference signal to calibrate the offset level to be added to the difference signal so that the difference signal is at a desired reference level at an output of the apparatus.

Abstract: First and second analogue signal processing circuit has first to fourth input terminals and first and second output terminals, and functions such that the first and second output terminals have an equal potential and that a difference between output currents of the first and second output terminals is proportional to a product obtained by multiplying a potential difference between the first and second input terminals by a potential difference between the third and fourth input terminals. The first input terminal of the first analogue signal processing circuit is supplied with an input signal, and the second input terminal is supplied with ground potential. The third input terminal is supplied with a second reference potential, and the fourth input terminal is supplied with a third reference potential. The first input terminal of the second analogue signal processing circuit is supplied with an output signal from an operational amplifier, and the second input terminal is supplied with the ground potential.

Abstract: An integrated circuit includes a semiconductor die and electronic circuitry elements formed therein. First and second internal power supply lines transmit first and second supply voltages to provide power for the circuitry elements. The die includes bypass circuitry to inhibit variations in the supply voltages. The bypass circuitry includes transconductance circuitry, characterized by a variable conductivity, having a first flow electrode coupled to the first supply line, a second flow electrode coupled to the second supply line, and a control electrode for controlling current flow between the flow electrodes. The conductivity of the transconductance circuitry varies in response to a voltage difference between the control electrode and the second flow electrode. Voltage amplifier circuitry has a first input terminal coupled to the first supply line and a second input terminal coupled to the second supply line.

Abstract: Electronic switch for low-voltage supply circuits completed with CMOS technology and comprising a first, a second and a third circuit element (SW1 ,SW2,SW3) consisting each of a pair of complementary transistors. The first and second of said elements (SW1,SW2) are inserted between two connection terminals of the switch (A,B) while the third element SW3 is inserted between a node (C) included between the first and the second element of a voltage reference (VCM). The first and second element are driven to conduction in phases (.phi.1) not overlapping the phases (.phi.2) in which it conducts the third element.

Abstract: An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch.

Abstract: The inventor has created several methods to eliminate or greatly reduce the ground loop problem. The inventor has discover that ground loop distortion is caused by the switching from positive to negative in alternating current. He has designed several devices to eliminate this problem. In his first embodiment he places a set of two diodes either cathode to cathode or anode to anode, or a neon bulb, or piezoelectric crystals in parallel with all the capacitors in an amplifier or other electronic device. These sets of diodes eliminate the ground loop distortion within the amplifier or electronic device. The applicant has also devises several power supply that eliminate or greatly reduce the ground loop distortion in an amplifier or electronic device they are attached to. Also the applicant has found that by attaching two diodes either anode to anode or cathode to cathode, or a neon bulb, or a piezoelectric crystals between an audio, video or digital cable and its ground will reduce distortion within the cable.

Abstract: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.

Abstract: A load current detection circuit restrains the generation of noise spikes with a minimum of circuitry when changing between current detection sensitivity ranges by providing a plurality of sensitivity resistors between the output of a voltage source, such as a negative feedback voltage amplifier, and a load. Sensitivity range changing is performed via switches that increase or decrease the number of sensitivity resistors between the voltage source and the load. When a current detection sensitivity change is commanded, a voltage difference across the sensitivity resistors is measured, and a control processor generates a control voltage for changing voltage difference gradually until the voltage difference is zero without changing the voltage across the load. The sensitivity range switching then occurs when no current flows through the sensitivity resistors so that no noise spikes are produced.

Abstract: A microprocessor clocking system is provided for achieving attenuation of a clock signal sent to a microprocessor during initial activation of a connected power supply. By attenuating the clock signal during initial turn-on of the power supply, the clock input to the microprocessor is prevented from erroneous triggering and improper operation. After a delay period has expired, the clock signal is allowed to input directly to the microprocessor input. The delay period is determined as a time exceeding normal spurious noise conditions found on the power supply during initial activation. The microprocessor clocking system includes a clock conditioning circuit configured between a clock signal output of a core logic unit and the clock signal input to a microprocessor. The clock conditioning circuit utilizes a turn-on circuit and a delay circuit coupled to the power supply voltage.

Abstract: A monolithic voltage clamp provides low impedance, low voltage electrostatic discharge protection for an integrated circuit without affecting the integrated circuit's DC characteristics. First, second, third, and fourth regions of semiconducting material are formed with p-n junctions between each region. A first inductor electrically connects the first and second regions, and a second inductor electrically connects the third and fourth regions. The first and second inductors should each have an inductance which is large enough to delay an increase in bypass current around their respective p-n junctions for a period which is long enough to assure that conduction is sufficient to discharge an electrostatic pulse. In a preferred embodiment, first and second reverse bias diodes are used to electrically connect the invention to one or more input/output nodes.

Abstract: An integrated circuit output stage is intended for use with an operational amplifier. The output is capable of driving capacitive load to within a V.sub.SAT of the power supply rails. The complementary output transistors are driven by way of a combination of buffers and complementary differential amplifiers which act to bias the stage in class AB. The quiescent current is stabilized and controlled, in part, by simple resistor rationing. The output transistor saturation is sensed and a current limit is imposed so that hard saturation is avoided. Frequency compensation is achieved in a manner that responds to output transistor saturation so as to improve the high frequency transient response. Feedforward capacitors are also included to further improve high frequency response.

Abstract: The invention is an active, hot insertable, SCSI terminator circuit having a bypass device that permits an initially unpowered active SCSI terminator to be coupled to a signal line of a powered SCSI bus such that no damage results to the SCSI terminator circuit itself or to other SCSI devices on the SCSI bus, and without having the effect of altering the existing state of the SCSI bus as a result of the coupling. Preferably, the terminating element of the SCSI terminator is a p-channel MOSFET. The SCSI terminator is prevented from being damaged during the coupling by using the bypass device to effectively short the gate of the p-channel MOSFET terminating element to its drain. When the drain of the p-channel MOSFET terminating element is shorted to its gate the amount of current the SCSI terminator may draw from any and all SCSI signal lines during the coupling is substantially limited to less than 50 .mu.A.

Abstract: An active clamp circuit for controlling over-voltage, surge conditions in electrical circuits. The active clamp includes a varistor which is switched into a circuit by a high power switch upon the detection of a surge condition. The use of a MOS Controlled Thyristor ("MCT") as a means for the switching the varistor permits the circuit to withstand a high di/dt and surge current while maintaining both on and off gated control of the switch.

Abstract: A resistance capacitance (RC) coupled low-voltage triggering silicon-controlled rectifier (LVTSCR) suppression circuit is presented for protecting an integrated circuit from electrostatic discharges or other potentially damaging voltage transients occurring at an input and/or output node of the integrated circuit or integrated circuit chip. The suppression circuit includes a discharge circuit and a trigger circuit. The discharge circuit is electrically coupled to the input and/or output node for dissipating the electrostatic discharge, while the trigger circuit is electrically connected to the input and/or output node and to the discharge circuit. The trigger circuit provides direct low-voltage turn-on of the discharge circuit as the electrostatic discharge builds at the input and/or output node of the integrated circuit.

Abstract: In a circuit configuration for the shutoff of a semiconductor component in the event of excess current, the semiconductor component has gate and cathode terminals and is controlled by the field effect. A controllable switch is connected between the gate and cathode terminals and is made conducting by a control signal. A device controls the controllable switch to a range of high on-state DC resistance when there is excess current and a shutoff signal is simultaneously present.

Abstract: A control circuit for controlling the power or bounce of an output driver circuit is disclosed. The control circuit can sense the output voltage and/or the bounce and then adjust the control node voltage of the output driver circuit accordingly. In addition, the output circuit can discharge the output node to a lower voltage level before turning on the output driver circuit.

Abstract: An apparatus for suppressing voltage transients and detecting desaturation conditions in power transistor systems. A first transistor, usually a power transistor, has a first terminal, a second terminal, a drive terminal, and an avalanche breakdown voltage rating between the first mad second terminals. The cathode of a first diode is coupled to the first terminal of the first transistor. The first diode has a reverse breakdown voltage which is less than the avalanche breakdown voltage rating of the first transistor. The anode of a second diode is coupled to the anode of the first diode, and the cathode of the second diode is coupled to the drive terminal of the first transistor. Driver circuitry is also coupled to the drive terminal, and provides a drive signal to the first transistor. An RC network comprising a first resistor and a first capacitor is coupled to the driver circuitry. The base terminal of a second transistor is coupled to the driver circuitry by means of the RC network.

Abstract: A transmission line driver circuit has active pullup and pulldown N-type field-effect transistors (N-FETs). An input stage employs a group of N-FETs and a group of P-type field-effect transistors (P-FETs) both being dimensioned and configured to yield a variable-slope switching characteristic for both high-to-low and low-to-high signal transitions. In the N-FET group, one N-FET has the same threshold voltage as the pulldown N-FET, is diode-connected, and is also connected in parallel with a substantially smaller N-FET. In the P-FET group, one P-FET is connected in parallel with a substantially smaller P-FET, and receives a buffered version of the output signal. Both the larger N-FET and larger P-FET conduct for only part of the respective signal transition during which they are active, so that each edge has two distinct slopes. The driver circuit also includes a differential amplifier connected in feedback configuration with the pullup N-FET to limit the maximum transmission line voltage.

Abstract: An active filter circuit has differential transistors having first conductivity type bipolar transistors and load transistors having second conductivity type bipolar transistors. A connecting node between the differential transistors and the load transistors is driven by a middle electric potential. Voltage dependent characteristics of earth capacitance including parasitic capacitances parasitic to the differential transistors and the load transistors can be kept constant by offsetting the voltage dependent characteristics of the parasitic capacitances. It is thereby possible to make the active filter circuit small in size and the consumed electric power reduced.

Abstract: A non-saturating transistor circuit (11) having a first terminal (13), a control terminal (12), and a second terminal (14). The first terminal (13), control terminal (12), and second terminal (14) correspond respectively to a collector, base, and emitter of a transistor. The non-saturating transistor circuit (11) comprises a voltage divider (15), a diode (19), and a transistor (16). The voltage divider (15) enables the transistor (16) when a voltage is applied across the control terminal (12) and the second terminal (14) of non-saturating transistor circuit (11). The diode (19) removes current drive to the transistor (16) prior to the transistor (16) becoming saturated thus preventing the transistor (16) from saturating under all operating conditions.

Abstract: An improved gate drive circuit for use with a switching power device in a power converter and other power-transfer type circuits and the like is described. The gate drive circuit according to the present invention requires fewer components and space that convention prior art gate drive circuits. The drive circuit provides isolation between the control circuitry and the device without storing a significant amount of long-term (i.e., D.C.) energy and is also more energy efficient than many prior art gate drive circuits. Additionally, the present invention comprises means for cleanly terminating the drive signal to the switching power device when the control circuitry terminates operation. This prevents an incorrect signal to the switching power device, which may conduct at an inappropriate time, causing damage to the power converter or power-transfer circuit. Many prior art drive circuits have D.C.

Abstract: A noise suppression circuit for a floating bus in a digital integrated circuit includes pull-up and pull-down feedback loops each connected to the floating bus. The pull-up feedback loop includes a PMOS device connected between a high logic level and the floating bus, with a NOR gate switching the PMOS device. The pull-down feedback loop includes an NMOS device connected between a low logic level and the floating bus, with a NAND gate switches the NMOS device. The NOR and NAND gates are configured such that one of their inputs is connected directly to the floating bus and the other input is connected to the floating bus through an inverter having a finite gate delay. Voltage transitions occurring on the floating bus due to noise injection drive the bus back to its original state before the finite gate delay of the inverter.

Abstract: In order to prevent a malfunction caused by an electrical noise and limit an excessive main current at a high speed while cutting off the same to a value close to zero, the main current is regulated by an IGBT (1) which is connected with a load. A part of this main current is shunted to another IGBT (2). The as-shunted current flows through a resistor (3), to be converted to a voltage across the resistor (3). When the main current is excessively increased by shorting of the load or the like, this voltage exceeds a prescribed value so that a transistor (5) and a thyristor (7) enter conducting states. Consequently, a voltage across a gate (G) and an emitter (E) of the IGBT (1) is so reduced as to cut off the main current. The transistor (5) prevents the main current from excessive increase since the same has a high speed of response, while the thyristor (7) cuts off the main current to zero since the same has lower resistance in conduction.

Abstract: An output buffer circuit has a pull-up output transistor controlled by a first node and a pull-down output transistor controlled by a second node. The first node is coupled to the second node through a switching stage controlled by feedback from the output terminal. When the output buffer circuit is switched between the high and low output states, the switching stage is initially on, switches off shortly after the potential of the output terminal begins to change, then switches on again when the output terminal reaches a certain intermediate potential.

Abstract: A power output stage has a Darlington-pair circuit (11, 12) for switching an inductive load, especially the ignition coil of an internalcombustion engine. In order to predetermine the operating mode of the power output stage, a switch (24) is provided which bridges the base-emitter junction of the Darlington-pair circuit (11, 12), is closed in the event of a quick disconnection of the output stage, and is opened in the event of a voltage-limited disconnection of the output stage. A voltage divider, which consists of at least two resistors (16, 18) and bridges the switching junction of the Darlington-pair circuit (11, 12), is connected by means of its pick-off to the junction point between the switch (24) and the base of the Darlington-pair circuit (11, 12), the switch (24) being connected in parallel with a part (18) of the voltage divider.

Abstract: A noise-suppression logic system suppresses a noise signal having a time duration which is less than a predetermined time. A delay circuit has a delay which is equal to the predetermined time. A logic combining circuit is coupled to the system input terminal and to the output terminal of the delay circuit. A R-S latch circuit, having a RESET input terminal, a SET input terminal, and an OUTPUT terminal provides a delayed output signal corresponding to an input signal which has a time duration greater than the predetermined time. A set circuit has a first input terminal coupled to the system input terminal, a second input terminal coupled to the output terminal of the delay circuit, and an output terminal coupled to the SET input terminal of the R-S flip-flop circuit.

Abstract: A high efficiency switching power transistor uses the energy in a snubber circuit to drive the gate driver and the pulse-width-modulator (PWM). The snubber consists of a resistor and a capacitor connected in series between the drain and source of a field-effect-transistor (FET). A steering diode is connected from the junction between the capacitor and the resistor to the power supply of the gate driver and PWM. This diode steers current from the snubber and makes it flow into the power supply thereby lowering the power requirements of the power supply. This energy would have been dissipated in the snubber as heat if it were not used this way. Efficiency of the switcher is increased both by lowering heat loss in the snubber and by using recovered snubber energy to lower the power requirements of the power supply of the gate driver and PWM.

Abstract: A data slicer follows abrupt variations in level of the detection signal. The data slicer for converting a detection signal into a digital signal in a data transmission system includes a maximum value detecting section, a minimum value detecting section, a voltage shift-down section, a voltage shift-up section, and a binary encoding circuit. The maximum value detecting section detects the maximum value of the detecting signal, while the minimum value detecting section detects the minimum value of the detecting signal. The voltage shift-down section sets a minimum value which the minimum value detecting section should take according to the output voltage of the maximum value detecting section, while the voltage shift-up section sets a maximum value which the maximum value detecting section should take according to the output voltage of the minimum value detecting section.

Abstract: In a noise canceler, a pilot-canceling signal without noise is applied to the inverting input of a subtracter via a first MOS transistor. When a noise signal is present, a pilot signal and noise signal passing through a capacitor are applied to the inverting input port of the subtracter via a second MOS transistor to cancel the noise signal contained in the composite input signal. In the canceler, external noise may be digitally converted and the inverted noise thereof stored in a memory. When a noise signal detector detects the external noise, inverted data corresponding to the external noise is output from the memory. The detector enables an address generator to continuously generate addresses. The memory reads out inverted noise patterns which are converted into analog form and transmitted via a speaker, thereby canceling noises produced by various electrical and electronic appliances as well as nearby automobiles and aircraft.

Abstract: A semiconductor component for limiting transient voltages on the signal or other supply lines of a system, includes, in a common semiconductor body, a plurality of multi-junction diodes connected in the same sense between a common terminal and respective input means which are for connection to the respective supply lines of the system, and a respective further diode connected in shunt with each multi-junction diode with the opposite sense to the multi-junction diode.