Abstract: The present disclosure provides a brushless motor driving circuit capable of clamping an output voltage at a proper voltage, even when a power source voltage changes. Namely, a pre-driver circuit generates a voltage for driving a brushless motor from a source voltage by turning on/off first and second PMOS transistors and first and second NMOS transistors in an H bridge circuit of a drive voltage generating circuit, and applies the voltage to a coil of the brushless motor. A first clamp circuit turns on/off the first NMOS transistor on the ground side so that the output voltage at a first output terminal becomes equal to or lower than the source voltage. A second clamp circuit turns on/off the second NMOS transistor on the ground side so that output voltage at a second output terminal becomes equal to or lower than the source voltage.

Abstract: The limiter circuit of this invention is a limiter circuit which, by switching action of a pair of transistors, allows passage of only signal voltage components of an input signal voltage included in ranges of an upper limit signal voltage and a lower limit signal voltage. With this construction, the pair of transistors carry out comparisons between the input signal voltage and threshold signal voltages and line switching at the same time. Therefore, there is no influence of propagation delay speed, and no switching noise occurs at times of line switching. Since diodes are not used, a high-speed limiter circuit can be manufactured.

Abstract: An apparatus comprises an integrated circuit (IC) comprising an external IC connection, an IC substrate connection, a voltage clamp circuit and an under voltage circuit. The voltage of the IC substrate connection is set to a first voltage when a voltage of the external connection of the IC is within a normal operating voltage range. The voltage clamp circuit is configured to clamp the voltage supply of one or more circuits internal to the IC to within a normal operating voltage range when the voltage of the external IC connection exceeds the normal operating voltage range. The under voltage circuit is communicatively coupled to the clamp circuit and configured to set the voltage of the substrate to a second voltage when the voltage at the external IC connection of the IC is less than zero volts.

Abstract: A MOS-type semiconductor clamping circuit is disclosed. The clamping circuit comprises a pmos device coupled to a nmos device in series to form the clamping circuit to selectively clamp a signal to a reference voltage, the signal configured to swing between a first voltage and a second voltage about the reference voltage. When the signal is swung between the first voltage and the second voltage, the pmos device and the nmos device are subjected to a voltage swing less than the voltage swing between the first voltage and the second voltage.

Abstract: A clamp-point active circuit is provided. The clamp-point active circuit includes a rate amplifier configured to receive an output from a device transitioning between at least two levels. The clamp-point active circuit has at least one switching device configured to receive an output from the rate amplifier. The at least one switching device is in at least one respective feedback loop of the rate amplifier. A switching of the at least one switching device causes the rate amplifier to amplify with high linearity in a desired operating range and to clamp outputs received from the transitioning device that are outside the desired operating range to a fixed level.

Abstract: A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio.

Abstract: A MOS-type semiconductor clamping circuit is disclosed. The clamping circuit comprises a pmos device coupled to a nmos device in series to form the clamping circuit to selectively clamp a signal to a reference voltage, the signal configured to swing between a first voltage and a second voltage about the reference voltage. When the signal is swung between the first voltage and the second voltage, the pmos device and the nmos device are subjected to a voltage swing less than the voltage swing between the first voltage and the second voltage.

Abstract: In an active clamp implemented in a 5V complementary BiCMOS process, the footprint of the active clamp, which includes at least one NMOS clamp stack, is reduced by introducing a BJT into the circuit to allow the number of NMOS clamp stacks to be reduced.

Abstract: Methods, devices, and systems are provided for a power generator system. The power generator system may include a control device configured to output a first reference voltage and a second reference voltage that define a dead band range. The control device may be configured to independently adjust the first reference voltage and the second reference voltage. The power generator system may also include a power generator operably coupled to the control device, and the power generator may be configured to receive the first reference voltage and the second reference voltage and to output a voltage that is greater than or substantially equal to the first reference voltage and less than or substantially equal to the second reference voltage.

Abstract: A power device includes a power transistor, a capacitor with a first plate coupled to a ground node and a second plate separated from the first plate by an insulator, a first plurality of wires coupling a drain node of the power transistor to the second plate of the capacitor, a second plurality of wires coupling the second plate of the capacitor to a DC supply node, and a voltage clamping device coupled in parallel with the capacitor. The voltage clamping device is operable to limit the voltage at the second plate of the capacitor to a value below a breakdown voltage of the power transistor.

Abstract: The limiter of the invention uses as a diode a stacked gate thin film transistor (TFT) including a floating gate. When the TFT including a floating gate is used, the threshold voltage Vth may be corrected by controlling the amount of charge accumulated in the floating gate even in the case where there are variations in the threshold voltages Vth of the TFT.

Abstract: A communication system comprises a twisted pair communication link operably coupled to at least two driver stages for providing at least two independent input signals on the twisted pair communication link. The at least two independent input signals on the twisted pair communication link are summed and input to a comparator arranged to compare the summed signal to a reference value. The output of the comparator is input to the at least two driver stages. The outputs from the at least two driver stages are summed and fed back and summed with one or more of the independent input signals. In this manner, adverse effects due to non-ideal symmetry between components in a twisted pair communication link, such as a Controller Area Network system, are reduced.

Abstract: An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.

Abstract: An N-channel transistor is provided as a switch between a high potential power line and a low potential power line. A high-pass filter is constituted by a capacitor and a resistor. When a voltage between the high potential power line and the low potential power line is started to oscillate by a switching operation, the high-pass filter causes a high-pass component thereof to pass, thereby turning ON the N-channel transistor to reduce a ringing.

Abstract: The self-powered detection device comprises a Non-Volatile Memory (NVM) unit (52) formed at least by a NVM cell and a sensor which is activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester that transforms energy from said physical or chemical action or phenomenon into an electrical stimulus pulse, said NVM unit being arranged for storing in said NVM cell, by using the electrical power of said electrical stimulus pulse, a bit of information relative to the detection by said sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal (SET) and a base terminal (SET *) of said NVM unit with at least a given set voltage.

Abstract: An operating circuit includes a differential amplifier stage, which has a first input node for receiving a first input signal of a differential input, a second input node for receiving a second input signal of the differential input, a first output node for outputting a first output signal of a differential output, and a second output node for outputting a second output signal of the differential output; an offset current stage coupled to the first output node and the second output node for inducing a first offset current at the first output node and a second offset current at the second output node; and a first clamping device coupled to the first output node for selectively clamping an output voltage at the first output node according to the first output signal at the first output node.

Abstract: A level shift circuit shifts a first voltage level to a second voltage level that is different from the first voltage level. The level shift circuit includes a set-level circuit 21 configured to detect and transmit a set signal that is used to set a logic voltage state based on the second voltage level, a reset-level circuit 22 configured to detect and transmit a reset signal that is used to reset the logic voltage state based on the second voltage level, and a reference-level circuit C3 configured to provide a reference signal that is used to detect the set signal and reset signal based on the second voltage level. The set-level circuit, reset-level circuit, and reference-level circuit transmit signals from the first voltage level to the second voltage level through capacitors C1, C2, and C3, respectively.

Abstract: A temperature sensor circuit comprises a first reference voltage generator configured to generate a first signal that linearly varies with temperature and a first reference voltage signal that maintains a certain level irrespective of temperature, a second reference voltage generator configured to generate a second reference voltage signal by using the first reference voltage signal, and a controller configured to compare the first signal with the second reference voltage signal and control a voltage level of the first signal according to a comparison result.

Abstract: A preset circuit of an audio power amplifier includes an inverter and a voltage drop device. The inverter receives an input signal to output an output signal, and includes a first switch and a second switch. The first switch is controlled with the input signal, and has a first terminal coupled to a power voltage and a second terminal for outputting the output signal. The second switch is controlled with the input signal, and has a third terminal for outputting the output signal and a fourth terminal coupled to a low reference voltage. The voltage drop device is coupled between the first terminal of the first switch and the power voltage and configured to lower the power voltage. The output signal is kept at a low level when the voltage drop device and the first switch are de-actuated due to the power voltage having a level below a first threshold.

Abstract: A cascoded input-output device is provided configured to receive at an input node a lower voltage input signal and to generate at an output node a higher voltage output signal. The input-output device is split into two voltage domains to enable output signals in a larger range to be generated, whilst the components of the input-output device individually operate in a smaller range. By applying a selected bias voltage to a protected node of the cascoded input-output device, first changing that selected bias voltage in response to a transition of the input signal and then switching that selected bias voltage back when the output signal reaches a predetermined level, that node is protected, either avoiding stress-inducing voltage swings or providing a switching speed increasing charge boost.

Abstract: The invention relates to the field of signal processing. It is an object of the invention to provide for limitation of a signal voltage to a predetermined maximum voltage (Vmax). To this end, an input signal (Vin) is applied to a voltage divider which includes a variable-resistance component (T1) whose resistance is controlled by a control signal. An output signal (Vin?) is picked-up at the variable-resistance component (T1). The control signal is generated as an amplified difference between the output signal (Vin?) and a fixed reference voltage (Vmax/2), so that for an “overvoltage case” in which the value of the input signal (Vin) exceeds that of a predetermined maximum voltage (Vmax) the output signal (Vin?) is kept substantially constant.

Abstract: A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.

Abstract: By using a stacked gate transistor including a floating gate in a limiter, a threshold voltage Vth of the stacked gate transistor can be corrected by controlling the amount of charge accumulated in the floating gate of the stacked gate transistor even in the case where there are variations in the threshold voltage Vth of the stacked gate transistor.

Abstract: A storage section (101) stores a digital value. A compensation section (102) controls an offset value of an amplifier circuit (2) according to the digital value stored in the storage section (101). A determination section (103) determines whether the voltage value of an output signal (S2) from the amplifier circuit (2) is higher or lower than a reference voltage value. An adjustment section (104) adds a positive value to the digital value in the storage section (101) if the number of times the voltage value of the output signal is determined higher than the reference voltage value among k determination results by the determination section (103) is greater than the number of times the voltage value of the output signal is determined lower than the reference voltage value.

Abstract: A voltage clamping circuit includes a current source having a fixed current source and a variable current source and a variable resistor receiving current from the current source. The variable resistor varies its resistance in response to an environmental operating condition. The voltage clamping circuit also includes an amplifier configured to compare a sensor node voltage with a reference voltage, the sensor node voltage being in communication with the voltage drop across the variable resistor. The amplifier is configured and connected to provide a control output to control the variable current source to modify current output from the variable current source to at least in part prevent the sensor node voltage from exceeding a reference voltage when certain operating conditions are present.

Abstract: An internal voltage detection circuit and an internal voltage generation device using the same are disclosed. The internal voltage detection circuit includes a first detect signal generator for generating a first detect signal to detect a level of an internal voltage corresponding to an operating temperature of a memory cell, a second detect signal generator for generating a second detect signal to detect a specific level of the internal voltage corresponding to a preset temperature, and a detect signal clamp unit for comparing a level of the first detect signal and a level of the second detect signal with each other and clamping the first detect signal according to a result of the comparison.

Abstract: A signal adjusting circuit is provided. The signal adjusting circuit includes a first operational unit, a second operational unit, an auto-gain controller (AGC), a first clamp circuit, and a second clamp circuit is provided. The first operational unit performs an operation to a digital signal and a first gain value, to obtain a first adjusting signal. The second operational unit performs an operation to the digital signal and a second gain value, to obtain a second adjusting signal. The AGC generates a third gain value according to the first adjusting signal. The first clamp circuit receives and restricts the third gain value between a first upper limit and a first lower limit for generating the first gain value. The second clamp circuit receives and restricts the third gain value between a second upper limit and a second lower limit for generating the second gain value.

Abstract: The present invention provides a voltage clamping circuit which is operated in a stable manner with the simple constitution and a switching power source device which enables a high-speed operation. In a switching power source device, one of source/drain routes is connected to an input terminal to which an input voltage is supplied, a predetermined voltage to be restricted is supplied to a gate, and using a MOSFET which provides a current source between another source/drain route and a ground potential of the circuit, a clamp output voltage which corresponds to the input voltage is obtained from another source/drain route. The switching power source device further includes a first switching element which controls a current which is made to flow in an inductor such that the output voltage assumes a predetermined voltage and a second switching element which clamps an reverse electromotive voltage generated in the inductor when the first switching element is turned off to a predetermined potential.

Abstract: For supplying voltage to at least one main current consuming unit, a voltage supply unit provides the voltage to the at least one main current consuming unit at a supply node. In addition, an auxiliary current consuming unit conducts auxiliary current from/to the supply node for at least a predetermined time period before the at least one main current consuming unit begins to conduct current. Thus, voltage overshoot is prevented at the supply node.

Abstract: An electronic device under test (DUT) may be incorporated into a circuit having a voltage limiter connected in parallel with the DUT. The circuit includes a controlled current source having an output current connected in series with the DUT. The voltage limiter is characterized in that, when the output current is such that the voltage across the DUT (Vdut) would exceed a particular maximum voltage Vmax, without the voltage limiter in place, at least a portion of the output current flows through the voltage limiter, so as to limit Vdut to be less than or equal to Vmax. When the output current is such that Vdut would be less than or equal to Vmax, current does not flow through the voltage limiter. The circuit may include a plurality of DUTs, each DUT connected in series with the output current of a controlled current source, with a voltage limiter connected in parallel with each DUT.

Abstract: The invention provides a serial link transmitter coupled to a serial link receiver through a pair of transmission lines and having a pair of transmitting terminals respectively coupled to one of the transmission lines. The serial link transmitter comprises a differential amplifier and a voltage clamping circuit. The differential amplifier generates a pair of differential output voltages on the transmitting terminals according to a pair of differential input voltages for transmitting data to the serial link receiver, and the differential output voltages are transmitted with a common mode voltage to the serial link receiver during data transmission. The voltage clamping circuit clamps the pair of differential output voltages of the transmitting terminals to the common mode voltage before the serial link transmitter transmits data to the serial link receiver.

Abstract: A semiconductor memory device includes a mode register set circuit having a changeable default value. The mode register set circuit, the default value of which is changeable, includes a signal input unit for latching an input signal, a storage unit driven by an initializing signal for setting the default value to a logic high or low state as required, and an output unit for latching an output of the storage unit.

Abstract: A circuit and method for limiting a signal voltage in which the minimum and maximum levels of the output signal can be controlled by selectively applying different lower and higher reference voltages from which the minimum and maximum output signal levels are derived.

Abstract: An active clamp switching circuit includes a transformer having a primary winding and a secondary winding, a first switch, a capacitor, an impedance device, a second switch and a rectifier. The capacitor, the impedance device and the second switch form a reset loop for the primary winding so that the impedance device lowers the electric current going through the second switch, preventing burnout of the second switch.

Abstract: Versatile control pin electronics are disclosed. The control pin electronics are coupled to a control pin and allow for the passing of both analog and digital control signals. The control pin electronics work with digital logic having logic levels that are compatible with analog signals having predefined voltage and current limits. The versatile control pin electronics include both a voltage regulator that sets a regulated voltage at the control pin and a current limiter. The versatile control pin electronics can be coupled to a comparator to provide both hysteresis and latching functionality from a single pin.

Abstract: A driving circuit of a switch includes first and second transistors connected in series to each other and to relative intrinsic diodes in antiseries and driven by a driving device that includes at least one first and one second output terminal connected to the switch to supply it with a first control signal for driving the switch in a first working state and a second control signal for driving the switch in a second working state. At least one latch circuit coupled between respective common gate and source terminals of the first and second transistors supplies the common gate terminal with the first and second control signals, respectively, according to the working state to turn off and turn on the first and second transistors.

Abstract: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.

Abstract: An integrated circuit radio transceiver and method therefor includes a linear regulator an output transistor for producing a current into an output node of the regulator wherein an amplification block is operable to produce a bias signal to a gate terminal of the output transistor to operably bias the output transistor to produce the current into the output node of the regulator. A current steering amplification block is operably disposed to steer current in/out of the gate of the output transistor (depending on device type) based upon the current being conducted through the output node of the regulator exceeding a specified threshold. The current steering amplification block further includes a current sinking element operably disposed to sink a specified amount of current to define the specified threshold.

Abstract: A novel system for protecting one or more circuits during a dose rate event is presented. A clamping circuit is utilized that outputs a voltage signal that may be used to control prevent circuits from receiving input signals during a dose rate event. The clamping circuit comprises a photocurrent generating device that creates a current as a function of dose rate event strength. This current is used to control a grounding switch, which pulls the clamping circuit output to ground when a substantial current is created by the photocurrent generating device. The clamping circuit output may control a coupling switch that permits external input signal current flow when the clamping circuit output is above a threshold voltage level, and may prevent current flow when the output is grounded. The photocurrent generating device may be a PMOS device, while the coupling switch and clamping switch may be realized by NMOS devices.

Abstract: An output circuit includes an output block and a predrive block for driving the output block based on an input signal. The predrive block has a clamp unit connected between the gate terminal of a first output transistor and the gate terminal of a second output transistor to limit the potential of the gate terminal of the first output transistor to a value of not more than a first potential and limit the potential of the gate terminal of the second output transistor to a value of not less than a second potential.

Abstract: A clamper circuit for receiving an input signal from a victim wire, the clamper circuit being capable of receiving aggressor signals from aggressor wires, the aggressor wires being the signal wires that can potentially induce crosstalk on the victim wire and an output signal being selectively enabled based on the logic states of the input signal and the aggressor signals, the clamper circuit also being capable of accelerating the switching of the victim wire when an opposite transition occurs on the aggressors and victim wire at the same time, so as to thereby reduce worst case delay and improve the signal integrity.

Abstract: The present invention provides a voltage clamping circuit which is operated in a stable manner with the simple constitution and a switching power source device which enables a high-speed operation. In a switching power source device, one of source/drain routes is connected to an input terminal to which an input voltage is supplied, a predetermined voltage to be restricted is supplied to a gate, and using a MOSFET which provides a current source between another source/drain route and a ground potential of the circuit, a clamp output voltage which corresponds to the input voltage is obtained from another source/drain route. The switching power source device further includes a first switching element which controls a current which is made to flow in an inductor such that the output voltage assumes a predetermined voltage and a second switching element which clamps an reverse electromotive voltage generated in the inductor when the first switching element is turned off to a predetermined potential.

Abstract: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.

Abstract: A phase adjustment circuit generates multiple clock signals by, for example, successively delaying a first clock signal. One of the generated clock signals is selected and output. A phase difference detector determines whether the phase of the selected clock signal and the phase of a second clock signal satisfy a given condition. The clock signal selection can changed until the condition is satisfied, either by external control by a device that monitors a signal output by the phase difference detector, or by a built-in selection signal generator. This scheme assures that two clock signals with phases satisfying the given condition are obtained, regardless of environmental factors or fabrication variations.

Abstract: A logic device with low electromagnetic interference. The logic device includes a digital logic gate, a voltage-limited circuit and a current-limited circuit. The digital logic gate provides a corresponding digital logic function. The voltage-limited circuit is connected to the digital logic gate in order to provide a fixed voltage to the digital logic gate to thus reduce an output voltage swing of the digital logic gate. The current-limited circuit is connected to the digital logic gate in order to provide a fixed current to the digital logic gate to thus reduce a transient current of the digital logic gate. Accordingly, an electromagnetic interface (EMI) caused by switching of the digital logic gate is reduced with the reduced output voltage swing and transient current.

Abstract: A clamping circuit containing a transistor and a current amplifier. The transistor is designed to turn on when the voltage at a node exceeds (falls below) a specified upper (lower) level. The current amplifier is designed to draw substantial amount of current when the transistor is turned on to clamp the voltage at the node to the desired level.

Abstract: A circuit has a voltage source, a node, a photodetector electrically coupled between the voltage source and the node, a resistor electrically coupled between the node and ground, and a voltage clamp electrically connected to the node, the voltage clamp configured to maintain a reverse bias of the photodetector above a predetermined level.

Abstract: Driver circuits and methods for operating driver circuits in automatic test equipment are provided. The driver circuit includes an output circuit operable in a dynamic mode and in a termination mode, and a mode control circuit for supplying a first current to the output circuit in the dynamic mode and for supplying a second current to the output circuit in the termination mode in response to a mode select signal. The mode control circuit may include a current multiplier and a switching circuit for switching a control current supplied to the current multiplier. In one example, the slew current supplied to the output circuit is controlled in response to the mode select signal.

Abstract: A communication system in which a reception signal can be accurately obtained from a signal transmitted over two-wire type transmission lines without any significant reduction in the communication speed. The communication system utilizing two-wire type transmission lines for transmitting transmission signals in opposite phases has a plurality of nodes connected to the two-wire type transmission lines, and each of the nodes incorporates terminating resistors acting upon the two-wire type transmission lines. A node which includes a reception circuit for receiving a transmission signal has an AC coupling circuit for extracting AC components in a transmission signal input through the transmission lines, a bias circuit for applying a bias voltage to a signal output from the AC coupling circuit and a clip circuit for clipping the level of a signal output from the bias circuit, which are provided at each of the two-wire type transmission lines.

Abstract: A digital blocking filter and filtering method are provided for a device receiving signals from a transmission line. The transmission line, which may comprise part of a complex bus system, is incompletely terminated, thereby resulting in a reflection signal within the line with transmission of a signal. The digital blocking filter includes a pulse generator for generating a masking pulse timed and of sufficient duration to substantially block at the device the reflection signal, and logic for combining the masking pulse and a received signal from the transmission line, thereby substantially blocking the reflection signal. Circuitry for handling reflection signals of various duration, as well as for substantially blocking a reflection signal on either a falling edge or a rising edge of a state change in the received signal are provided.