Abstract: A reference voltage and an input signal voltage are applied to gates of FETs each equipped with a LOCOS-drain structure, respectively, and currents according to the voltages are made to flow from a power supply voltage Vbat to drain sides through resistors and sources, respectively. The currents are made to flow in FETs to be converted to voltages. Then, both voltages are compared in a comparator. When a potential of a reference voltage input terminal in the comparator that operates with power provided by a power supply Vcc tends to rise above a predetermined level, a FET is turned on and clamps the voltage so as to suppress its potential rise.

Abstract: A configurable low voltage differential signal (LVDS) system is located on a chip, such as a programmable logic device. The configurable LVDS system includes a pair of I/O pads, an LVDS transmitter for driving a differential output signal onto the I/O pads, an LVDS receiver for receiving a differential input signal from the I/O pads, and a termination resistor coupled across the pair of I/O pads, wherein the termination resistance can be enabled for use with either the LVDS transmitter or the LVDS receiver. Control circuitry is provided to control the selective enabling and disabling of the LVDS transmitter, the LVDS receiver and the termination resistance. This control circuitry can be configured in response to configuration data values stored on the chip.

Abstract: A transceiver circuit includes driver circuits, receiver circuits, and suspend-mode buffers that are arranged to withstand an over-voltage conditions that would otherwise damage those circuits. An over-voltage sense circuit is arranged to detect the over-voltage condition on a data line in the transceiver. Cascode devices are placed in critical points of the various circuits, while voltages are coupled to other critical points such that none of the transistor devices that are coupled to the data lines are damaged by the over-voltage condition. Selector circuits are arranged to couple the highest detected voltages to various transistor wells to prevent forward biasing parasitic diodes in the transistors. Series switching circuits are arranged to break critical conduction paths during the over-voltage condition. The over-voltage protection scheme is suitable for use in integrated USB transceivers.

Abstract: A dynamic clamp 200 selectively clamps overshoot on a signal line 100 when overshoot is likely, while not clamping the received signal at times when overshoot is not likely encountered. A Driver Disable signal 102 disables the output of an output driver 110 so that it presents a high impedance to the signal line 100. An activation element 310 asserts a Clamp Enable signal 311, for example, in response to a transition of the received signal that occurs, for example, during a period in which a corresponding Driver Disable signal 102 is asserted. A deactivation element 320 asserts a Clamp Disable signal 321, for example, a predetermined deactivation delay period after the Clamp Enable signal 311 is asserted. A clamping portion 330 selectively clamps the received signal 100 beginning with the assertion of the Clamp Enable signal and ending with the assertion of the Clamp Disable signal.

Abstract: Disclosed is a high voltage decoupling capacitor-biasing circuit with no dc current. In one embodiment, the circuit includes a power supply node, a ground node, a common node, a first p-channel FET, a first n-channel FET, and a common node biasing circuit. The first p-channel FET includes a source, gate, and drain, wherein the source and drain of the first p-channel FET are coupled to the power supply node, and wherein the gate of the first p-channel FET is coupled to the common node. The first n-channel FET includes a source, gate, and drain, wherein the source and drain of the first n-channel FET are coupled to the ground node, and wherein the gate of the first n-channel FET is coupled to the common node. The common node biasing circuit is coupled between the power supply and ground nodes. The common node biasing circuit is configured to maintain the common node at a predetermined voltage above ground by charging up or charging down the common node.

Abstract: A wireless user terminal (42) and system (40) implementing a mixed signal CODEC (100) including an improved sigma-delta ADC (18) which limits input signals into a switched capacitor configuration and avoids adding circuit overhead in the signal path is disclosed herein. This sigma-delta analog-to-digital converter (18), having an input signal and an output signal, includes a switch (sw1), a clipping circuit (20), and a known sigma-delta ADC (34). It solves the clipping signal problem by limiting the signal right at the input of the sigma-delta ADC (34). The clipping circuit (20) couples to the switch (sw1) and the sigma-delta ADC (34) for switching the voltage applied to the sigma-delta ADC between the input signal (vin) and at least one threshold voltage (Vn and Vp).

Abstract: A circuit for controlling a bitline during a memory access operation is provided. The circuit includes a plurality of sub-arrays with each sub-array having a plurality of memory cells. Each of the memory cells is coupled to respective bitline columns. The circuit further includes a sensed output from one of the bitline columns, and a global bitline coupled to a same respective bitline column of each of the plurality of sub-arrays. Each global bitline includes a voltage swing limiter for limiting a voltage swing of the global bitline, and an n-type transistor. The n-type transistor has a gate, a first terminal, and a second terminal. The gate is coupled to the sensed output, the first terminal is coupled to the global bitline, and the second terminal is coupled to the voltage swing limiter.

Abstract: The Disclosed is a boosting circuit. A boosting voltage (VBOOT) is rapidly increased to a given voltage level in two steps by using a preboosting circuit unit and a bootstrap circuit unit. The boosting voltage (VBOOT) is dropped through a clamp circuit unit to generate a final target voltage. Therefore, it is possible to make fast read access time in a read operation, minimize consumption of current and generate a stabilized word line voltage (W/L).

Abstract: Power supply voltages are selectively modulated to correspond with degraded input voltages to a logic device. Modulated power supply voltages are provided to transistors within the logic device, so that the degraded input voltages supplied to the transistors are sufficient to turn the transistors substantially on or off. Leakage currents are prevented thereby from flowing across the transistors.

Abstract: An input buffer comprises: a pull-up transistor connected between a power supply voltage and an input pad and having a gate to which a control voltage is applied, and a substrate to which a floating well voltage is applied; a transmission transistor having a gate to which the power supply voltage is applied and a substrate connected to a ground voltage, and transmitting a signal applied to the input pad; a buffer generating an input signal by buffering the signal applied to the transmission transistor; and a control circuit generating a voltage applied to the input pad as the control voltage and the floating well voltage when a high voltage is applied to the input pad, generating the ground voltage as the control voltage and the power supply voltage as the floating well voltage in the case where a voltage less than the high voltage is applied to the input pad.

Abstract: The input/output circuit of the present invention includes a first p-channel transistor and a charge drawing circuit. The first p-channel transistor is connected to an input/output pad of the semiconductor integrated circuit. The charge drawing circuit, driven with a control signal, draws a charge from an n-well diffusion region of the p-channel transistor during output. By the charge drawing, the potential at the n-well diffusion region of the p-channel transistor is kept at the supply voltage during output, and thus the input/output circuit is prevented from deterioration in current flow capability due to a back bias effect.

Abstract: In the clamp circuit, the first transistor shifts a target clamp voltage by a gate-source voltage to output the target clamp voltage. The buffer circuit inputs the shifted voltage and output a reference voltage on the inputted shifted voltage. The gate of the second transistor is connected to the output terminal of the buffer circuit. The source of the second transistor is connected to the input terminal of the first transistor. In this structure, the reference voltage is supplied to the gate of the second transistor so that, when a terminal voltage of the input terminal of the IC is not less than a clamp voltage corresponding to the sum of the reference voltage and a threshold voltage of the second transistor, the second transistor turns on, whereby the terminal voltage is clamped to a clamp voltage related to the target clamp voltage.

Abstract: A clipping circuit (20) for clipping an input signal to a level corresponding to a regulated power supply voltage (AVDD). The clipping circuit (20) includes a current mirror-like arrangement having a reference transistor (30) and a mirror transistor (32) The input signal (BDATA) is received at the drain of the mirror transistor (32), with the source of the mirror transistor (32) producing the output signal (CLPBDATA). The reference transistor (30) receives a bias current (IBIAS) that is mirrored by the mirror transistor (32) to limit the pull-up drive of the mirror transistor (32) in pulling up the output (CLPBDATA). Disclosed embodiments of the clipping circuit (20; 20′, 20″) include a current source (29) for producing a DC bias current (IBIAS), and a charge pump (34) for producing a transient bias current (IPUMP).

Abstract: System and methods are provided for monitoring circuit performance and correcting for variations in current reference signals to maintain a desired Voltage Output Differential (VOD) between the two differential output signals. A voltage signal associated with VOD is compared to a signal that is set to a desired voltage level based on a desired VOD. By determining whether the VOD level is higher or lower than the desired level, adjustments are made to at least one of an output current source level and an output current sink level. An increase in the source and sink currents at the output results in an increased VOD, while a balance decrease in the source and sink currents results in a decreased VOD.

Abstract: The clamp circuit clamps an input voltage at prescribed higher and lower clamp voltages which are stabilized under a temperature fluctuation. Transistors Q12 and Q14 are switched on in their linear region. In a lower voltage clamp circuit 18, an Vin detecting circuit 20 outputs Va1 by level-shifting Vin by Q13 and voltage-divides by series resistance circuit 23 the level-shifted Vin, while a reference voltage generating circuit 21 outputs Vr1 by level-shifting 0 V by Q15 and voltage-divides by series resistance circuit 25 the level-shifted voltage. Q11 is switched on, when a comparator 22 determines that Va1 descends and goes across Vr1. Here, Q12 is of the same characteristics as Q14, while Q13 is of the same characteristics as Q15. Further, the resistance of the circuits 23 is the same as that of the circuit 25. The higher voltage clamp circuit 19 is similar to the circuit 18.

Abstract: The present invention relates to a boosting circuit. A boosting voltage (VBOOT) is dropped to a given voltage level through a pre-select clamp circuit and the boosting voltage (VBOOT) is again dropped through a clamp circuit, depending on the power supply voltage, so that a final target word line voltage is generated. Accordingly, a read access time is rapid upon a read operation, the current consumption is minimized and a stabilized word line voltage can be generated.

Abstract: An active load circuit for automatic test equipment that tests integrated circuits. The active load circuit includes a current source; a current sink; a current switching switching circuit having current source and current sink nodes respectively connected to the current source and the current sink; and a control circuit for controlling the current switching circuit with a differential voltage that is limited in amplitude and of the same polarity as a voltage difference between a fixed reference voltage and a pin output voltage of a device under test.

Abstract: A circuit and a method for limiting a voltage to a specified value (e.g., a rail voltage) without clipping thereby includes a pair of MOSFETs that turn on when a specified bias voltage is reached to either add to or sink current from the input node of the resistive load responsive to fluctuations in current going through the output resistive load to maintain a constant current through it. A plurality of biasing circuits is provided that control the turn on voltage levels for the MOSFETs to achieve the desired operation. The biasing circuits include circuit components that are matched to circuit components within the circuitry that adds and drains current to the output resistive load including a resistive load that matches the output resistive load.

Abstract: A protection circuit for a transmission gate having a PMOS transmission gate transistor and an NMOS transmission gate transistor coupled between a core circuit and an I/O pad. Biasing transistors are coupled to gates of the NMOS and PMOS transmission gate transistors to turn them on during normal operation. A protection circuit will turn off the NMOS and PMOS transmission gate transistors when the voltage at the pad exceeds the supply voltage by more than a threshold amount. This protection circuit includes a first protection transistor coupled between the gates of the biasing transistors and the pad to turn the biasing transistors off when the voltage on the pad exceeds the supply voltage by more than the threshold amount.

Abstract: In one embodiment of the invention, a clamping circuit clamps an input signal to reduce overshoot and ringback. A pulse generator generates a pulse signal having a pulse interval from the input signal and a delayed signal. The input signal transitions from a first level to a second level. The delayed signal is derived from the input signal. A controller generates a control signal responsive to the pulse signal. A switching circuit clamps one of the overshoot and the ringback of the input signal within the pulse interval upon receipt of the control signal.

Abstract: In the clamp circuit, the first transistor shifts a target clamp voltage by a gate-source voltage to output the target clamp voltage. The buffer circuit inputs the shifted voltage and output a reference voltage on the inputted shifted voltage. The gate of the second transistor is connected to the output terminal of the buffer circuit. The source of the second transistor is connected to the input terminal of the first transistor. In this structure, the reference voltage is supplied to the gate of the second transistor so that, when a terminal voltage of the input terminal of the IC is not less than a clamp voltage corresponding to the sum of the reference voltage and a threshold voltage of the second transistor, the second transistor turns on, whereby the terminal voltage is clamped to a clamp voltage related to the target clamp voltage.

Abstract: A DC voltage bus clamp includes a transistor, a resistor, and a diode. The transistor is placed in parallel with a load. The resistor is connected across a bridge rectifier. A gate or base of the transistor is connected to the resistor. The anode of the diode is connected to ground and the cathode is connected to the gate or base of the transistor. A hysteresis circuit may be added to form a second embodiment of the DC voltage bus clamp to trigger the transistor suddenly. A third embodiment of the DC voltage bus clamp includes a resistor sensing circuit. The diode of the first embodiment is replaced with a sense resistor. The resistor sensing circuit is connected between the sense resistor and the transistor.

Abstract: Systems and methods are disclosed for a clamping circuit for protecting against voltage overstresses. One embodiment of the system comprises a first voltage comparator adapted to detect when a selected voltage exceeds a first predetermined voltage and a second voltage comparator adapted to detect when the selected voltage falls below a second predetermined voltage, thereby preventing voltage overstresses.

Abstract: A voltage differential sensing circuit and methods of operation are disclosed for use in a memory device. The sensing circuit utilizes the inherent delay during sensing, i.e., the period between when an enable signal is enabled and when data is valid, by pulling a node of a transition logic circuit to a midpoint voltage. As the node of the transition logic circuit starts at a midpoint voltage, the voltage swing to valid data is faster because the output no longer needs to swing from rail to rail as before.

Abstract: A switching device (20) is formed to generate a ramp voltage by using a capacitor (48) formed on the semiconductor die (90) with the switching device (20). The switching device (20) drives a high-power device to conduct load currents for a load. The ramp voltage is used to gradually increase the drive that is applied to the high-power device in order to gradually increase the current conducted by the high-power device.

Abstract: An apparatus for conditioning an output waveform delivered from a testing device produces an output voltage that is the sum of a control voltage and an input voltage. To that end, the apparatus includes an input for receiving the input voltage, and an output capable of producing the output voltage. The output is coupled with the testing device. The apparatus further includes a voltage element coupled between the input and the output, and a switching element to alternatively charge and discharge the voltage element. The switching element controls the voltage element to change the control voltage between a first voltage and a second voltage. Consequently, the output voltage is the sum of the control voltage and the input voltage.

Abstract: Systems and methods are provided for limiting voltage to low-voltage devices employing a high-voltage supply. The systems and methods employ voltage limiting devices to bias cascode devices. The cascode devices are serially connected from a high-voltage supply to a low-voltage node. The voltage limiters are serially connected from the high-voltage supply to ground to bias the cascode devices. Current sources are connected in parallel with the voltage limiters except the one connected to ground. If the current sources are set to deliver substantially equal currents, then the order in which the cascode transistors are biased becomes nondeterministic, but the circuit continues to finction and the overall supply current is thereby minimized.

Abstract: A comparator, having an offset of 0.1V, compares a terminal voltage Vin1 with a clamp voltage VCL (5.1V). When an overvoltage input exceeding the VCL is entered to an input terminal, the comparator turns on a transistor Q11. The current flows across an externally provided resistor R11, the input terminal, and the transistor Q11, and flows into an output terminal of an operational amplifier. With a voltage drop at the resistor R11, the terminal voltage Vin1 starts decreasing toward an output voltage Vc of the operational amplifier.

Abstract: A method and an apparatus for turning off a cascode circuit comprising a series circuit formed by a low-blocking-capability and high-blocking-capability semiconductor switch, are described. When a turn-off command arrives, the gate voltage of the low-blocking-capability semiconductor switch is controlled in such a way that its drain voltage is held constant in the active range of the low-blocking-capability semiconductor switch. Consequently, an impermissible overvoltage at high potential of the cascode circuit at low potential is detected and actively limited.

Abstract: A level adjustment circuit of the present invention includes a MOS transistor for pulling up an output node, a first inverter for inputting an output data signal and outputting a gate control signal for controlling a gate electrode of the MOS transistor, and a second inverter connected to the MOS transistor between the first and second electrodes for inputting the first node obtained based on the output data signal, and outputting the output node.

Abstract: A method and apparatus that restrict the differential output voltage (VOD) for an LVDS input buffer is provided. Specifically, VOD is prevented from exceeding a predetermined threshold. The input and output common-mode voltage, as well as the input and output differential voltage swing, are maintained during the VOD restriction. The VOD restriction reduces output jitter of the LVDS input buffer and provides a more robust LVDS system as compared to an LVDS system not using a VOD restriction circuit. Clamping circuits are used to restrict the VOD. Each half of the differential output voltage may be clamped to restrict the differential output voltage. The clamping circuits are activated in response to the VOD reaching the predetermined threshold. When a clamping circuit is active, an alternate current path is provided maintaining the level of the signal before clamping.

Abstract: A multichannel receiver circuit is provided, which suppresses effectively crosstalk or interference between the electric signals transmitted in parallel through multiple channels at high speed and which improves the S/N for each channel. The receiver circuit comprises first to n-th sections for forming respectively first to n-th channels, where n is an integer greater than unity. The first to n-th sections receive first to n-th electric input signals to produce first to n-th electric output signals, respectively, where each of the first to n-th output signals having different logic levels according to a corresponding one of the first to n-th input signals. Each of the first to n-th sections includes an output level fixer circuit that produces an output signal. The output signal of the output level fixer circuit having a fixed level that induces no oscillation when a corresponding one of the first to n-th input signals has a level less than a specific reference level.

Abstract: A circuit and a method for limiting a voltage to a specified value (e.g., a rail voltage) without clipping thereby includes a pair of MOSFETs that turn on when a specified bias voltage is reached to either add to or sink current from the input node of the resistive load responsive to fluctuations in current going through the output resistive load to maintain a constant current through it. A plurality of biasing circuits is provided that control the turn on voltage levels for the MOSFETs to achieve the desired operation. The biasing circuits include circuit components that are matched to circuit components within the circuitry that adds and drains current to the output resistive load including a resistive load that matches the output resistive load.

Abstract: A comparator, having an offset of 0.1V, compares a terminal voltage Vin1 with a clamp voltage VCL(5.1V). When an overvoltage input exceeding the VCL is entered to an input terminal, the comparator turns on a transistor Q11. The current flows across an externally provided resistor R11, the input terminal, and the transistor Q11, and flows into an output terminal of an operational amplifier. With a voltage drop at the resistor R11, the terminal voltage Vin1 starts decreasing toward an output voltage Vc of the operational amplifier.

Abstract: A clamp for use with a circuit (having an output for delivering an output voltage) forms a voltage boundary for the output voltage based upon a clamp voltage. To that end, the clamp includes a clamp input for receiving the clamp voltage, a clamp transistor in communication with the clamp input, and a control transistor in communication with the output. The clamp also includes a driving source for driving at least one of the clamp and control transistors based upon the voltage at the clamp input and the voltage at the output. The output is clamped at a voltage within the voltage boundary of the clamp voltage after the clamp transistor begins being driven by the driving source.

Abstract: A current clamp circuit which can easily restrict an output current externally in an output current amplifier circuit using a current buffer IC, is provided. The current clamp circuit 10 restricts the output current in the output current amplifier circuit 20 for amplifying the output current by using the operational amplifier 2 and the current buffer IC 1, wherein the resistor 4 is connected to the output terminal of the current buffer IC, and the output current restriction unit for restricting the output current is connected to the current buffer IC 1 and the resistor 4 in parallel.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes a bias voltage source. The bias voltage source is coupled to a pad of the integrated circuit so as to clamp the pad voltage to the bias voltage when, during circuit operation, the voltage of the pad exceeds an upper voltage rail of the integrated circuit.

Abstract: A mixed signal CODEC including an improved sigma-delta ADC (20) which limits input signals into a switched capacitor configuration and avoids adding circuit overhead in the signal path is disclosed herein. Additionally, it avoids overshoot and settling problems. This sigma-delta analog-to-digital converter (20), having an input signal and an output signal, includes a switch (sw1), a clipping circuit (21), and a known sigma-delta ADC (34). It solves the clipping signal problem by limiting the signal right at the input of the sigma-delta ADC (34). The clipping circuit (21) couples to the switch (sw1) and the sigma-delta ADC (34) for switching the voltage applied to the sigma-delta ADC between the input signal (vin) and at least one threshold voltage (Vn and Vp).

Abstract: A CMOS bus switch (20) having undershoot protection circuitry (22) to help prevent data corruption when the switch is open and the buses (A,B) are isolated from one another. A bias generator (30) sets a voltage (Bias) referenced to ground which allows the active pull-up clamp to turn on when the bus voltage goes negative. This clamp attempts to counteract the undershoot voltage and limit the Vgd or Vgs of the N-channel pass transistor (MN1) and the Vbe of the parasitic NPN transistor. Since the active pull-up clamp circuit is also over-voltage tolerant, this invention will work equally well in high, low, and mixed voltage systems.

Abstract: A voltage clamp for a failsafe buffer used in connection with an electronic device. The voltage clamp clamps a voltage present at the output terminal of the buffer only when the electronic device is powered-on, and present a high impedance when the electronic device is not powered-on. Thus, when an electronic device such as a printer, for example, is connected to a network and the device is in a powered-on state, the voltage at the output terminal of the buffer is clamped to approximately the value of the electronic device power source. When the electronic device is powered-off, a voltage present at the output of the buffer will not clamped by the voltage clamp. Instead, the buffer will present a high impedance to the network and to other electronic devices connected thereto. Consequently, when an electronic device having a failsafe buffer constructed in accordance with the present invention enters an inoperable state due to device failure, power loss, etc.

Abstract: Accuracy of correction of offset drift with temperature and noise are corrected in a high voltage, high current amplifier is improved by thermal isolation and/or temperature regulation of another amplifier having greater gain and connected to a different power supply in a closed loop feedback servo system. A clamping network connected to the higher gain amplifier to avoid hard saturation due to transient feedback signals from a reactive load, especially an inductive load, also prevents hard saturation of the high voltage, high current amplifier. An adjustable feedback circuit connected to the higher gain amplifier allows adjustment to obtain critical damping of a second order system and faster response to achieve proportionality of output current to input voltage with an accuracy of very few parts per million error and with minimum settling time.

Abstract: A regulated-cascode amplifier circuit comprising a positive sub-line, a negative sub-line, a first auxiliary amplifier, a second auxiliary amplifier and a clamping circuit. The positive sub-line has a positive output terminal and the negative sub-line has a negative output terminal. The positive and negative sub-line each has a cascode transistor structure. Each auxiliary amplifier includes a positive input terminal, a negative input terminal, a positive-bias output terminal and a negative-bias output terminal. The clamping circuit includes a first diode and a second diode. The front terminal of the first diode is electrically connected to the end terminal of the second diode. The front terminal of the second diode is electrically connected to the end terminal of the first diode. In addition, each auxiliary diode is connected to a clamping circuit such that the positive-bias output terminal and the negative-bias output terminal are connected to the two terminals of the diode clamping circuit respectively.

Abstract: An active pull-up circuit for connection to an input pin that receives high and low logic level signals and a high voltage signal whose level is higher than the high logic level. The active pull-up circuit includes a pull-up circuit that is coupled between the input pin and a voltage supply line, and a breaking circuit that is coupled between the pull-up circuit and the voltage supply line. The pull-up circuit selectively brings the input pin to the level of the voltage supply line, and the breaking circuit operates to inhibit the pull-up circuit when the high voltage signal is on the input pin. In a preferred embodiment, the breaking circuit inhibits the pull-up circuit by electrically isolating the pull-up circuit from the voltage supply line. A method for selectively pulling-up an input node is also provided.

Abstract: A method and apparatus for accelerating the transmission of signals across an interconnect wire of an integrated circuit is presented. According to the method, a minimum charge level is maintained on the wire when it is driven to a low voltage level and a maximum charge level is maintained on the wire when it is driven to a high voltage level. In accordance with the apparatus of the invention, the minimum and maximum charge levels are maintained on the wire using a pair of clamping circuits which clamp the voltage level on the receiving end of the wire to a respective minimum voltage level and maximum voltage level. Accordingly, when the interconnect wire is driven to a high voltage level at a driven end of the wire, the charge level on the receiving end of the wire is already at a minimum level, resulting in less delay time to charge the wire to a high voltage level.

Abstract: A high-side, low-side driver that controls voltage from a voltage source to an inductive or resistive load includes a power transistor with a gate, a source and a drain. The driver is configured in a high-side configuration when the load is connected between the source and ground and the drain is connected to the voltage source and in a low-side configuration when the load is connected between the drain and the voltage source and the source is connected to ground. A gate drive circuit turns the power transistor on and off. The positive clamp circuit is connected to the drain and the voltage source. The positive clamp circuit provides a recirculation path for inductive energy that is stored in the inductive load when a loss of reverse battery condition occurs or when ground is lost.

Abstract: When a semiconductor integrated circuit device is reset, an input and output node is to be pulled down or up for stability of the integrated circuit, wherein a series combination of a pull-down resistor/pull-up resistor and a switching transistor is integrated on the semiconductor chip in such a manner as to permit the switching transistor to flow electric current through the pull-down/pull-up resistor only when the semiconductor integrated circuit device is reset, thereby enhancing the stability without sacrifice of the power consumption.

Abstract: An active termination circuit having a selective DC power consumption for clamping signals on a bus in an electronic device is described. The active termination circuit is configured to clamp the signals on the bus to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes bottom clamping transistors coupled to a first potential having bottom clamping transistor control nodes arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes top clamping transistors coupled to a second potential having top clamping transistor control nodes arranged for clamping the signal at about a second reference voltage. The circuit also has a variable current supply coupled to said first threshold reference transistor and said second threshold reference transistor arranged to reduce the DC power consumption of the active termination circuit as needed.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage as well as stabilizing capacitors for stabilizing control node voltages.

Abstract: An active termination circuit for clamping signals on a bus in an electronic device is described. The active termination circuit is configured to clamp the signals on the bus to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes bottom clamping transistors coupled to a first potential having bottom clamping transistor control nodes arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes top clamping transistors coupled to a second potential having top clamping transistor control nodes arranged for clamping the signal at about a second reference voltage.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage.