Abstract: An active termination circuit having localized potential supplies for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first localized potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second localized potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device in a tri-state mode is described. The active circuit includes a tri-state output buffer and a bottom clamping transistor coupled to GND and the tri-state output buffer having a bottom clamping transistor control node arranged for clamping the signal at about GND. A bottom threshold reference transistor coupled to a first reference voltage supply configured to supply a first reference voltage. The bottom threshold reference transistor provides a first bias voltage to the bottom clamping transistor control node that biases the bottom clamping transistor control node at about a first threshold voltage above GND where the first threshold voltage represents a threshold voltage of the bottom clamping transistor.

Abstract: A transient negative voltage pump circuit pumps the ESD voltage to a negative voltage. The negative voltage with the ESD voltage are used for early triggering of an SCR structure on the integrated circuit. In one version of the present invention, a pn junction diode of the SCR device is used as part of the negative voltage pump circuit. This saves the layout area while improving the ESD performance. The present invention improves the ESD performance of an SCR ESD protection circuit which is used for protecting the power bus or an IC pin during an ESD event.

Abstract: A structure for protection against electrostatic surges having two input terminals and two output terminals. The output terminals of the structure are connected to the inputs of a circuit to be protected. A first input terminal is connected to a first output terminal via an impedance. The second input terminal is connected to the second output terminal. The input terminals are interconnected by a first avalanche diode. The output terminals are interconnected by a second avalanche diode having the same biasing as the first avalanche diode.

Abstract: A low-voltage differential signaling (LVDS) output buffer has an improved eye pattern. The LVDS buffer has two parallel stages. A primary stage generates enough current to generate a first voltage drop across a load resistor. At higher frequencies, parasitic capacitive coupling reduces this first voltage drop, closing the eye pattern. A boost stage generates an additional boost current through the load resistor, adding to the voltage drop and opening the eye pattern. The boost stage is coupled to the outputs by link transistors that are enabled by a pre-emphasis signal generated by resetable pulse generators. When outputs switch, the pre-emphasis signal pulses the link transistors on, adding the boost current. At high frequencies, the pulse generators are reset before the pre-emphasis signal ends. The boost current is continuously added at high frequencies, but at low frequencies the boost current only occurs during the pre-emphasis period after outputs switch.

Abstract: One end of a current source transistor is connected to a standard power source (VDD), and the gate of the first current source transistor is applied with a bias potential B1 for stabilizing fluctuations in current. The gate of a current source transistor is connected to the other end of the current source transistor, and the other end of the current source transistor is connected to GND. Output NMOS transistors are connected in series between the current source transistors. Output NMOS transistors are connected in series between the current source transistors, while the output NMOS transistors are connected in parallel with said the output NMOS transistors. An output terminal is provided between the output NMOS transistors, and an output terminal is provided between the output NMOS transistors. A terminal resistance is provided between the output terminals. Output NMOS transistors and NMOS transistors, which compose clamp circuits, are provided at both ends of the terminal resistance.

Abstract: An apparatus including an overvoltage protection circuit is provided that comprises an input terminal configured to convey an input voltage, an output terminal configured to convey an output voltage, a buffer circuit, coupled between the input terminal and the output terminal, configured to receive and buffer the input voltage and in accordance therewith provide the output voltage, and a voltage sensing circuit, coupled to the input terminal and the buffer circuit, configured to sense the input voltage and in accordance therewith maintain the buffer circuit in a predetermined voltage range.

Abstract: A multi-phase charge pump continuously pumps to establish a DC voltage outside the range of supply and reference voltages. The multi-phase charge pump in one embodiment includes four stages operating in a ring with a four-phase clock. Each stage includes a three-mode charge pump that generates and provides reset and control signals to other stages. Each stage includes a pass transistor having a gate driven in excess of the DC voltage for efficient transfer of charge. The gate drive signal from a first stage is coupled to a next stage in the ring where it is used to generate the next gate drive signal. Each gate drive signal corresponds to one waveform having a phase skewed in time so that each stage in the ring is operating in a different mode. In a method of use, a first stepped voltage is developed on a first capacitor and selectively coupled to a second capacitor to develop a second stepped voltage of greater absolute value.

Abstract: A switching device includes a phase controlling circuit (801) which shifts and outputs a phase of a command signal, and a plurality of switching units (110) connected in parallel between a power supply (101) and a load (102).

Abstract: A boost level clamping circuit and a method for clamping a boosted wordline voltage from a booster circuit used in a semiconductor memory device is provided which is power supply and process corner independent. The clamping circuit is formed of a plurality of parallel-connected clamp stages connected to the boosted wordline voltage from the booster circuit. Each of the plurality of clamp stages serves to clamp the boosted wordline voltage at different predetermined levels. Each of the clamp stages is formed of a sampling circuit, a comparator circuit, a pulse generator circuit, and a pull-down circuit.

Abstract: The input circuit of the present invention includes an NMOSFET. One terminal of the NMOSFET is connected to an input terminal and the gate of the NMOSFET is connected to a power supply terminal via a clamping circuit. A signal, received at the one terminal of the NMOSFET with an amplitude equal to or larger than that of a power supply voltage, is output through the other terminal of the NMOSFET with an amplitude equal to that of the power supply voltage. The input circuit further includes: a gate controller, which is connected to the other terminal of the NMOSFET; and a PMOSFET. One terminal of the PMOSFET is directly connected to the other terminal of the NMOSFET and the gate of the PMOSFET is also connected to the other terminal of the NMOSFET via the gate controller. If the voltage at the other terminal of the NMOSFET is at a high level, the gate controller turns the PMOSFET ON. Alternatively, if the voltage at the other terminal of the NMOSFET is at a low level, the gate controller turns the PMOSFET OFF.

Abstract: A signal-transmission system includes signal-transmission lines connected to a terminal voltage via terminal resistances, open-drain-type transistors outputting signals to the signal-transmission lines, branch lines stemming from the signal-transmission lines to connect the open-drain-type transistors with the signal-transmission lines, and insertion resistances inserted in the branch lines in proximity of the signal-transmission lines.

Abstract: The present invention provides an integrated circuit having an operating voltage adaptable buffer, capable of operating in different voltage signaling environments, which includes a control circuit that provides a clamping function to the signaling path under prescribed operating conditions and which also reliably biases the p-type transistor substrate voltage of the buffer to the most positive voltage seen by the buffer under all operating conditions occurring on the signaling path, thereby protecting the p-type transistors.

Abstract: It is common that the presence of a defect causes abnormal gate output voltage excursions in data buffers, AND gates, OR gates and multiplexers in current-mode logic circuits. A voltage excursion is detected by a voltage excursion detection apparatus which includes a built-in detector. The detector, which is little overhead, is used to monitor output swings of all gates (differential circuits) and flags all abnormal voltage excursions. These detection results cover classes of faults that cannot be tested by stuck-at testing methods only. The voltage detection apparatus works well below "at-speed" frequencies.

Abstract: An active termination circuit for terminating a transmission line in memory bus, which might include a plurality of devices. The active termination circuit is configured to clamp a voltage level on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a first clamping transistor coupled to a transmission line terminal and a first terminal. The transmission line terminal is configured to be coupled to the transmission line in the electronic device. The first terminal is configured to be coupled to the first reference voltage level in the electronic device. There is included a second clamping transistor coupled to the transmission line terminal and a second terminal. The second terminal is configured to be coupled to the second reference voltage level in the electronic device. There is also included a first threshold reference device coupled to the first clamping transistor.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: two transistors coupled together in the integrated circuit so that upon the application of complementary voltage signals, electrical charge is substantially evenly distributed between output nodes. Briefly, in accordance with one more embodiment of the invention, an integrated circuit includes: a charge recycle circuit including two transistors. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a charge recycle circuit including a first and second transistor coupled so as to respectively receive complementary voltage signals at the control voltage port of the first and second transistors. The transistors have a threshold voltage level different from the threshold voltage level of other transistors coupled to the charge recycle circuit.

Abstract: A voltage limiting circuit for fuse technology. The voltage limiting circuit is coupled to the two terminals. The voltage limiting circuit is responsive to a fuse blow through a low impedance sensing circuit, and then minimizes the voltage across the fuse gap that is created by the fuse blow. Thus, the invention prevents dendritic growth and corrosion in copper or similar types of fuses.

Abstract: An interface in accordance with IEEE 1284 has a signal output stage which is a totem pole circuit. The totem pole circuit may be damaged if its output signal line is left grounded for an extended period of time or if outputs are being delivered at both ends of the signal line. Drive by the totem pole circuit is limited to a case where a signal to be output is at a low level and to a length of time equivalent to, say, one clock period from the moment the signal makes a transition from the low to a high level. A high impedance is established at all other times during which the high level is in effect, with the high level being maintained by a pull-up resistor connected to the output signal line. As a result, the totem pole circuit will not be damaged even if the output line is grounded while at the high level.

Abstract: A clamping circuit useful in reducing ringing on a transmission line is described. The clamping circuit includes a pair of transistors coupled between the transmission line and opposite terminals of a voltage source. An enable circuit monitors the transmission line for transitions, both low-to-high and high-to-low, and enables the transistors to be biased such that they connect the transmission line to the voltage source in the presence of ringing.

Abstract: An output buffer interfaces a digital system having devices designed for low operating voltages to an output coupled to an external system having higher operating voltages. The output buffer drives the output to one of a high output voltage and a low output voltage while limiting voltage across terminals of devices within the output buffer. The output buffer includes a pull-up stack of a first plurality of devices, coupled between a high power supply and the output, which turn on when the output is driven to the high output voltage and which turn off when the output is driven to the low output voltage. The voltage difference between the output and the high power supply is distributed across the first plurality of devices when the output is driven to the low output voltage.

Abstract: An output amplitude regulating circuit comprises a first MOS differential circuit, with a first MOS transistor connected between an output terminal of the first MOS differential circuit and a power supply. The circuit also includes a second MOS differential circuit having a first input terminal that receives a reference electric potential, and a second MOS transistor that is connected between the power supply and a second input terminal of the second MOS differential circuit, and is connected to a reference electric potential via a third MOS transistor and a current source. In the circuit, output terminals of the first and second MOS transistors are used to regulate an output amplitude from the output terminal of the first MOS differential circuit.

Abstract: A system and method for providing a high speed differential receiver circuit is disclosed. The system comprises a source device. A receiver is coupled to the source device. The receiver receives first and second differential signals at a first input and a second input and provides first and second output signals at a first output and a second output. The system also comprises a first plurality of load devices coupled to the first output. The first plurality of load devices control a first voltage swing at the first output. The system also comprises a second plurality of load devices coupled to the second output. The second plurality of load devices control a second voltage swing at the second output.

Abstract: A multi-phase charge pump continuously pumps to establish a DC voltage outside the range of supply and reference voltages. The multi-phase charge pump in one embodiment includes four stages operating in a ring with a four-phase clock. Each stage includes a three-mode charge pump that generates and provides reset and control signals to other stages. Each stage includes a pass transistor having a gate driven in excess of the DC voltage for efficient transfer of charge. The gate drive signal from a first stage is coupled to a next stage in the ring where it is used to generate the next gate drive signal. Each gate drive signal corresponds to one waveform having a phase skewed in time so that each stage in the ring is operating in a different mode. In a method of use, a first stepped voltage is developed on a first capacitor and selectively coupled to a second capacitor to develop a second stepped voltage of greater absolute value.

Abstract: A level shifter interfaces a digital system having devices designed for low operating voltages to an external system having higher operating voltages. The level shifter is comprised of two level shifting stages. Each level shifting stage includes a pull-up stack of a plurality of pull-up devices, coupled between a high power supply and a coupling node, which turn on when the coupling node is driven to a high shifted voltage, which is substantially the voltage at the high power supply, and which turn off when the coupling node is driven to a low shifted voltage, which is substantially the voltage at a low power supply. Each level shifting stage further includes a pull-down stack of a plurality of pull-down devices, coupled between the low power supply and the coupling node, which turn on when the coupling node is driven to the low shifted voltage and which turn off when the coupling node is driven to the high shifted voltage.

Abstract: A CMOS delay circuit for differential signals is provided. By adjusting the amplitude of clamping voltages, the delay period may be adjusted to a desired level. By using a single constant current source to charge both output nodes, current consumption is reduced.

Abstract: An output buffer translates digital input signals which toggle between ground and V.sub.DDL to signals which toggle between ground and V.sub.DDH. The technology dielectric breakdown voltage limit is less than the magnitude of V.sub.DDH, such that use of a traditional output stage would subject transistors' dielectrics to voltages which exceed their dielectric breakdown limit, and would thus be damaged. Predrive circuits (40, 50) control output stage (70) transistors' (72, 78) gates, and voltage dropping circuits control output stage (70) transistors (74, 76). These control signals are generated specifically to maximize output stage transistor drive strengths, thereby minimizing output stage size. Output buffer functions when V.sub.DDL =V.sub.DDH, and its performance is V.sub.DDL independent. Temperature compensation is incorporated into the output buffer by deliberately offsetting temperature effects on output stage transistor drive strengths.

Abstract: Electro-static-discharge (ESD) protection circuits are supplied for inhibiting the destruction of buffers, drivers, logic and memory cells in Metal-Oxide-Semiconductor (MOS) devices such as a CMOS device including Static-Random-Access-Memory (SRAM). This is accomplished by tiering diodes adjacent the input of the chip and in certain specific areas internally of the chip (e.g. power supplies etc.) providing bidirectional diode protection from over-voltage.

Abstract: A microcomputer 4 responds to an instruction signal to turn the load L on or off to control the FET 2 through the drive circuit 5. The microcomputer 4 samples an electric current I.sub.L which is supplied through the A/D converter 6 and which flows in the load L at every predetermined sampling time T.sub.S and subjects the sampled electric current I.sub.L to a comparison with a known rated current value I.sub.R for the load L. When I.sub.L .gtoreq.I.sub.R is satisfied, the microcomputer 4 starts counting energizing time T. When the accumulated value of I.sub.L .times.T.sub.S is enlarged to a predetermined value S.sub.O, the microcomputer 4 turns the FET 2 off. When the detected electric current I.sub.L is larger than an upper limit I.sub.O (>I.sub.R) determined previously, the microcomputer 4 immediately turns the FET 2 off through the drive circuit 5.

Abstract: A switching circuit has switching elements for passing-through or cutting-off signals of a positive pulse, which is a rectangular pulse rising from a low level and falling after having kept a high level for a certain time as a high voltage input signal, and a negative pulse, which is a rectangular pulse falling from a high level and rising after having kept a low level for a certain time, the switching circuit being applied to a capacitive load driving device.

Abstract: A novel PNP driven NMOS (PDNMOS) protection scheme is provided for advanced nonsilicide/silicide submicron CMOS processes. The emitter of a PNP transistor and the drain of protection NMOS device are connected to an I/O pad for which ESD protection is provided by the PDNMOS. The collector of the PNP transistor and the gate of the protection NMOS transistor are connected to ground through a resistor. The source of the protection NMOS transistor is grounded. The base of the PNP transistor is connected to either a capacitor or the parasitic capacitor of the integrated circuit.

Abstract: A CMOS differential transmitter and matched receiver apparatus and method for transmitting data. The system uses a CMOS bias network to create low voltage swings and optimize the voltage offsets to compensate for variations caused by the manufacturing process, and thereby increase data transmission rates to approximately 1 gigabit per second.

Abstract: A fast, low output impedance, low-power clamp circuit for a switched complementary emitter follower includes a current mirror circuit and two transistors. In operation, high current is provided to allow for fast switching when turning off the complementary emitter follower. When the complementary emitter follower has been turned off, the clamp circuit reverts to low-power operation requiring much lower current while maintaining the complementary emitter follower in the off condition.

Abstract: An electronic circuit apparatus having a bus, a plurality of stubs branched from the bus, and a plurality of semiconductor devices having signal input/output terminals connected to the corresponding stubs. The electronic circuit apparatus includes at least one impedance circuit arranged between the bus and at least one of the stubs, and each impedance circuit has a high-pass filter characteristic. Therefore, ringing is suppressed, attenuation in the high-frequency components of a transmission signal is prevented, the definition of the signal is maintained, and transmission frequency and speed are both improved.

Abstract: A low-voltage output driving circuit capable of preventing the generation of leakage current. The circuit includes a transfer gate GT installed between the output S.sub.2 of a first CMOS inverter INV.sub.C1 and the node S.sub.1 at the gate of an MOS transistor PT.sub.3 for active pull-up. At the same time, a reference voltage V.sub.REF and a voltage level V.sub.OUT, which corresponds to the voltage level of the output line of the signal S.sub.OUT, are compared by a comparator CMP. When the voltage V.sub.OUT is lower than the reference voltage V.sub.REF, the transfer gate GT is set to the ON state, and the output of the first CMOS inverter INV.sub.C1 is sent to the gate of the transistor PT.sub.3 for active pull-up. The comparator CMP is installed so that when the voltage level V.sub.OUT is higher than the reference voltage V.sub.REF, the output of the first CMOS inverter INV.sub.C1 is prevented from reaching the gate of the transistor PT.sub.3 for active pull-up.

Abstract: A discharge control circuit is connected between an output signal line of a boot-strap circuit having an allowable output signal voltage level range and a low voltage line. If an output signal voltage level of the output signal line is within the allowable output signal voltage level range, then the discharge control circuit provides no electrical connection between the output signal line and the low voltage line and if the output signal voltage level of the output signal line exceeds the allowable output signal voltage level range, then the discharge control circuit provides an electrical connection between the output signal line and the low voltage line.

Abstract: The present invention provides a method and apparatus for improving immunity to common mode noise. The present invention prevents common mode noise from exceeding acceptable limits. The present invention is also useful to prevent common mode noise from being converted to differential mode noise by the action of parasitic diodes. One embodiment of the present invention bleeds charge off two differential lines such that the relative voltage differential is maintained, for example during a memory read, until at least one of the lines is low enough that the maximum possible upward noise (common+differential) is insufficient to turn on the parasitic diodes coupled to the positive voltage supply, leaving enough margin on the differential signal to allow a sensing circuit to accurately sense the differential signal.

Abstract: A voltage clamping circuit for a semiconductor memory device which is capable of rapidly coping with the demand of the user. The voltage clamping circuit includes PMOS transistors connected in series between an external supply voltage terminal and a node on an output line of a DC voltage generator, a control PMOS transistor having a channel connected at both ends thereof respectively to the node on the output line and a node between the second and third ones of the series-connected PMOS transistors, and a pad connected to a control electrode of the control PMOS transistor. The pad is selectively connected to a supply voltage in a first state and to a ground voltage in a second state, thereby controlling a clamping interval of the clamping means to be variable. The first state is a state requiring a longer clamping interval than that of the second state.

Abstract: The present invention relates to a static and monolithic current limiter and circuit-breaker component including, between two terminals, a one-way conduction current limiter, a sensor of the voltage between the terminals, and a mechanism for inhibiting the conduction of the current limiter when the voltage sensed exceeds a given threshold.

Abstract: A voltage-controlled transistor drive circuit includes a gate-voltage generating circuit for outputting on and off gate signal voltages in response to an input signal, switching a voltage-controlled transistor by applying the gate voltage to the gate of the voltage-controlled transistor; and a current limiting circuit limiting current flowing from the gate of the voltage-controlled transistor to the gate-voltage generating circuit when the gate-voltage generating circuit outputs an off gate signal voltage.

Abstract: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit, a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.

Abstract: Disclosed are a programmable digital device and method for generating tracking threshold signals for qualification of input peak signals in response to programmed digital gain signals which control the rate at which the envelope of the qualified input peak signals is followed, and in response to a programmed digital attenuation signal which determines the proportion of the peak envelope at which to generate new tracking threshold signals. The programmable digital device and method also provide a programmed clamp signal to clamp the positive and negative threshold signals to not fall below the programmed values. An anti-hang capability is provided to allow the thresholds to drop after a programmed time period during which no signal is detected. In an alternative arrangement, the centerline of the envelope is followed and used as the threshold.

Abstract: The voltage detection and control circuit includes a voltage detect circuit having an associated switch point greater than a first predetermined voltage, with the voltage detect circuit being responsive to an input voltage greater than the first predetermined voltage for generating an activation signal; and a clamp control circuit, responsive to the activation signal, for clamping an operating voltage to a second predetermined voltage. The second predetermined voltage may be substantially equal to the first predetermined voltage. A spike filter may be included for suppressing spikes in the activation signal. A clamp stage control circuit is provided for suppressing oscillations in the second predetermined voltage. At least one clamp stage, which may include a delay device, provides the operating voltage to a corresponding circuit component as well as reducing current peaks in the corresponding circuit component.

Abstract: An apparatus for switching an inductive load includes a MOSFET switch and provides for limiting a voltage across the load during switching-off of the latter. One or two clamping circuits are used without zener diodes and with different, temperature-independent clamping voltages for the purpose of rapid demagnetization of the load in a constant demagnetization time.

Abstract: An object is to provide a semiconductor device having an internal power supply circuit capable of supplying stable internal power supply voltage while not increasing layout area. A differential amplifying circuit in a voltage down converter controls potential level V.sub.OUT of the drain of transistor P14 such that it attains the reference potential V.sub.REF. If the potential V.sub.OUT increases, the gate potential of transistor N12 increases because of coupling function of a capacitance C2, and the transistor is rendered conductive. Thus the potential level V.sub.OUT is pulled down. By contrast, if the potential level V.sub.OUT lowers, transistor P12 is rendered conductive, and the potential level V.sub.OUT is pulled up.

Abstract: A non-inverting pass gate local wordline scheme for block architecture memory arrays is described which includes two switches connected in parallel which may be driven by complementary control signals. A clamping switch may be connected to the local wordline to clamp the local wordline to a power supply voltage at a low logic level whenever the pass gate blocks an input signal. When a particle or defect creates a short which short circuits a local wordline to a global wordline, the global wordline may be permanently disabled by pulling it LOW. Regardless of the states and/or polarities of the BLOCK and BLOCK signals, the local wordline is permanently held LOW because the pass gate is non-inverting. The present invention may thus reduce power in a memory device by preventing a row of memory cells from unnecessarily drawing unused and/or unusable current.

Abstract: A switch mode regulator circuit is provided to facilitate the conversion from one voltage level to another in a substantially power lossless manner. The circuit is particularly advantageous in instances where the power supply can be operable in a discontinuous mode, as inductor-capacitor oscillatory transients ("ringing"), along with its associated voltage spikes at the associated output transistor source, can be avoided. Such transients and their associated voltages are avoided by clamping the gate-source voltage on the circuit's output NMOS transistor over the entire positive operation voltage range.

Abstract: An op amp clamp for charging or discharging a capacitor prevents the voltage on the capacitor from going beyond a reference voltage determined by a reference clamp voltage applied to an input of a differential amplifier. The second input of the differential amplifier is connected to the capacitor. The output of the differential amplifier is provided in a feedback loop to the capacitor. The feedback loop includes a charging circuit or a discharging circuit depending upon the function of the op amp clamp. The feedback loop may be arranged with a current mirror in which current generated by the output of the differential amplifier is mirrored in the charging or discharging circuit. A signal to activate charging or discharging is applied at the output of the differential amplifier to activate or deactivate the current mirror.

Abstract: A pulse-shaping circuit comprises a current limiter, which is connected in parallel with a voltage divider, for limiting a source voltage and enabling first and second voltage signals divided by the voltage divider to be constantly maintained, and an output voltage limiter which is provided to prevent a collector voltage of an output switching transistor from being increased to more than 0.1 V, so that an output pulse signal from an output terminal thereof may be lowered nearly to about 0.1 V when a low input pulse signal is applied to an input terminal thereof.

Abstract: A driver circuit that is powered by a power supply voltage has an output terminal, and includes a pull-up transistor for pulling the output terminal up toward the power supply voltage. A voltage divider that is connected across the power supply voltage has a tap connected in circuit to an input of the pull-up transistor and includes variable resistance elements whose resistance varies together with a threshold voltage of the pull-up transistor for limiting a voltage at the output terminal to within a predetermined range that is lower than the power supply voltage.

Abstract: A circuit for limiting the output voltage from a power transistor connected in series with a resonant load between a voltage supply and a voltage reference, ground, is disclosed. The circuit includes a semiconductor junction element, in particular a diode of the SCR type, having an anode terminal connected to the voltage supply, a cathode terminal connected to a common circuit node between the power transistor and the resonant load, and a control terminal connected to a reference voltage of predetermined value. The reference voltage can be constructed by using a resistor connected in series with a diode across the voltage supply. The SCR diode is constructed using the parasitic PNP-NPN transistors which exist in the structure of the power transistor.