Abstract: A modulator has an FET output driver for applying repetitive pulses to an inductive load. A predriver comprises a resistor and capacitor in parallel across the FET source and gate for shaping the control voltage. A constant current source, turned on and off by an input signal, couples the shaping circuit to ground. The resistor and capacitor values determine the rate of control voltage change which is the same for turn-on and turn-off, to control the driver current slew rate for minimizing RFI emissions.

Abstract: When turned on by an input CONTROL signal, a MOSFET transistor switch in accordance with the present invention connects a low impedance voltage source to a moderate to high impedance load. The switch includes a relatively large first MOSFET transistor (Q1), a smaller second MOSFET transistor (Q2), a resistor and a current source. Source terminals of transistors Q1 and Q2 are tied to the voltage source. The load is connected to the drain of Q1 while the current source is connected to the drain of the Q2 and also to the gates of both transistors Q1 and Q2. The resistor links the gates of transistors Q1 and Q2 to the voltage source. When the CONTROL signal is asserted, it turns on the current source, thereby quickly turning transistors Q1 and Q2 on to connect the voltage source to the load. When the control source is de-asserted, the current source turns off. Transistors Q1 and Q2 then turn off at a controlled rate in order to minimize current injection into the load.

Abstract: A method and dynamic circuit selectively controls the amount of feedback that is supplied to the dynamic node to provide more feedback when more is needed to enhance functional operation and less feedback when less is needed to enhance performance. The additional feedback inhibits the detrimental effects of charge loss due to leakage and noise mechanisms. The circuit may, for example, selectively control the amount of feedback in response to a test signal. The test signal can be manipulated to cause the circuit to provide more feedback when the circuit is undergoing reliability stress testing and less feedback when the circuit is in normal operation as part of an electronic device.

Abstract: A low leakage solid state switch for range-changing uses a pair of low leakage diodes switched to a reference voltage to block leakage through the switch when it is in the "off" state.

Abstract: An input/output circuit with wide voltage tolerance is using a feedback circuit for increasing the voltage tolerance. A single gate oxide structure is fabricated instead of a dual gate oxide structure.

Abstract: An output buffer in accordance with the present invention exhibits a fixed output signal slew rate. The output signal behavior is independent of the capacitive load seen by the buffer. The circuit includes a capacitive feedback path from the output node to circuitry which drives the output transistors. In one embodiment, the feedback path comprises two capacitive elements, one which comes into play during a rising edge transition and the other which affects a falling edge transition. In a second embodiment, a single capacitive element is coupled to a switching circuit for use during either a falling transition or a rising transition. The second embodiment provides precharging of the output transistor gates, and so improves response time.

Abstract: A power semiconductor device (10) and a method for increasing the turn-on time of the power semiconductor device (10). The power semiconductor device (10) has a first stage (13) and a second stage (14), where the transconductance of the first stage (13) is less than the transconductance of the second stage (14). The turn-on time of the power semiconductor device (10) is increased by turning on the first stage (13) before turning on the second stage (14).

Abstract: A switching device with a power FET for switching an inductive load to which a free-wheeling diode is connected in parallel, wherein the terminal of the series resistor facing away from the gate terminal is connected to a driver circuit which is so designed that it connects the specified terminal with a reverse potential in order to block the FET, wherein, at the beginning of the process of making the FET conductive, it connects the specified terminal with a high resistance to a control voltage source that puts the FET into the conductive state, in such a way that the current rise of the current flowing through the FET is slowed down to such an extent that, within a period of time in which the free-wheeling diode is not yet blocking after starting to make the FET conductive, an increase of the current to undesirable high values is prevented, so that damage to the power FET and the free-wheeling diode and/or other circuit elements and/or the occurrence of electromagnetic disturbances is reduced, and wherein, a

Abstract: An improved output driver that minimizes source point reflections when driving a signal on a transmission line by generating a constant source impedance. The improved output driver uses a transistor switching circuit for generating a nearly constant channel impedance when transistor switching circuit is enabled and is not operating in a saturation mode. A switched diode circuit is coupled in parallel to the transistor switching circuit for generating a nearly constant source impedance when a sufficient voltage to bias the switch diode circuit is applied. Control circuitry is coupled to both the transistor switching circuit and to the switched diode circuit for enabling and disabling the transistor switching circuit and the switched diode circuit. By alternatively enabling and disabling the transistor switching circuit and the switched diode circuit the control circuit is able to generate a constant source impedance.

Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.

Abstract: Disclosed is an output signal buffer circuit of semiconductor memory devices comprises: a plurality of buffer groups each comprising a plurality of output buffers grouped into unit group, in which each output buffer comprises a pull up transistor and a pull down transistor connected between a power supply voltage and ground in series; driving means for sequentially driving respective buffer groups according to internal control signals; and control signal generating means for producing the internal control signals for sequentially driving said buffer groups to said driving means in accordance with an external control signal.

Abstract: A CMOS circuit prevents feedthrough current and has a small-scaled circuit constitution. An output stage has a P-channel MOS transistor and an N-channel MOS transistor with drains connected to each other to form an output terminal and gates respectively connected to output terminals of first and second series circuits. The first and second series circuits control supply of power and each includes an N-channel MOS transistor and a P-channel MOS transistor with drains connected together to form the output terminal and gates connected together to form an input terminal. A delay circuit receives an input signal and produces a delayed input signal which drives the input terminals of the first and second series circuits. P-channel and N-channel MOS transistors control power potentials applied to sources of the respective P-channel and N-channel MOS transistors of the second and first series circuits and are driven by the input signal which is applied to their gates.

Abstract: A digital interface circuit has two inverters with different switching points, one below and one above the nominal transition point of the circuit. Each inverter controls both pull-up and pull-down output transistors. The inverter with the low switching point controls the low-to-high signal transition, while the inverter with the high switching point controls the high-to-low signal transition. Pass gates responsive through delay elements to either the circuit input, an inverter output, or the circuit output isolate the other inverter from the output transistors. The pass gates may also be tristatable by means of a logical combination of the delayed pass gate enable signals with output enable signals. In yet another embodiment, the pair of inverters are replaced by a single inverter with dual switching points.

Abstract: A circuit comprising a first driver circuit, a second driver circuit and a delay circuit. The first driver circuit may be configured to generate a first output signal and a control signal in response to a first input signal. The delay circuit may be configured to generate a delay signal in response to a second input signal and the control signal. The second driver circuit may be configured to generate a second output signal in response to the delay signal.

Abstract: A drive circuit for a voltage controlled power switching device includes a transformer, a full-wave rectifier bridge coupled to the transformer, first and second capacitors connected in series between nodes of the full-wave rectifier bridge and first and second controlled switches coupled between a control electrode of the power switching device and the first and second capacitors, respectively, wherein each controlled switch has a control electrode coupled to a secondary winding of the trans-former. Current is provided by the first capacitor to the control electrode of the power switching device through the first controlled switch at the beginning of a negative pulse appearing at the secondary winding of the transformer and charging current is provided to the first capacitor from the secondary winding of the transformer through the full-wave rectifier bridge after the beginning of the negative secondary pulse.

Abstract: A CMOS integrated circuit regulator for mixed mode integrated circuits reduces digital switching noise through use of a clamped dual source follower circuit and a charge reservoir bypass capacitor. Relatively constant current is provided to the CMOS logic during transitions to minimize switching noise.

Abstract: An integrated circuit (10) provides analog and digital circuitry on a common substrate (12). A first digital circuit (14) operates in combination with an analog circuit (18) to perform a useful function. A second duplicate digital circuit (26) is disposed adjacent to the first digital circuit and operates out-of-phase with respect to the first digital circuit. The second duplicate digital circuit introduces voltage spikes equal and opposite to the voltage spikes introduced into the substrate by the first digital circuit. The equal and opposite voltage spikes tend to cancel and thereby minimize cross-talk between the digital and analog circuits. A guard ring (16,28) surrounds each of the first and second digital circuits and the analog circuit to reduce voltage spikes into the substrates. By minimizing cross-talk, the analog circuit operates without interference from the digital circuits.

Abstract: A signal transmission cable driver apparatus for transmitting an input signal through a transmission cable performs frequency compensation without using a peaking coil. The signal transmission cable driver apparatus includes a transmission driver for receiving the input signal and driving the transmission cable to transmit the input signal therethrough, and transition signal drive means having a capacitor circuit for detecting transition of the input signal by charge/discharge in the capacitor circuit and amplifying currents in said charge/discharge of the capacitor circuit, wherein the currents amplified by the transition signal drive means are superimposed on the input signal driven by the transmission driver at an input of the transmission cable.

Abstract: An output driver for high speed integrated circuits includes a static driver portion and a transient driver portion. The static driver size can be adjusted to satisfy the minimal requirements for maintaining output DC voltage levels. The transient drivers include a feed-back control from the output voltage node. During a transition, the transient buffer control will sense the output level and feedback to turn off the transient driver whenever the output level rises/falls across the trip point. Accordingly the di/dt noise will drop quickly once the output has reached the trip point. The transient drivers can be larger to speed up switching speed. The buffer can use single power and ground pins or multiple power/ground pins.

Abstract: An electrostatic protection circuit in a internal circuit isolated from a substrate bias which protects the internal circuit from static electricity with regard to any of three different sources of bias voltage. An electrostatic protection circuit is constructed for each source of bias voltage so that the internal circuit is protected from static electricity flowing through bonding pads of the isolated circuit. The protective circuit comprises a plurality of NMOS or PMOS transistors for protecting input/output buffers and drivers from the static electricity flowing through the bonding pads. The respective NMOS or PMOS transistors are connected to the respective source voltage terminals and the input/output drivers.

Abstract: Disclosed is an analog switch circuit which has: an analog switch which is composed of a P-channel first transistor and a N-channel second transistor whose drains are connected to each other and whose sources are connected to each other; first and second diodes which are in parallel and reversely to each other connected between a back gate of the first transistor and a high-potential power source; and third and fourth diodes which are in parallel and reversely to each other connected between a back gate of the second transistor and a low-potential power source.

Abstract: A circuit comprising a switch section configured to generate a first and second control signal. A pull section may receive the first and second control signals to generate an output. A capacitor may be coupled between the switch section and the pull section for coupling the output to the switch section.

Abstract: Semiconductor device according to the present invention includes package frame, bonding wire, pad, first internal power supply line, second internal power supply line, internal circuit, stabilize circuit, GND package frame, GND bonding wire, GND pad, and internal GND line. Bonding wire, pad, and first and second internal power supply lines function as a filter. As a result, noise generated by operation of the internal circuit is absorbed in propagating to the stabilize circuit through first internal power supply line, pad, and the second internal power supply line. Therefore, effects of noise given to the stabilize circuit are small.

Abstract: The present invention provides an input buffer circuit for reducing false transitions within a circuit. The input buffer circuit includes an input pad for receiving an input voltage, an input buffer having an input and a circuit for modifying a voltage entering the input buffer to track changes in a power supply voltage relative to a voltage at the input pad. The circuit is connected in series between the input pad and the input the input buffer.

Abstract: A bus line termination circuit for limiting signal swing on a bus line to a reduced CMOS-swing. The termination circuit includes a switch and a first resistor connected in series between the bus line and a first voltage supply, and a second resistor connected in series between the bus line and a second voltage supply. The values of the first and second resistors are selected such that a termination voltage equal to the average of the first and second supply voltages exists on the bus line. The bus line is further connected to a receiver circuit having a threshold voltage equal to the average of the first and second supply voltages. The switch is controlled to disconnect the bus line from the first voltage supply when the bus line is in an inactive state. In an alternative embodiment, a termination circuit includes one or more voltage regulator circuits, each being coupled to the first and second voltage supplies. A clamping resistor coupled each voltage regulator circuit to the bus line.

Abstract: An output buffer circuit of the present invention comprises a first input terminal receiving a first input signal, a second input terminal receiving a second input signal, a control input terminal receiving a control signal, an output terminal outputting an output signal, a first transistor coupled between the output node and a first potential source and a second transistor coupled between the output node and a second potential source. The output buffer of the present invention further includes a first gate circuit and a second gate circuit. The first gate circuit has a first input node coupled to receive the first input signal, a second input node coupled to receive the control signal, an enable input node coupled to receive the second input signal and an output node coupled to the control terminal of the first transistor. The first gate circuit outputs the signal received by the enable input node when the signals received by the first and second input nodes have predetermined level.

Abstract: A protection circuit (1) for input comprises two transistors (11, 12) connected in series between a first voltage supply (V.sub.cc) and a second voltage supply (GND), and an intermediate junction point is used as an input terminal and an output terminal. When a surge voltage is applied to the input terminal, since terminals (51, 53) of the two transistors (11, 12) are connected to predetermined junction points in such a way that the transistors can operate as bipolar transistors or cause punch through phenomenon (without causing breakdown operation of a low response speed to surge voltage), the surge voltage can be absorbed at high speed, thus increasing anti-ESD (electro static discharge) rate. Further, a protection circuit for power supply comprises two transistors (31, 32) connected in parallel to each other between a first voltage supply (V.sub.cc) and a second voltage supply (GND).

Abstract: An improved signal line routing scheme includes a plurality of dynamic signal lines disposed in parallel to each other, and a plurality of static signal lines disposed in parallel to each other and also disposed in parallel with the plurality of dynamic signal lines, wherein at least one of the plurality of static signal lines is disposed immediately adjacent to each one of the plurality of dynamic signal lines.

Abstract: A circuit provides an output signal having a portion with a constant maximum amplitude, followed by a portion decreasing down to a constant zero value when an input voltage increases from zero. The circuit includes an asymmetrical differential stage having a low gain branch and a high gain branch, respectively controlling two branches of a symmetrical differential stage. The current of the asymmetrical differential stage corresponds to the end of the decreasing portion. The current of the symmetrical differential stage corresponds to the maximum amplitude of the signal which is provided by one of the branches of the symmetrical differential stage. The high gain branch and low gain branch are respectively controlled by the input voltage and by a voltage corresponding to the beginning of the decreasing portion.

Abstract: A circuit for and a method of driving first and second power transistors arranged in series in a half-bridge configuration provides for soft turn-on of the power transistors when there is a change of state in the input voltage. When the input voltage initially changes state, the gate drive voltage of one of the power transistors is raised to a voltage barely above its threshold value for a predetermined interval. The gate drive voltage of this power transistor is then raised to the supply voltage value. When the input voltage again changes state, the transistor is turned off, and the other transistor is turned on in a similar manner. As a result, when one of the transistors is turned on, current transients in the other transistor is reduced.

Abstract: A bidirectional buffer circuit is provided with a terminal, an input buffer, a steady state output driver and a strong output driver. The input buffer is for receiving an input signal from the terminal. The steady state output driver includes a weak driver for driving the terminal to a first voltage corresponding to a first particular logic value of the output signal. The weak driver has a limited driving capacity that can be out-driven by the input signal. The strong output driver is for driving the terminal to the first voltage. The strong output driver has a greater driving capacity than the weak output driver. Enable circuitry is also provided. The enable circuitry includes at least one delay circuit with a particular delay period. The enable circuitry enables the strong output driver in response to a transition of the output signal from a complement of the first logic value to the first logic value. However, the enable circuitry only enables the strong driver during the delay period of the delay element.

Abstract: A variable capacitor for integrated circuits used as a decoupling capacitor that operates at both low and high frequencies is disclosed. Based upon a programmable input signal, the decoupling capacitance of the circuit varies within a specific range providing a vehicle for testing decoupling capacitance requirements of new integrated circuits and functions and new silicon processes. The programmable input signal switches a transistor from the saturated region of operation to the unsaturated region of operation, varying the decoupling capacitance of the transistor. By providing circuitry to control the switching of the transistor, the circuit operates at both low and high frequencies, reducing the negative impacts of transistor channel resistance during high frequency operation.

Abstract: There is disclosed an integrated circuit includes an output driver circuit providing control of transition time from one state to another. The output driver includes first and second input transistors coupled to an input node at which data is received. First and second output transistors are coupled to an output node at which the data is presented when the output driver is enabled. The first input transistor is coupled to the first output transistor defining a first node. The second input transistor is coupled to the second output transistor defining a second node. First and second switching circuits are coupled between the first node and the second node. The first switching circuit is switchable between a first state that isolates the first node from the second node, and a second state that couples the first node to the second node.

Abstract: A plurality of MOS transistors connected to each other at a substrate electrode thereof to have a substrate potential are deviation-compensated by a combination of a power source having a power source potential independent from the substrate potential, a power supply line connected to a source electrode of each of the MOS transistors, a sample circuit composed of a sampled one of the MOS transistors, detection circuitry for detecting an action of the sample circuit to provide a detection signal representing a difference between the detected action of the sample circuit and a reference action therefor, and a voltage generator connected between the power source and the power supply line, the voltage generator generating a voltage depending on the detection signal.

Abstract: A transistor T26, serving as an output circuit 42, has a collector connected to a communication line B+ and an emitter connected to the other communication line B-. A base current generation circuit 44 generates a base current Ib for actuating transistor T26 based on a transmission signal. Transistors T24 and T25 constitute a current-mirror circuit. A correction circuit 46 takes in or absorbs a current equivalent to base current Ib from the collector of transistor T26, so as to equalize the drive currents IB+ and IB- flowing through twin communication lines B+ and B-. Since only one transistor T26 is used to actuate the twin communication lines B+ and B-, it, becomes possible to completely equalize the drive currents IB+ and IB- in their absolute values and to cause no phase dislocation between these two drive currents IB+ and IB-. Hence, the radio noises can be completely canceled when generated from each of twin communication lines B+ and B- due to change of currents flowing therethrough.

Abstract: An open drain driver circuit includes first and second NMOS driver transistors, a delay circuit, an OR gate and an AND gate. Each NMOS driver transistor has a drain coupled to an output terminal, a source coupled to a supply terminal, and a gate. The delay circuit has an input coupled to the input terminal and has an output. The OR gate has a first input coupled to the input terminal, a second input coupled to the output of the delay circuit and an output coupled to the gate of the first NMOS transistor. The AND gate has a first input coupled to the input terminal, a second input coupled to the output of the delay circuit and an output coupled to the gate of the second NMOS transistor.

Abstract: Disclosed is a novel circuit technique that will significantly improve the noise margin of a passgate latch design. The circuit technique consists of a passgate latch with additional circuitry for sensing the occurrence of coupled noise and then turning on a current mirror that injects current into the latch internal node to stabilize the latch. The circuit further includes a disabling system for disabling the additional circuitry during normal operation of the passgate latch.

Abstract: A CMOS circuit includes an output unit for receiving an enable signal and an input data and producing an output signal. A transmission gate unit receives a precharge signal and the output signal from the output unit and transmits a corresponding signal in accordance with the precharge signal. A precharge unit having a data output terminal receives the corresponding signal from the transmission date unit and stores an electric charge. The precharge unit also maintains the electric charge at an intermediate level in accordance with the corresponding signal of the transmission gate unit and outputs data at the intermediate level.

Abstract: A clock generator circuit that produces clock signals at the logic signal transitions at an output in response to a sinewave input control signal derived from an oscillator includes a delay means connected in one of the inverter-amplifier stages to prevent unwanted noise-induced logic transitions at the output, thereby to reduce significantly the adverse effects of oscillator and power supply noise on the clock output signal.

Abstract: An electronic clamping circuit is provided. In one preferred embodiment, the clamping circuit includes a pair of diodes connected in series, both having the same bias, which are shunted across a feedback path of a transimpedance amplifier circuit. A capacitor is connected to a node in-between the diodes and a potential (e.g., ground). The arrangement of the diodes and capacitor serve to keep the amplifier circuit's operation within its linear limits without severely degrading its bandwidth.

Abstract: A buffer or driver circuit drives a high-capacitance clock signal line inside an integrated circuit (IC). Power is reduced by limiting the voltage swing of the clock output. The clock voltage swing is limited to within a transistor threshold-voltage of power and ground by feeding the output voltage back to the gates of the driver transistors which drive the output clock signal line. Thus the output clock swings from Vtn to Vcc-.vertline.Vtp.vertline. rather than from ground to Vcc. The limited output swing reduces dynamic power which is more critical than static power in downstream logic receiving the clock for higher-speed clocks. Crowbar current from power to ground through the driver transistors is eliminated by turning off the active driver transistor before the complementary driver is turned on. The gates of the driver transistors are charged and discharged from the clock line capacitance rather than from power and ground.

Abstract: A variable strength clock signal driver circuit and method of manufacturing the same are provided that accommodate either full or reduced drive strength of a generated clock signal. The clock driver circuit includes a package bonding option to select the desired strength of drive. Thus, the clock driver circuit may be operated at either fast or slow clock frequencies as determined by the system requirements. As a result, both high performance, high drive versions and low cost, low drive versions of a digital circuit such as a microprocessor may be provided that differ only in package bonding. The same set of masks may be used to produce either version of the circuit, thus permitting greater manufacturing flexibility and reducing cost. Furthermore, electromagnetic interference may be reduced by selecting the low drive strength option for cost sensitive applications.

Abstract: An output driver is provided for operating in a primary power supply environment to drive an output system that can have voltages associated therewith that are higher than the primary power supply level. The driver includes a pull-down N-channel (34) and a pull-up P-channel transistor (44). An output node (40) is driven by the transistor (34) and (44). An N-channel protection device (38) is disposed between node (40) and transistor (34) and an N-channel transistor (48) is disposed between node (40) and transistor (44). Transistor (38) has the gate thereof biased to the primary supply voltage level and the transistor (48) has the gate thereof biased to a voltage slightly above the primary supply voltage level.

Abstract: Power consumption, electromigration, joule heating, and voltage supply ringing are reduced in digital integrated circuits by reducing crowbar current. In one embodiment, crowbar current in a buffer circuit (71) is reduced by electrically connecting the drain region of a PMOS transistor (73), in a first inverter, to a gate electrode (84) of an NMOS transistor (79) and a gate electrode (82) of a PMOS transistor (77), in a second inverter, through a first conductive interconnect (78). In addition, the drain region of the NMOS transistor (75) in the first inverter is electrically connected to the gate electrode (84) of the NMOS transistor (79) and to the gate electrode (82) of the PMOS transistor (77), in the second inverter, through a second conductive interconnect (80). These conductive interconnects allow crowbar current, which is created during a transition between logic states, to be reduced.

Abstract: A level convertor is provided between circuits, which act with different power supply voltages, respectively, and converts a first voltage level of an output of a circuit to a second voltage level, which corresponds to an operational voltage level of another circuit. The level convertor comprises a level shift circuit, which receives the first voltage level and outputs an output of the second voltage level, and a buffer circuit, which receives the output of the second level and a control signal, and fixes the output of the second voltage level to a low logic level, when the control signal is a low logic level. The control signal may be used to set a timing for registering the data to a register, avoiding data in an instable state when power is supplied, from being registered to the register.

Abstract: An apparatus for diminishing supply and ground bounce in integrated circuits. Two separate techniques are used simultaneously to diminish the problem of ground bounce. First impedance is placed between a power source bus on the integrated circuit and an external power source; and between a ground bus on the chip and an external ground. This effectively dampens ground bounce oscillations in the power and ground leads of the chip. Secondly, capacitance is dynamically added to the pre-drive of an output buffer with a capacitance node. Dynamic digital sizing is utilized in both techniques, therefore both techniques are responsive to the changing performance variations within the chip.

Abstract: A buffer which provides compensation for the RC time delay introduced by a switch matrix of a high density programmable logic device (PLD). The buffer includes circuitry to provide an input threshold which varies to compensate for the RC delay of the switch matrix on a high to low input signal transition. The buffer further includes a negative hysteresis circuit to prevent oscillations on slow rate low to high input signal transitions.

Abstract: In a semiconductor integrated circuit device, particularly in a switch circuit, a first and a second FETs are connected in series with respect to the signal path, and a third FET is connected between the node of these first and second FETs and the ground region. Thereby, low insertion loss, high isolation, and miniaturization of the entire circuit can be realized simultaneously.

Abstract: An input buffer circuit for a frequency divider includes a bias circuit including a first group of diodes connected in series and to a power supply voltage terminal, at least first and second resistors connected in series to each other at a first junction, the first resistor being connected in series with the first plurality of diodes, and a second plurality of diodes connected in series, the second plurality of diodes being connected between the second resistor and a ground; an input signal terminal for receiving an input signal from a frequency divider; a reference input terminal for receiving a reference signal; an output signal terminal; a reference output terminal connected to the reference input terminal; an amplitude limiting circuit connected to and between the output signal terminal and the reference output terminal; third and fourth resistors connected in series to each other at a second junction, the third resistor being connected to the output signal terminal and the fourth resistor being connecte

Abstract: A row address detection circuit includes a fuse bank, including a plurality of fuses connected to a common node. A precharge circuit is connected to bias the common node at a supply voltage. The fuse bank is also coupled through an isolation circuit to a buffer circuit. Selected ones of the fuses are blown in a pattern corresponding to an address of a defective circuit to enable a redundant circuit to be substituted for the defective circuit. The isolation circuit allows the buffer circuit to measure the node voltage to determine if an input to a group of address select lines corresponds to the address of the defective circuit, yet isolates the buffer circuit from the common node to prevent partially blown fuses from placing an excessive load on the buffer circuit. In one embodiment, the isolation circuit is realized with a pair of transistors of opposite channel type coupled for synchronous switching to provide substantial isolation while minimizing voltage drop.