Abstract: A wafer having a first surface, an opposite second surface, and an outer circumferential surface that includes a curved part curved outward in a protruding manner is separated into two wafers. Part of the wafer is removed along the curved part, and a separation origin is formed inside the wafer by positioning the focal point of a laser beam with a wavelength having transmissibility with respect to the wafer inside the wafer and executing irradiation with the laser beam while the focal point and the wafer are relatively moved in such a manner that the focal point is kept inside the wafer. The wafer is separated into two wafers by an external force.

Abstract: An analog-to-digital converter (ADC) includes a modulator, an integrator circuit, and first and second differentiator circuits. The modulator has a modulator input and a modulator output. The modulator input is configured to receive an analog signal, and the modulator is configured to generate digital data on the modulator output. The integrator circuit has an integrator circuit input and an integrator output. The integrator input is coupled to the modulator output. The first differentiator circuit is coupled to the integrator output, and the first differentiator circuit is configured to be clocked with a first clock. The second differentiator circuit is coupled to the integrator output, and the second differentiator circuit configured to be clocked with a second clock. The second clock is out of phase with respect to the first clock.

Abstract: A method and apparatus that cancels or reduces DC offset in a fully-differential optical receiver. The method includes receiving differential optical signals, converting, with photodetectors, the differential optical signals to differential current signals representative of the differential optical signals, converting, using a transimpedance amplifier, the differential current signals to differential intermediate voltage signals, amplifying, using a main amplifier, the differential intermediate voltage signals to generate differential output voltage signals, and cancelling a DC component of the differential output voltage signals using a fully differential DC cancellation circuit. Output offset may also be cancelled or reduced using digital control.

Abstract: Technologies are provided for adaptive control of bias settings in a digital microphone. In some embodiments, a device includes a first component that provides data indicative of a clock frequency of operation in a functional mode of a digital microphone. The clock frequency clocks one or more microphone components having switching activity. The device also can include a second component that determines, using the clock frequency, an amount of bias current to supply to at least a first microphone component of the one or more microphone components. The device can further include a memory device that retains control parameters that include at least one of a first subset of parameters defining a relationship between current and frequency and a second subset of parameters defining a quantization of the relationship. The quantization including multiple bias current levels for respective frequency intervals.

Abstract: Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.

Abstract: An apparatus, system, and method for managing an electrostatic charge of a workpiece are disclosed. The method comprises coupling an electrostatic voltmeter to a conductor, coupling a charge-adjustment system to the conductor, and coupling the conductor to the workpiece. A level of charge in the workpiece is adjusted, via the conductor, with the charge-adjustment circuit and a voltage of the workpiece is monitored, via the conductor, with the electrostatic voltmeter. A controller may be used to adjust the charge on the workpiece based upon the monitored voltage.

Abstract: A DC-DC converter control circuit includes an error amplifier, a voltage-to-current conversion circuit, an oscillator circuit, and a pulse frequency modulation (PFM) control circuit. The error amplifier is configured to generate a difference voltage as a difference of an output voltage of the DC-DC converter circuit and a reference voltage. The voltage-to-current conversion circuit configured to convert the difference voltage to a difference current. The oscillator circuit is configured to generate a clock signal at a predetermined frequency for pulse width modulation. The PFM control circuit is configured to disable the oscillator circuit, based on the difference current, for PFM operation.

Abstract: Technologies relating to implementing two-stage ramp ADCs in crossbar array circuits for high performance matrix multiplication are disclosed. An example two-stage ramp ADC includes: a transimpedance amplifier configured to convert an input signal from current to voltage; a comparator connected to the transimpedance amplifier; a switch bias set connected to the comparator; a switch side capacitor in parallel with the switch bias set; a ramp side capacitor in parallel with the switch bias set; a ramp generator connected to the comparator via the ramp side capacitor, wherein the ramp generator is configured to generate a ramp signal; a counter; and a memory connected to the comparator, wherein the memory is configured to store an output of the comparator.

Abstract: A FMCW radar receiver includes a LO providing a chirped LO signal, an in-phase (I) channel for outputting I-data and a quadrature (Q) channel for outputting Q-data. A dynamic correction parameter generator generates IQ phase correction values (P[n]s) and IQ gain correction values (G[n]s) based on a frequency slope rate of the chirped LO signal for generating during intervals of chirps including a first sequence of P[n]s and G[n]s during a first chirp and a second sequence of P[n]s and G[n]s during a second chirp. An IQ mismatch (IQMM) correction circuit has a first IQMM input coupled to receive the I-data and a second IQMM input receiving the Q-data, and the P[n]s and G[n]s. During the first chirp the IQMM correction circuit provides first Q?-data and first I?-data and during the second chirp the IQMM correction circuit provides at least second Q?-data and second I?-data.

Abstract: A device is provided comprising a first oscillator based analog-to-digital converter configured to receive an analog input signal and output a first digital signal and a second oscillator based analog-to-digital converter configured to receive an analog reference signal and output a second digital signal. The device further comprises output logic configured to generate a digital output signal based on the first digital signal and the second digital signal.

Abstract: A FMCW radar receiver includes a LO providing a chirped LO signal, an in-phase (I) channel for outputting I-data and a quadrature (Q) channel for outputting Q-data. A dynamic correction parameter generator generates IQ phase correction values (P[n]s) and IQ gain correction values (G[n]s) based on a frequency slope rate of the chirped LO signal for generating during intervals of chirps including a first sequence of P[n]s and G[n]s during a first chirp and a second sequence of P[n]s and G[n]s during a second chirp. An IQ mismatch (IQMM) correction circuit has a first IQMM input coupled to receive the I-data and a second IQMM input receiving the Q-data, and the P[n]s and G[n]s. During the first chirp the IQMM correction circuit provides first Q?-data and first I?-data and during the second chirp the IQMM correction circuit provides at least second Q?-data and second I?-data.

Abstract: The present disclosure, which relates to a data communication between a micro-controller and a source readout circuit, does not require a clock circuit of a slave, and thus, allows the size of a slave circuit and power consumption to be reduced.

Abstract: An apparatus and method for managing an electrostatic charge of a workpiece are disclosed. The method includes coupling an electrostatic voltmeter to a conductor, coupling a charge-adjustment system to the conductor, and coupling the conductor to the workpiece. A level of charge in the workpiece is adjusted, via the conductor, with the charge-adjustment circuit and a voltage of the workpiece is monitored, via the conductor, with the electrostatic voltmeter. A controller may be used to adjust the charge on the workpiece based upon the monitored voltage.

Abstract: The present invention discloses an online method for metering performance of a diaphragm gas meter. A magnetic turntable in an electromechanical conversion device is reasonably segment and motion information of each segment is recorded and analyzed. Every time when the diaphragm gas meter discharges gas of a rotary volume, a rotating shaft of a meter core rotates a circle. The magnetic turntable is meshed with a driving gear output by the rotating shaft in the meter or output by the rotating shaft outside the meter to ensure that the magnetic turntable rotates a circle every time when the diaphragm gas meter discharges a rotary volume. The present invention is significant for error management of the gas meter and intelligent control and gas utilization safety management of a gas user.

Abstract: Disclosed is a field device of automation technology, comprising: a housing having a wall; a data transmission means arranged on an outside of the housing wall; and an electronic operating circuit arranged in a housing chamber and is adapted to operate the data transmission means, wherein the data transmission means and the electronic operating circuit are connected via an electrical signal line having a plurality of electrical conductors, wherein a first electrical conductor is adapted to lead a data signal and wherein at least a second electrical conductor is adapted to shield the first electrical conductor, wherein the signal line has an isolation device adapted to isolate a first signal line section galvanically from a second signal line section, wherein the isolation device includes an electromagnetically transparent plate having a first lateral surface and a second lateral surface parallel to the first lateral surface.

Abstract: In a current detection apparatus, an arm current detection unit detects each of at least first and second phase currents having respective amplitudes and flowing in a multiphase rotary electric machine based on a potential difference between input and output terminals of the corresponding one of first and second detection switches during the corresponding one of the first and second detection switches being on. A bus current detection unit detects each of at least bus-based first and second phase currents corresponding to the first and second phases of the multiphase rotary electric machine based on a current flowing through one of first and second buses. An amplitude correction unit corrects the first and second phase currents based on the bus-based first and second phase currents such that the amplitudes of the respective first and second phase currents match with each other.

Abstract: An on/off system operates to affect a variable state or condition of a building by switching between an on state and an off state. An extremum-seeking controller operates the on/off system by providing a pulse width modulated (PWM) control signal having a duty cycle to the on/off system. The extremum-seeking controller is configured to generate the PWM control signal by receiving a performance variable as feedback from the on/off system, extracting a gradient of the performance variable with respect to the duty cycle, modulating the duty cycle using an extremum-seeking control technique to determine an optimal value of the duty cycle that drives the gradient toward zero, and generating the PWM control signal such that each period of the PWM control signal has a pulse width proportional to the duty cycle.

Abstract: A signal transmission device for pulse density modulated signals comprises a signal input for an input signal with a defined maximum signal value, a modulation stage for generating a pulse density modulated transmission signal out of the input signal, a locking device at the input for the pulse density modulated transmission signal to overwrite same with a static fault signal, a pulse reconstructing transmission path for the pulse density modulated transmission signal, a demodulation stage at the output, for reconstructing the input signal out of the transmitted pulse density modulated transmission signal, and a signal change monitoring device capturing the pulse density modulated transmission signal of the transmission path at the output, which has an error signal output for signaling the detection of a missing dynamic pulse density modulated transmission signal on the transmission path due to the static fault signal.

Abstract: A field measuring device includes a sensor, a measuring transducer, and interface electronics. The interface electronics include a measuring and control device, and first and second terminals for connecting an external electrical device. A current controller and a current measuring device are connected in series in a terminal current path between the first and second terminals. The interface electronics has a voltage source that can be switched on in the terminal current path and disconnected from the terminal current path, so that the voltage source can drive a current in the terminal current path in the switched-on state and in the case of a connected external electrical device. The measuring and control device actuates and reads the current controller, the current measuring device, and the voltage source such that a current signal is output or input via the first and second terminals when an external device is connected.

Abstract: An A-D conversion circuit configured to convert an analog input signal into numerical data using a pulse delay circuit includes pulse position digitizing units, a clock generation circuit, and a processing unit. The clock generation circuit includes inverters each including one or more n-channel transistors and one or more p-channel transistors. The inverters differ from each other in a number ratio of the number of n-channel transistors connected in a common-gate parallel-connected manner and the number of p-channel transistors connected in a common-gate parallel-connected manner.

Abstract: Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Today's leading edge modulated sinusoidal wave wireless communication standards and systems achieve power efficiencies of 50 nJ/bit employing narrowband signaling schemes and traditional RF transceiver architectures. However, such designs severely limit the achievable energy efficiency, especially at lower data rates such as below 1 Mbps. Further, it is important that peak power consumption is supportable by common battery or energy harvesting technologies and long term power consumption neither leads to limited battery lifetimes or an inability for alternate energy sources to sustain them. Accordingly, it would be beneficial for next generation applications to exploit inventive transceiver structures and communication schemes in order to achieve the sub nJ per bit energy efficiencies required by next generation applications.

Abstract: According to various embodiments, an inverter-based resistor may be provided. The inverter-based resistor may include at least one digital inverter, wherein each of the at least one digital inverter is configured to receive an input and provide an output, each of the at least one digital inverter further includes a positive voltage rail and a negative voltage rail, wherein the digital inverter input is connected to the inverter output and the positive voltage rail is connected to the negative voltage rail, and wherein a current flowing through the inverter-based resistor varies in direction and magnitude in response to a digital input provided to the positive voltage rail and the negative voltage rail.

Abstract: An analog-to-digital converter has a switched capacitor comprising a capacitor to perform charging and discharging by switching a switch, the switched capacitor varying a charge amount of the capacitor in accordance with a frequency of an oscillation signal in accordance with a differential signal between an input signal and a feedback signal, capacitance of the capacitor, and a predetermined bias voltage, a feedback signal generator to generate the feedback signal based on an output signal of the switched capacitor, and a digital converter to generate a digital signal by digital conversion of the input signal based on the oscillation signal.

Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).

Abstract: A comparator includes a first voltage-time conversion circuit, a second voltage-time conversion circuit, and a determination circuit. A first delay unit includes a first primary conductivity type transistor of which current is controlled based on a first input signal, a first secondary conductivity type transistor of which current is controlled based on a second input signal, and a first delay buffer provided between the transistors. A second delay unit includes a second primary conductivity type transistor of which current is controlled based on a second input signal, a second secondary conductivity type transistor of which current is controlled based on a first input signal, and a second delay buffer provided between the transistors.

Abstract: A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single pulse signal in synchronization with the respective delayed clock signals, and output sampling signals; and a count sub-circuit configured to output a count value resulting from counting a number of active sampling signals of the sampling signals.

Abstract: Each of a plurality of analog-to-digital (AD) converters configuring a column AD converter used in an image sensor comprises: an oversampling AD converter that receives an output voltage of a pixel unit; a recursive AD converter that receives an analog residual signal of the oversampling AD converter; and a counter that adds a digital signal output from the oversampling AD converter and a digital signal output from the recursive AD converter. The controller dynamically allocates the number of bits of the oversampling AD converter and the number of bits of the recursive AD converter, while maintaining the total number of bits of the oversampling AD converter and the recursive AD converter.

Abstract: Noise in a semiconductor device including a photo sensor is reduced. The semiconductor device includes an analog/digital converter and a photo sensor including a photodiode. The analog/digital converter includes an oscillation circuit and a counter circuit. A first signal output from the photo sensor is input to the oscillation circuit. The oscillation circuit has a function of outputting a second signal obtained by a change in oscillation frequency of the first signal. The counter circuit has a count function by which addition or subtraction is performed by a control signal with the second signal used as a clock signal. The counter circuit performs subtraction during the reset operation of the photo sensor. The counter circuit performs addition during the selection operation of the photo sensor. Thus, the output value of the analog/digital converter can be corrected.

Abstract: Provided is a current output circuit 1 including a pseudo sine wave separation circuit 11 that separates a pseudo sine wave represented by a digital code Din into two pseudo half-waves represented by digital signals D1 and D2, a DA converter 113 that converts the pseudo half-wave represented by the digital signal D1 into an analog half-wave signal V1, a DA converter 114 that converts the pseudo half-wave represented by the digital signal D2 into an analog half-wave signal V2, and a voltage-current conversion circuit 12 that converts voltages of the half-wave signals V1 and V2 into currents and outputs a current Iout obtained by combining the currents.

Abstract: In one embodiment, an apparatus includes: a first voltage controlled oscillator (VCO) analog-to-digital converter (ADC) unit to receive a first portion of a differential analog signal and convert the first portion of the differential analog signal into a first digital value; a second VCO ADC unit to receive a second portion of the differential analog signal and convert the second portion of the differential analog signal into a second digital value; a combiner to form a combined digital signal from the first and second digital values; a decimation circuit to receive the combined digital signal and filter the combined digital signal into a filtered combined digital signal; and a cancellation circuit to receive the filtered combined digital signal and generate a distortion cancelled digital signal, based at least in part on a coefficient value.

Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.

Abstract: In one embodiment, an apparatus includes: a first voltage controlled oscillator (VCO) analog-to-digital converter (ADC) unit to receive a first portion of a differential analog signal and convert the first portion of the differential analog signal into a first digital value; a second VCO ADC unit to receive a second portion of the differential analog signal and convert the second portion of the differential analog signal into a second digital value; a combiner to form a combined digital signal from the first and second digital values; a decimation circuit to receive the combined digital signal and filter the combined digital signal into a filtered combined digital signal; and a cancellation circuit to receive the filtered combined digital signal and generate a distortion cancelled digital signal, based at least in part on a coefficient value.

Abstract: In the field of imaging devices comprising a detector generating electric charges in response to incident photon radiation, and an analog-to-digital conversion circuit forming means for reading the quantity of electric charges generated, an analog-to-digital conversion circuit comprises: a comparator which can switch depending on the comparison between a potential on an integration node and a predetermined threshold potential, a counter incrementing with each switch of the comparator, a counter-charge injection circuit injecting a quantity Qc of counter-charges on the integration node with each switch of the comparator, and control means which determine the quantity Qc of counter-charges injected. The analog-to-digital conversion circuit is characterized in that the control means determine the quantity Qc of counter-charges injected as a function of a value of the counter.

Abstract: An output changing method of an A/D conversion apparatus is provided. The apparatus includes a pulse delay circuit in which delay units are connected in series, and an encoding circuit which detects the number of stages of the delay units, through which a pulse signal passes during predetermined measurement time, and generates numeric data corresponding to the number of stages. The apparatus receives an analog input signal as power supply voltage of the pulse delay circuit to perform A/D conversion for the analog input signal. The method includes determining whether or not the analog input signal is within an allowable voltage range in which the apparatus operates normally, outputting the numeric data as an A/D conversion value if the analog input signal is within the range, and outputting numeric data formed of a specified value as the A/D conversion value if the analog input signal is not within the range.

Abstract: An A/D conversion device has an A/D conversion section including A/D conversion units. Each A/D conversion unit has a pulse delay circuit including delay units connected in daisy chain to form a ring delay line. Each delay unit delays a pulse signal by a delay time corresponding to an input voltage. The A/D conversion section counts the number of pulse signals that passed through the delay units during a period counted from a timing when a start signal is switched to an activation level from a non-activation level at a timing when a sampling signal is received. When each two successive timing signals CKi (i=1, 2, . . . and m) have a same specific period. The each two successive timing signals have a different phase shifted by 1/m of the specific period. Each A/D conversion unit receives the timing signal CK1 as the start signal, and the timing signal CKi+1 (CKm+1=CK1) as the sampling signal.

Abstract: A device having a first oscillator circuit configured to generate a first signal with a first frequency based on an analog input and external characteristics, and a second oscillator circuit configured to generate a second signal with a second frequency based on a constant voltage and the external characteristics. The device also having one or more discrete logic gates configured to generate a digital composite signal based on the first signal and the second signal, such that a number of transitions in the digital composite signal over a period of time, based on the first frequency of the first signal, are indicative of the analog input.

Abstract: An integrated circuit in a PET imaging system with a plurality of photo detectors is provided. A plurality of differential transimpedance amplifiers with differential inputs and differential outputs is provided, wherein differential inputs for each differential transimpedance amplifier of the plurality of differential transimpedance amplifiers are electrically connected to a photodetector.

Abstract: The invention relates to a synchronous power controller for a generation system based on static power converters, said controller comprising two main blocks referred to as: block 1 (electric block) (10) and block 2 (electromechanical block) (20), electric block 1 (10) being, in turn, formed by a virtual electrical characteristic controller (11) and a virtual admittance controller (12) and the electromechanical block 2 (20) being formed by a virtual electromechanical characteristic controller (21) and an inertia and damping factor controller (22).

Abstract: A method is provided for calibrating the mean frequency of a voltage controlled oscillator (VCO) based analog-to-digital converter (ADC). The method accepts a differential analog input signal comprising a positive signal and a negative signal. The positive signal is converted into a first frequency and the negative signal is converted into a second frequency. The first frequency is converted into a first digital value and the second frequency is converted into a second digital value. The first digital value is added to the second digital value to find a common mode value, and the common mode value is compared to a predetermined common mode value to find a first error. The first error is converted to a first bias modification of the differential analog input signal, and in response to the differential analog input first bias modification, the first error is minimized.

Abstract: In one embodiment, an AD converter includes a first (second) oscillation circuit, a first (second) counter, a first (second) arithmetic circuit, a first (second) subtracting circuit, an adder circuit, and a feedback circuit. The first oscillation circuit generates a first pulse signal having a frequency corresponding to a level of a first analog signal. The first counter counts the first pulse signal. The first arithmetic circuit generates a first signal corresponding to a change amount of a count value. The first subtracting circuit outputs a digital signal corresponding to a difference between the signals generated by the first and second arithmetic circuits. The adder circuit generates a sum signal of the signals generated by the first and second arithmetic circuits. The second subtracting circuit generates a difference signal between the sum signal and a reference signal. The feedback circuit inputs the difference signal to the first oscillation circuit.

Abstract: A ring oscillator circuit causing a pulse signal to circulate around a circle to which an even number of inverting circuits are connected in a ring, wherein one of the inverting circuits is a first starting inverting circuit, which drives a first pulse signal according to a control signal, another of the inverting circuits is a second starting inverting circuit, which drives a second pulse signal based on a leading edge of the first pulse signal, still another is a third starting inverting circuit, which drives a third pulse signal based on the leading edge of the first pulse signal after the second pulse signal is driven, and the first to third starting inverting circuits are arranged within the circle of the inverting circuits in order of the third, second, and first pulse signals in traveling directions of the pulse signals.

Abstract: An analog to digital converter (ADC) includes a clock-halting circuit that is enabled by an externally generated trigger signal. The clock-halting circuit halts an input clock signal to the ADC for a predetermined time period and resumes the input clock signal to the ADC when the predetermined time period ends.

Abstract: A method is provided for generating a digital signal (DS) from an analog signal (IA, UA) generated by a frequency converter on the basis of pulse width modulation, wherein the digital signal corresponds to a mean value of the analog signal over a period of the pulse width modulation. The method includes the acts of: generating a bit stream (BS(i)) with a predetermined bit repetition duration (BW) depending on the analog signal by way of a sigma-delta modulator (1) and, during a time interval which has a duration which is at least as great as the period of the pulse width modulation: multiplying a respective bit (BS(i)) of the bit stream by a corresponding rating coefficient (BK(i)) for generating a respective bit/rating coefficient product and summing the respective bit/rating coefficient products, wherein the sum represents the digital signal.

Abstract: A method for testing the material of a test object (8) in a nondestructive manner, said test object being moved relative to a probe (1) at a variable relative speed, comprises the following steps: detecting a probe signal (US) by means of the probe (1), subjecting the probe signal (US) to analog-to-digital conversion in order to generate a digitized probe signal (USD) in the form of a sequence of digital words with a predefined, in particular constant, word repetition rate, n-stage decimation of the word repetition rate of the digitized probe signal (USD) or of a digital demodulation signal (UM) derived from the digitized probe signal by means of n cascaded decimation stages (5_1 to 5_n), where n?2, selecting an output signal (UA_1 to UA_n) of one of the n decimation stages (5_1 to 5_n) depending on the instantaneous relative speed and filtering the selected output signal by means of a digital filter (7), which is clocked with the word repetition rate of the selected output signal.

Abstract: A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.

Abstract: A high dynamic range sensitive sensor element or array is provided which uses periodic sampling phase domain integration techniques to accurately capture high and low intensity images. The sensor element of the present invention is not limited by dynamic range characteristics exhibited by prior art solid-state pixel structures and is thus capable of capturing a full spectrum of electromagnetic radiation to provide a high quality output image.

Abstract: In a pulse phase difference coding circuit, a count unit includes a plurality of partial counters connected to each other in series so that the most significant bit of an output of the previous stage serves as an operation clock of the subsequent stage. A circulation number detecting unit includes a first latch circuit which is provided for each of the partial counters and latches an output of the partial counter according to a pulse for measurement, and a first delay circuit which treats the partial counter in the second stage or later as an object counter and delays the pulse for measurement by a total delay time in all the partial counters located at the previous stages of the object counter. The pulse for measurement is inputted into the first latch circuit which latches an output of the object counter.

Abstract: Disclosed are a ramp signal generator and an image sensor. The ramp signal generator includes: a comparator comparing a first bias voltage input to a first input terminal and a second bias voltage input to a second input terminal and outputting a ramp signal from an output terminal; a ramp signal adjustment unit including a plurality of switched capacitors made up of switches and capacitors connected in series, and connected in parallel between a first input terminal of the comparator and an output terminal of the comparator; and a controller switching the switches of the plurality of switched capacitors to adjust the ramp signal output from the comparator such that the ramp signal becomes nonlinear over time.

Abstract: A circuit arrangement for detecting and digitizing an analog input signal and to a field device for process instrumentation, wherein the field device comprises such a circuit arrangement which includes a first electronics unit, a second electronics unit, and an interface by which the two electronics units are galvanically separated from each other. A first signal is generated at a first frequency in the second electronics unit. A voltage frequency converter, to which the analog input signal is routed, uses a reference frequency to generate a second signal at a second frequency that corresponds to the level of the analog input signal. After the second signal has been transmitted to the second electronics unit using an optical coupler, a ratiometric measurement of the second frequency is performed in the second electronics unit dependent on the first frequency using a capture timer.

Abstract: A method is provided for operating an electromechanical actuator comprising a movable element, a position sensor for detecting the position of the movable element, a logic unit connected to the position sensor, and exactly one output line for the logic unit to transmit a pulse width modulated (PWM) signal having a predetermined frequency value, the method providing for the logic unit to perform detecting a position of the movable element, determining a value of a duty cycle of the pulse width modulated (PWM) signal on the basis of the detected position of the movable element, and transmitting a pulse width modulated (PWM) signal indicative of the position of the movable element having the determined value of the duty cycle.