Abstract: Embodiments disclosed herein relate generally to digital transponders.

Abstract: A method to receive channels in an undersampled broadband receiver is provided. The method includes converting received radio frequency signals to downshifted-sampled-digital signals at an analog-to-digital converter in a sampling system, outputting the downshifted-sampled-digital signals to a digital system for digital processing, and determining if the unique identifying code associated with a desired channel is detectable. Each channel in the radio frequency signal has an assigned unique identifying code. When the unique identifying code is detectable, the method includes detecting the unique identifying code associated with the desired channel. When the unique identifying code is undetectable, the method includes outputting control signals from the digital system to tune an adjustable sample clock in the sampling system and tuning the adjustable sample clock based on the output control signals.

Abstract: A time-to-digital converter includes low and high resolution time-to-digital converters for providing both high resolution and wide measurement range. The low resolution time-to-digital converter measures a time difference between first and second signals with a first quantization step. The high resolution time-to-digital converter measures the time difference between the first and second signals with a second quantization step that is smaller than the first quantization step. The low resolution time-to-digital converter has a wider measurement range than the high resolution time-to-digital converter.

Abstract: In-system signal monitoring using an integrated circuit such as a programmable logic device is described. An analog-to-digital converter is disposed in the programmable logic device. A sampling bridge is coupled to provide an analog input to the analog-to-digital converter and to receive first signaling of a first frequency. A signal generator is configured to provide second signaling at a second frequency which is a fraction of the first frequency. Sample window circuitry is coupled to receive the second signaling and configured to provide third signaling to the sampling bridge at least partially responsive to the second signaling and at least partially responsive to an adjustable impedance setting of the sample window circuitry. The sample window circuitry is configured to provide an adjustable sample window within a pulse-width range.

Abstract: A flash A/D converter includes a reference voltage generator for generating a plurality of reference voltages, a first group of amplifiers having a plurality of amplifiers each of which amplifies a difference voltage between each reference voltage generated by the reference voltage generator and a voltage of an input signal, and a second group of amplifiers having a plurality of amplifiers. Each amplifier of the first group of amplifiers is a differential amplifier having a different pair formed of a plurality of sets of cascade-connected transistors, and has a first switch for short-circuiting respective cascade connection portions of the plurality of transistors configuring the differential pair. Each amplifier of the second group of amplifiers is a differential amplifier having a differential pair formed of at least two transistors and has a second switch for short-circuiting a portion between input units of the differential pair.

Abstract: A sigma-delta converter comprises a sigma-delta modulator (SDM) with a signal processing block (SP) and a quantizer (QNT), as well as a stage adaptation element (DCC). The signal processing block (SP) is designed for deriving a modulated signal (MOD) in dependence on the respective signals at a signal input (SIN) and at a feedback input (FIN). The quantizer (QNT) comprises a quantization input (QIN) that is coupled to the signal output (SOT) and a quantization output (QOT) that is coupled to the feedback input (FIN), wherein the quantizer is designed for deriving a first quantized signal (Q1) from the modulated signal (MOD) by quantization with a first number of stages and for outputting this first quantized signal at the quantization output (QOT).

Abstract: An A/D converter circuit uses first and second ring delay lines. The first and second ring delay lines are supplied with input signals, which increase/decrease oppositely from each other with respect to change directions. In each ring delay line, a first counter counts the number of times of circulation of a pulse signal circulating therein to find a digital data, and a last digital data is subtracted from a present digital data. By adding the resulting first and second digital data of the first and second ring delay lines, a digital data of the input voltage of linear characteristics is provided.

Abstract: There are provided an analog-digital converter circuit capable of performing the same degree of operation as being performed at a high-frequency oscillation pulse using a low-frequency oscillation pulse without using the high-frequency oscillation pulse, a timing signal generating circuit generating a timing signal at the high frequency, and a control device using the circuits. In an analog-digital converter circuit, a periodic signal generating circuit allows the first to j-th pulse counting devices of the N pulse counting devices to count a count value X and allows the other pulse counting devices to count a count value X?1 in each sampling period by sequentially generating N serial periodic signals at a delay time interval of [approximate value of one period (T) of periodic signals]÷N. A digital signal generating circuit converts the analog signal to the digital signal.

Abstract: A high dynamic range sensitive sensor array is described which uses a combination of pixel structures, some of which incorporating phase domain integration techniques to accurately capture high and low intensity images. The sensor elements included as many of the pixel structures in the sensor array are not limited by dynamic range characteristics exhibited by prior art solid-state pixel structures and is thus capable of capturing a full spectrum of electromagnetic radiation to provide a high quality output image.

Abstract: A signal reader system having a processor for reconstructing a relatively high-frequency input signal to a low-pass filter from an output of the filter based on a characterization of the filter. The characterization may be adapted to compensate for filter output changes due to temperature. A signal reader may be connected to the output of the processor to determine certain things, such as a pulse count, about the filter input signal.

Abstract: This disclosure relates to adjusting a limit cycle frequency of a pulse width modulation in an analog to digital converter as a function of an input signal level to increase dynamic range.

Abstract: An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values.

Abstract: An inverter circuit configuring a delay unit is a so-called CMOS transistor including a PMOS transistor and an NMOS transistor, of which respective gates are interconnected and respective drains are interconnected. The source and a back gate of the NMOS transistor are connected to the ground. The source of the PMOS transistor is connected to a positive drive terminal and controlled by an analog input signal. The back gate of the PMOS transistor is connected to a control terminal and controlled by a control signal.

Abstract: Integrators are electronic components used to condition received analog signals, for example prior to Analog to Digital Conversion. Wide dynamic range, high gain and fine resolution are required of integrators and Analog to Digital Converters in order to limit the effects of noise, including quantization noise. Conventional integrators preceding Analog to Digital Converters are not capable of effectively meeting these requirements. A novel phase domain integrator that can meet effectively these requirements and is superior to conventional integrators for a wide range of applications is disclosed.

Abstract: The signal-to-noise ratio for a digital conversion circuit is improved by taking a source signal and generating N signals that are each phase-shifted relative to each other, thereby generating N phase-shifted signals. Each of the N signals has a frequency that is a fraction of a frequency of the source signal. The source signal is input to a dividing circuit to generate the N signals. The source signal is generated by a signal source, such as an oscillator. Each of the N signals is hard-limited and processed through a detection circuit. The detection circuit can be a frequency detection circuit configured to determine the frequency of the source signal and to output a corresponding digital word, or a phase detection circuit configured to determine a phase of the source signal and to output a corresponding digital word.

Abstract: In embodiments, a new analog-to-digital converter (ADC) architecture can be used with switch-mode power supplies (SMPS) operating at switching frequencies higher than 10 MHz. Analog-to-digital converter embodiments can achieve very low power consumption, fast conversion time, and can be implemented with a simple hardware. Another noteworthy benefit is that certain ADC embodiments feature a non-linear gain characteristic that provides improved load transient response for digital controllers.

Abstract: A cycle time to digital converter includes a dual delay lock loop, multi phase sampling detector and VDL sampling detector. The dual delay lock loop generates the first voltage corresponding to the first delay time and the second voltage corresponding to the second delay time. The multi phase sampling detector receives first start signal, first stop signal and first voltage to detect a coarse delay time, generates the first group signals according to the coarse delay time, delays the first stop signal by a common delay time to generate the second stop signal, and delays the first start signal by the coarse delay time and the common delay time to generate the second start signal. The VDL sampling detector receives first voltage, second voltage, second start signal and second stop signal for detecting a fine delay time and generates the second group signals according to the fine delay time.

Abstract: A digital to analog converter includes a time encoder that converts an analog input signal into a asynchronous pulse sequence, a pulse asynchronous DeMUX circuit that converts the asynchronous pulse sequence into a parallel stream of pulse sequences at a relatively lower speed, a parallel pulse to asynchronous digital converter, an asynchronous digital to synchronous digital converter, a timing reference circuit to generate absolute time references, and a Digital Signal Processor. This architecture provides for analog to digital conversion based on pulse encoding with a parallel digitization scheme of the pulse encoded signal.

Abstract: An ADC, such as a CT SD-ADC, includes a clock generation circuit that produces charging and discharging clock signals such that a settling time for an integrator in the ADC is increased. The clock signals may control a feedback SD-DAC in the CT SD-ADC. The clock signals also may be asymmetric and/or may result in the settling time of the integrator being greater than half the system clock.

Abstract: Certain exemplary embodiments can provide a method, which can comprise transmitting a recovered analog input signal to a programmable logic controller. The recovered analog input signal can be converted, on a downstream side of an isolation device, from a converted signal. The recovered analog input signal can have a voltage value that varies according to a frequency value of the converted signal.

Abstract: A method to receive channels in an undersampled broadband receiver comprising mixing bands of assigned channels with an oscillator to generate downconverted bands, wherein each assigned channel has an assigned unique identifying code. The method further includes undersampling the downconverted bands and determining if the unique identifying code associated with a desired channel is detectable. When the unique identifying code is detectable, the method further comprises detecting the unique identifying code associated with the desired channel. When the unique identifying code is undetectable, the method further comprises tuning the oscillator and detecting the unique identifying code associated with the desired channel based on the tuning.

Abstract: Disclosed is a differential amplifying circuit including an amplifying circuit, wherein 1) a drain of a sixth transistor is connected to a drain of an eighth transistor, and a drain of a tenth transistor is connected to a drain of a fourth transistor, and 2) a ratio between a total of gate widths of the fourth (or eighth) and tenth (or sixth) transistors (converted per unit gate length, and gate widths that follow are the same) and a gate width of a fifth (or ninth) transistor is nearly proportional to a current ratio between a first (or third) and second (or fourth) current source circuits, the gate width of the fourth (or eighth) transistor being equal to or more than that of the tenth (or sixth) transistor.

Abstract: An A/D converter circuit uses first and second ring delay lines. The first and second ring delay lines are supplied with input signals, which increase/decrease oppositely from each other with respect to change directions. In each ring delay line, a first counter counts the number of times of circulation of a pulse signal circulating therein to find a digital data, and a last digital data is subtracted from a present digital data. By adding the resulting first and second digital data of the first and second ring delay lines, a digital data of the input voltage of linear characteristics is provided.

Abstract: An analog to digital converter that first converts an analog input voltage into first and second periodic signals having a phase difference there between that is a function of the analog input voltage and then introduces the first periodic signal into a forward direction data path through a series of consecutive delay cells so that the first periodic signal propagates through the cells via the first series of delay elements in a first direction, and introduces the second periodic signal into a reverse direction data path through the same series of delay cells so that the second periodic signal propagates through the cells via the second series of delay elements in an opposite direction, and using the second periodic signal to latch the first periodic signal in each cell so as to generate an output signal for each cell, said output signals of said cells collectively indicating the unique cell in which the leading edges of corresponding pulses in the first and second directions met, and decoding the outputs of

Abstract: The digitization apparatus includes, as a main scale, a pulse delay circuit constituted by a plurality of delay units connected in series or in ring form, a latch/encoder, a circulation number counter, and a latch circuit, and includes, as a vernier, a reverse timing extraction circuit detecting a reverse timing at which any one of the delay units has reversed, and an interpolation circuit. The main scale digitizes a time interval between two successive measurement signals in a resolution equal to a delay time per one delay unit. The vernier digitizes a time difference between a measurement timing indicated by the measurement signal and the reverse timing in a resolution equal to 1/M (M being an integer not smaller than 2). The interpolation circuit includes two delay lines each constituted by a plurality of delay units connected in series or in ring form.

Abstract: An analog-to-digital conversion arrangement converting an input analog signal into an output digital representation. Two or more analog-to-digital conversion paths each applying a conversion mapping between input analog signal magnitudes and respective digital values generate an intermediate representation of the input analog signal, the conversion paths being operable to apply different respective conversion mappings. An output circuit combines the intermediate representations from at least two conversion paths to generate the output digital representation, the intermediate representations being combined according to a weighting dependent on the magnitude of the input analog signal. At least one of the conversion paths has an enhanced sensitivity mode appropriate to a range of magnitudes of the input signal that are below a threshold magnitude. Control logic inhibits operation in the enhanced sensitivity mode if the magnitude of the input analog signal exceeds the threshold magnitude.

Abstract: A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity corrector for a TDC. In one embodiment, the TDC includes a chain of delay elements configured to receive a clock signal and generate delayed clock signals. Each one of the delay elements includes: (1) a non-inverting buffer configured to delay the clock signal by about twice a delay of an inverter to provide a buffer-delayed clock signal and (2) a first transmission gate coupled to the non-inverting buffer and configured to delay the clock signal by about the delay of an inverter to provide a first gate-delayed clock signal.

Abstract: An analog-to-digital converter converts a frequency-modulated signal into a digital signal. The frequency-modulated signal is supplied to multiple comparators, such as low-pass filters, which determine whether the signal falls within their frequency ranges. The outputs of the comparators are converted into a digital output signal, e.g., by fat-tree encoding. Each comparator has a differently tuned capacitive load to cause a phase delay in the input signal. When the phase-delayed and non-phase-delayed signals are supplied to a D-Flop, the phase delay is determined by whether the latch conditions are met.

Abstract: In a semiconductor-integrated A/D converter, a pulse delay circuit is provided with a plurality of delay units. The plurality of delay units each includes at least one logic gate and operates based on a level of an input signal. The pulse delay circuit is configured to transfer a pulse signal through the plurality of delay units while the pulse signal is delayed by the plurality of delay units. A delay time of each of the plurality of delay units depends on the level of the input signal. The at least one logic gate is composed of at least one first transistor. The at least one first transistor has a first threshold voltage. A generating circuit is configured to obtain a number of the delay units through which the pulse signal has passed within a predetermined period to generate digital data based on the obtained number. The generating circuit is composed of at least one second transistor. The at least one second transistor has a second threshold voltage.

Abstract: The sensor network described herein uses a distributed sigma-delta converter, where each of a plurality of sensor nodes includes a sigma-delta modulator communicatively coupled to a remotely located sigma-delta processor in a control hub. Each sensor node generates a serial bit stream representative of a sensor output signal. The control hub includes a plurality of signal processors, each of which receive and digitally process the serial bit stream wirelessly transmitted by a corresponding sensor node. A controller in the control hub analyzes the digital output from each signal processor to determine one or more characteristics of the sensor network.

Abstract: An A/D conversion processing circuit includes: a switch sequentially switching over multiple inputs to select each thereof according to input bandwidth of the multiple inputs or fixedly selecting a single input; an A/D converter obtaining a digital signal through sampling on a switch output with a sampling frequency according to a necessary signal bandwidth; an interpolation section performing on each signal from a separation section which separates signals included in an A/D converter output, an interpolation processing according to a sampling timing deviation in the A/D converter, to obtain a signal where the multiple inputs are digitally converted at the same sampling timing; and an output section outputting as-is an output of the A/D converter if a signal of the single input is inputted to the A/D converter from the switch, thereby allowing commonly using a single A/D converter for multiple inputs, restraining increased circuit scale and power consumption.

Abstract: A method is for processing an incident signal, in which the incident signal is delivered to a transconductor stage, and a current output of the transconductor stage is coupled to an output capacitor so as to deliver to the output capacitor a current signal lasting for at least part of the first half-period of each period of a periodic signal and to thus obtain a frequency-transposed signal at the output capacitor. Upon the occurrence of each part of the first half-period, the voltage of the current output, seen from the output capacitor, is reset to a value equal to that of the voltage of the output capacitor.

Abstract: An A/D converter which converts an analog current signal into a digital signal, includes: a filter removing a noise component from the analog current signal to output an analog voltage signal; a quantizer quantizing the analog voltage signal outputted from the filter to generate the digital signal; and a D/A converter converting the digital signal generated by the quantizer into an analog feedback current to feedback to an input of the filter, and supplying a bias current for the D/A converter to an output of a frequency converter via a path of the analog current signal as a bias current driving the frequency converter outputting the analog current signal.

Abstract: An up-converter 124 frequency-up-converts an analog signal Sm. A down-converter 121 frequency-down-converts analog signal Sm. A signal selection block 125 selects one of the frequency-up-converted signal Sfu and frequency-down-converted signal Sfd. The signal Se selected by the signal selection block 125 is provided to the primary winding of a transformer 127. A signal induced in the secondary winding of the transformer 127 is provided to an A/D converter 128 to produce a digital signal Dm. For example, if the analog signal Sm has DC or a low frequency close to DC, the signal Sfu is selected as the signal Se. If the analog signal Sm does no have DC nor a low frequency close to DC, the signal Sfd is selected as the signal Se.

Abstract: A sigma delta (??) analog to digital converter (ADC) that compensates for the adverse effects associated with the time delay introduced by delay circuitry of the feedback loop. This ?? ADC includes a first summing stage, first integrator, second summing stage, second integrator, quantizer, and feedback loop. The second integrator has associated with it a feed forward pass operable to reduce negative effects of delay circuitry within the feed back loop. Feedback loop includes delay circuitry and a number of digital to analog converters. The feed forward path that reduces the effects of the delay includes a resistance within the second or additional integrator. This allows the adverse effects of the time delays associated, which may lead to circuit instability or meta-stability, to be reduced or eliminated.

Abstract: An adaptive data acquisition circuit (26) includes an amplifier (14) for amplifying electrical pulses generated by a detector (12) responsive to energy incident at the detector. The adaptive data acquisition circuit also includes a counting circuit (28) for counting amplified electrical pulses generated by the amplifier. In addition, the adaptive data acquisition circuit includes a digital logic circuit (30) for determining a pulse parameter indicative of a pulse rate and an amount of energy present in the amplified electrical pulses and for generating a control signal (34) responsive to the pulse parameter for controlling an operating parameter of the data acquisition circuit.

Abstract: The invention relates to at least one self-oscillating loop (SOL) comprising at least one forward path (FP), at least one feedback path (FBP) wherein said at least one forward path (FP) comprises amplitude quantizing means (AQM) combined with time quantizing means (TQM) and outputting at least one time and amplitude quantized signal (OS). According to the invention, a high-speed high-resolution A/D converter may be obtained.

Abstract: The invention relates to at least one self-oscillating loop (SOL) comprising at least one forward path (FP), at least one feedback path (FBP) wherein said at least one forward path (FP) comprises amplitude quantizing means (AQM) combined with time quantizing means (TQM) and outputting at least one time and amplitude quantized signal (OS). According to the invention, a high-speed high-resolution A/D converter may be obtained.

Abstract: Systems and methods are disclosed herein to provide analog-to-digital converter techniques. For example, in accordance with an embodiment of the present invention, an analog-to-digital converter architecture is disclosed that utilizes optical techniques to convert an analog electrical signal to a digital electrical signal.

Abstract: In a TAD (Time Analog-to-Digital) type of A/D converter in which delay units of a pulse delay circuit successively transfer a pulse signal during each of successive measurement intervals, with each delay unit applying an amount of delay determined by an analog input signal voltage, it is ensured that each new measurement interval begins as soon as the pulse delay circuit has become restored to an initialized condition after the preceding measurement interval. Output values expressing the number of delay units traversed by the pulse signal during a measurement interval are used directly as digital values representing the analog input signal voltage level.

Abstract: An A/D converter has inverting elements and delay elements alternately disposed in series. Each inverting element receives an analog voltage signal as a power source and converts a pulse signal in an inversion operation time depending on the analog voltage signal. Each delay element delays transmission of the pulse signal. The transmission of the pulse signal is started from a starting inverting element at a start time, and a transit position of the pulse signal is detected at a detection time later than the start time by a predetermined time. A digital value indicating a level of the analog voltage signal is determined from the detected transit position of the pulse signal. Because transmission of the pulse signal is delayed by the delay elements, the transit position depending on the analog voltage signal can be correctly detected.

Abstract: In an analog-to-digital converter, a generating unit executes analog-to-digital conversion of a first input signal and a second input signal based on an analog-to-digital conversion characteristic curve to generate first digital data and second digital data respectively corresponding to the first input signal and the second input signal. The input signal has a first level, and the first level is the sum of an offset level and a level of a target analog signal for analog-to-digital conversion. The second input signal has a second level, and the second level is generated by subtracting the offset level from the level of the target analog signal. In the analog-to-digital converter, an obtaining unit obtains difference digital data between the first digital data and the second digital data to output the obtained difference digital data as digital data of the target analog signal.

Abstract: An amplifier-based system having pulsed output includes an amplifier for amplifying a time varying voltage signal to produce an output voltage signal. A voltage-to-current (V-I) converter converts the output voltage signal into a current signal. An output stage including a current integrator integrates the current signal to generate an integrated voltage. An amplitude to time converter generates a pulse train from the integrated voltage, wherein a timing of the pulses in the pulse train represents the original time varying voltage signal. The pulse train representation permits transmission and accurate remote reconstruction of the original time varying voltage signal, such as signals generated by electrodes implanted inside a subject, including neural signals.

Abstract: Systems and methods are disclosed herein to provide various optical techniques. For example, in accordance with an embodiment of the present invention, a pulse position modulation discriminator architecture is disclosed for discriminating temporal positions of PPM-encoded optical pulses by converting them from time modulated to frequency modulated signals. As another example, time division multiplexed optical signals may be translated to wavelength division multiplexed optical signals. One or more of the architectures disclosed herein may be implemented, for example, to provide PPM to FM or time to wavelength conversion for receiver or transmitter applications.

Abstract: Differential delay-line analog-to-digital (A/D) converters for use in current and power sensing applications are provided. These A/D converters are well suited for a wide range of electronic applications, including over-load protection, current mode control, current sharing in digitally controlled switched-mode power supplies, power sensing, and implementation of power optimization methods in power management applications.

Abstract: A sigma delta signal treating apparatus includes: (a) a low pass filtered signal path including at least one low pass filter; and (b) a quantization noise filtered signal path coupled with the low pass filtered signal path; the quantization noise filtered signal path including at least one high pass filter and at least one feedback notch filter.

Abstract: The disclosure relates to a microelectronic image sensor device comprising: at least one detector formed by at least one photo-detector element, at least one integration capacitor associated to the photo-detector and capable of providing at least one analogue signal capable of varying at least according to a current provided by the detector, and analogue/digital conversion means for equalising charges comprising: a comparator, injector means capable of modifying the analogue signal by one or more injections, respectively of a given quantity of charge, into the capacitor, command means for charge injector means capable of modulating the given quantity of charge injected according to the intensity of said current.

Abstract: For testing an A/D converter circuit including a pulse delay circuit constituted by a plurality of cascade-connected delay units, and an encoding circuit configured to count the number of the delay units through which the input pulse signal passes within a predetermined measuring time and to output a digital signal representing the counted number, the method includes the steps of setting the A/D converter circuit in a test mode where the measuring time is set at a short test-use sampling period, applying the input pulse signal to each of serial delay blocks each of which is constituted by a predetermined number of the delay units, and determining good and bad of the A/D converter circuit on the basis of digital signals outputted from the encoding circuit representing the numbers of the delay units through which the input pulse signal has passed within each of the serial delay blocks.

Abstract: A delay line, an analog-to-digital converting device and a load-sensing circuit using the same are provided. The delay line comprises a delay-control terminal, a reset terminal, and n delay cells DCELLx (0<x?n). The delay cells DCELL1˜DCELLn are connected in series to each other. Each of the delay cells DCELLx is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The outputs of all delay cells are reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least an output terminal ty (0<y?n) of a delay cell DCELLy among the delay cells DCELL1˜DCELLn used as output terminal of the delay line.

Abstract: The digital sampler circuit processes an output signal from a high gain analog amplifier having as input an infrared motion detector output signal and a negative low pass filtered feedback signal. The amplifier output signal is a substantially square pulse signal having an irregular frequency and duty cycle and has an average duty cycle indicative of a DC level and a slow change in the DC level of the detector output signal. The sampler circuit includes a detector circuit for detecting the amplifier output signal and discriminating at regular intervals a high/low state of the output signal, and generates a high/low feedback signal corresponding to the high/low state of the output signal detected. The high/low state of the output signal is analyzed over a predetermined number of the intervals to obtain a ratio value for producing an output digital signal sample value. The digital sample value is a measure of the DC level and the change in the DC level of the detector output signal.