Abstract: A superconducting A/D converter (10) has an error correction system (70) for eliminating non-linearities in a primary quantizer (30). The converter (10) includes a primary quantizer (30), a primary SFQ counter (50), and the error correction system (70). The primary quantizer (30) generates primary SFQ pulses based on an average voltage of an analog input signal. The primary SFQ counter (50) converts the primary SFQ pulses into a digital output signal based on a frequency of the primary SFQ pulses. The error correction system (70) corrects the digital output signal based on the analog input signal and the primary SFQ pulses. Using the primary SFQ pulses to correct the digital output signal allows the converter (10) to take into account the non-linearities of the primary quantizer (30).

Abstract: An analog input voltage signal to be A/D-converted is supplied to a ring gate delay circuit including inverting circuits connected in series in a ring as a supply voltage thereto. The interval for which a pulse circulates the ring varies with the analog input voltage signal. The number of times circulation of the pulse and the position of the pulse for a predetermined interval are detected by a counter to provide upper bits and by a pulse position detector to provide lower bits of A/D conversion result of the analog input voltage signal, respectively. The counter and the pulse position detector are included in a coding process block which is driven by a constant voltage which is different from the analog input voltage signal to the ring gate delay circuit.

Abstract: A digital communication device having a dual conversion architecture. A first rf-mixing stage is provided followed by a second, quadrature, mixing stage of which output signals are sampled by means of an analog-to-digital converter and supplied to a digital signal processor (DSP) for further baseband processing. The A/D converter is a modified sigma delta analog-to-digital converter. A mixing function is added to the A/D-conversion function by modifying the input stage of a conventional sigma delta bitstream A/D converter. The result is a reduced number of IC-external components and a reduced power consumption.

Abstract: An isolation system is provided for generating a control voltage in a low voltage control system that is representative of the input voltage in a high voltage power system of an excitation system, such as in a rotating electrical apparatus. The control voltage isolation system includes a voltage-controlled oscillator for converting the input voltage into a first frequency signal corresponding to the input voltage. Fiber optic conversion and receiving devices are employed in conjunction with a fiber optic cable to transmit the first frequency signal from the high voltage power system to the low voltage control system. Utilizing a fiber optic device provides voltage isolation between the power system and the control system. The use of a fiber optic device for voltage isolation also resists the damaging effects of relatively high transient currents and voltages from affecting sensitive semiconductor components and the like in the control system.

Abstract: A method is provided for defining programmed values of the boost and cut-off frequency parameters of a low pass filter of pre-equalization, of a read channel for a magnetic medium mass memory device, to ensure optimal functioning conditions of the adaptive filter of final equalization. The method includes pre-programming instantaneous digital values of the boost and cut-off frequency parameters of the low pass filter of pre-equalization for each magnetic medium, as a function of purposely sensed instantaneous operating parameters of the adaptive filter that carries out the definitive equalization of the signal during a trim scanning of the magnetic medium.

Abstract: A method and apparatus for generating pulses that includes a circuit having a dynamical transfer function is disclosed. The circuitry exhibits oscillatory behavior when its operating point is forced to an unstable region of the transfer function by means of manipulating the transfer function. In an embodiment, a voltage source signal is used to manipulate the transfer function of the circuit. By manipulating the transfer function, the operating points can be dynamically set in the stable or the unstable region.

Abstract: Circuit arrangement for controlling an analog voltage signal comprising an input connection for applying the analog voltage signal (UE), a digitizer unit (10) which uses the analog voltage signal (UE) to produce a digital signal (UED) which has a predetermined duty ratio when the analog voltage signal (UE) is at a nominal value, a PI regulator (12) to which, as the input signal, a nominal signal (USD) and an actual signal which is correlated with the digital signal (UED) can be supplied and at whose output a control signal (UST) for controlling the analog voltage signal (UE) can be produced, in such a manner that the control signal (UST) allows the analog voltage signal to be increased if the duty ratio is less than the predetermined duty ratio, allows the analog voltage signal to remain unchanged if the duty ratio corresponds to the predetermined duty ratio, and allows the analog voltage signal to be reduced if the duty ratio is greater than the predetermined duty ratio.

Abstract: A method of and apparatus for the conversion of a frequency modulated signal to a digital output are disclosed. The output of the converter is a triangularly weighted sum of the number of zero crossings of the F.M. signal in each sub-sampling interval over a sampling interval T.

Abstract: A single slope A/D converter utilizes a sub-nanosecond time digitizer to achieve increased conversion rates independent of a high frequency clock, and so is capable of being implemented in diverse applications. High conversion rates ranging from about 3 MHz to about 12 MHz and higher may be implemented on integrated circuits without using a high frequency clock.

Abstract: Methods and apparatus for detecting ultra wide-band signals using circuitry having nonlinear dynamics characteristics are disclosed. The receiver circuit can be implemented using a simple tunnel diode or using an op-amp to provide dynamic characteristics. The detector can be used in a variety of modulation schemes, including but not limited to an ON-OFF keying scheme, an M-ary pulse position modulation scheme, and a pulse width modulation scheme. The approach requires only a single frame to detect the signal.

Abstract: A &Dgr;&Sgr; type AD converter includes a local D/A converter having a SC integrator which is constructed by an analog switch operated at the first and second timings of an input 1, an analog switch operated at the first and second timings of an input 2, an analog switch operated at the first and second timings without selection of the input, a capacitor charged and discharged by these analog switches and an operational amplifier (21), a comparator (22), a D-type flip-flop (28), a switch (29) and reference voltage sources (30, 31).

Abstract: A circuit that digitizes a quantity of light received from a strobe according to the present invention, includes: a photoelectric conversion device that receives light from the strobe and generates an output corresponding to an intensity of the received light; a storage device that stores the output generated by the photoelectric conversion device; a constant quantity discharge device that holds a storage quantity at the storage device close to a specific value by discharging a constant storage quantity from the storage device over a specific period which is in synchronization with a specific sampling frequency and is shorter than the sampling cycle when the storage quantity at the storage device exceeds a predetermined threshold value and by implementing feedback control on the storage quantity at the storage device; and a received light quantity output device that outputs one or more pulse signals when the storage quantity at the storage device exceeds the predetermined threshold value.

Abstract: An analog/digital converter including an amplifier (1) wired as an integrator, a comparator (2) electrically downstream from the integrator, a time counter (6) which continually counts the pulses of a pulse generator (5), a bistable element (4), and additional circuitry. The bistable element (4) drives the input network of the amplifier (1) with at least one switch (3) in such a way that in one of its two positions (“off” condition) a current Ix proportional to the analog measured value is integrated, and in the other position (“on” condition) a constant reference current Iref with opposite polarity to the current Ix is integrated in addition to current Ix.

Abstract: A method for detecting a pulsed usable signal that particularly includes the highest frequencies and possesses a poor signal/noise ratio. First an analog, frequency-limited input signal that corresponds to the usable signal to be detected is formed from the analog input signal through analog filtering. This signal is then converted into a series of digital phase values through a phase/digital converter. First phase difference values are formed from these digital phase values by parallel or serial signal processing, and second phase difference valves are formed from these first difference values. Absolute values of the second difference values are then supplied via a digital low-pass filter to a comparator having hysteresis. There, an output signal that can be digitally utilized and corresponds to the pulsed usable signal is formed by predeterminable threshold values.

Abstract: A control scheme for operating an oscillator/counter A/D converter so that it simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator. The voltage controlled oscillator receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit that, depending on a gate control signal, either blocks the pulses or passes the pulses to either an increment or a decrement port of a digital counter. When the pulses are passed by the gate circuit, the counter circuit accumulates the pulses during a sampling period.

Abstract: A circuit for recovering a signal of interest which is offset by a common mode displacement, such is the case when the signal is the voltage across a current sense resistor located on the high side bus or between the switches of a motor controller circuit. The circuit of the present invention converts the voltage across the resistor into a pulse code modulated data, then downshifts the voltage, and then recovers the signal of interest at the lower voltage by demodulating the signal. The recovered signal is then processed, either with a synchronized sample and hold circuit to provide an analog output, or with a counter and latch to provide a digital output.

Abstract: A method and arrangement for converting an analog input signal into a digital output signal. The analog input signal is converted into a duty cycle modulated square wave. For reducing the communication rate of the digital output signal a time frame of subsampling periods is created and, within each subsampling period, the position of samples, which approximately coincide with the transients of the square wave, is determined. The invention further provides an image sensor comprising a plurality of such arrangements.

Abstract: A method and apparatus for correcting DC offset in a frequency to voltage converter. An analog frequency to voltage converter receives a frequency signal and outputs a voltage signal having a level that is indicative of the frequency of the frequency signal. The frequency signal is also input into a digital processor which converts the frequency signal into a reference signal that is fed back and summed with the voltage signal. The processor integrates the difference between the reference signal and the output signal to drive the output signal to be equal to the reference signal thereby nullifying DC offset in the output signal. The invention can be applied to controlling the DC bus voltage in a variable frequency AC drive.

Abstract: A method for decoding pulse-width modulated signals, such that a sawtooth signal is generated. The sawtooth signal is synchronized with a signal to be decoded. By comparing the sawtooth signal with a reference, a temporal center of a time period reserved for transmission of a bit can be measured, thus reducing a demodulation of the signal to a measurement of the signal level. Furthermore, a data bus for an activation system utilizing this method is also provided.

Abstract: A control scheme for operating an oscillator/counter A/D converter (10) so that it simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter (10) uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator (12). The voltage controlled oscillator (12) receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit (14) that either passes or blocks the pulses depending on a gate control signal. When the pulses are passed by the gate circuit (14), a counter circuit (16) accumulates the pulses during a sampling period.

Abstract: An analog-to-digital converter receives slow-varying analog voltages from a sensing device and converts the slow-varying analog voltages to digital signals. The sensing device generates a slow-varying analog voltage directly proportional to absolute temperature. The analog-to-digital converter includes a second counter which receives the pulse train from the second voltage controlled oscillator that counts the number of pulses which informs the first counter whenever the count value thereof reaches a fixed number and resets the count value thereof to zero. As the first counter is being informed by the second counter, its count value is read and then reset to zero. The read count represents a digital signal corresponding to the slow-varying analog voltages input.

Abstract: The digital sampler circuit processes an output signal from a high gain analog amplifier having as input an infrared motion detector output signal and a negative low pass filtered feedback signal. The amplifier output signal is a substantially square pulse signal having an irregular frequency and duty cycle and has an average duty cycle indicative of a DC level and a slow change in the DC level of the detector output signal. The sampler circuit includes a detector circuit for detecting the amplifier output signal and discriminating at regular intervals a high/low state of the output signal, and generates a high/low feedback signal corresponding to the high/low state of the output signal detected. The high/low state of the output signal is analyzed over a predetermined number of the intervals to obtain a ratio value for producing an output digital signal sample value. The digital sample value is a measure of the DC level and the change in the DC level of the detector output signal.

Abstract: According to the exemplary embodiments, a voltage or current-controlled oscillator is controlled in frequency by the signal (i.e., voltage or current) from a microphone. The frequency modulated signal is applied to a direct digital discriminator that produces a digital representation of the instantaneous frequency at the desired speech sampling rate. The digital discriminator may be formed, for example, by applying the oscillator signal to a direct phase digitizing circuit along with a reference frequency and calculating a sequence of instantaneous phases of the oscillator relative to the reference frequency. The phase sequence is then applied to a digital phase locked loop (or otherwise numerically differentiated) to generate a sequence of binary words representative of instantaneous frequency and therefore representative of the speech waveform.

Abstract: A new method of presenting audio information is disclosed, wherein changes in amplitude and changes in frequency in two channels (stereo) has the additional parameter of phase information added to re-create the feeling of a live performance. Also, all three parameters are converted into duty cycle modulation of a high frequency digital pulse. Conventional loudspeakers and the brain decode the signal to provide audio signals that contain more information than simply frequency and amplitude changes as a function of time.

Abstract: Method and apparatus for processing an analog signal comprising one or more digital data streams encoded as a series of pulses is described. In a preferred embodiment, the analog signal is input to a mixer for mixing the signal with a signal of a local oscillator frequency to increase the frequency of the analog signal. The signal output from the mixer is applied to a narrow band filter such that a series of pulses is output from the filter when a signal of the frequency to which the filter is tuned is applied to the filter. The pulses are detected by a wave shaper, which uses them to identify the presence of a bit transition in the encoded data stream represented by the series of pulses. The wave shaper determines the polarity of the pulse, that is, whether it is positive or negative, which indicates whether the corresponding transition of the encoded data stream is positive or negative, respectively, then uses this information to reconstruct each digital bit, and hence the entire data stream.

Abstract: This invention relates to a microcomputer used to bias an analog signal conversion circuit. The microcomputer is programmed to select between one of two possible signal processing configurations. This is done rather than populating or depopulating components on the module, thus changing the hardware configuration.

Abstract: A circuit is provided to convert an analog signal into a pulse signal, and simultaneously compress the analog signal. The input analog signal buffered by a sample-and-hold circuit is supplied to a chain of amplifier stages having equal gains greater than 1. A set of comparators compares the output signal of each amplifier stage with a reference value. As soon as the output of any amplifier stage exceeds the reference value, a logical summing device coupled to the comparators causes a pulse signal produced by the conversion circuit to become active. A clock signal controls the sample-and-hold circuit to produce a zero level sample-and-hold signal that causes the pulse signal to become inactive. As the amplifier chain is arranged so as to increase its total gain for a lower level of the input analog signal with respect to its total gain for a higher level of the input analog signal, the conversion circuit compresses the input analog signal simultaneously with its conversion into the pulse signal.

Abstract: An analog-to-digital converter utilizing pulse width modulation and ramp and count techniques. A microcontroller generates the pulse width modulated digital signal which is converted into a floating triangle. When the floating triangle signal is equal to the analog, input signal, a comparator generates and output which is sensed by the microcontroller. During an initialization process, the microcontroller uses information with respect to the timing of the comparator output to adjust the duty cycle so that the triangle wave remains within maximum and minimum levels above and below the analog, output signal. Calculation of the voltage, of the input signal is made as a function of the timing of the comparator outputs on successive upward ramps of the floating triangle signal, and of the slope of the upward ramp signal. As a result, the analog-to-digital converter utilizes the same process for low and high resolution measurements, thereby significantly decreasing its cost and increasing its speed.

Abstract: In order to convert an analog signal of digital data transmission into a digital signal, the device embodying the invention comprises a passive analog circuit comprising a capacitor charged by the analog signal via a first resistor, the voltage at the terminals of the capacitor being applied via a second resistor, at the input of a digital circuit comprising a threshold comparator applying, to a flip-flop, a logic signal which is a function of the result of the comparison with a threshold of the voltage at the input, a means for periodically applying at the input a charge or discharge pulse so as to bring the voltage at the input back to the threshold voltage, a counting circuit for periodically determining a number representative of the analog signal, obtained from subtracting the number of discharges from the number of charges.

Abstract: An integrated circuit structure for use in identifying a value of an analog signal includes a central processing unit that executes instructions to perform data processing operations. The data processing operations include a successive approximation analog-to-dialog conversion operation to provide a digital value based upon an input data signal. A pulse with modulation (PWM) element converts the digital value to a square-wave output signal having a duty cycle corresponding to the digital value. A PWM element is adapted for connection to a low pass filter such that the square-wave output signal is provided as an input to the low pass filter. The low pass filter provides an output analog signal corresponding to the duty cycle of the square-wave output signal. An input port is adapted for connection to an output of a comparator. The comparator receives as inputs the output analog signal the low pass filter and the analog signal.

Abstract: A signal processing method includes steps for converting an input analog signal into a pulse width modulated signal, for converting the pulse width modulated signal into a single-bit digital signal, for digitally processing the converted single-bit digital signal into a processed digital signal and for converting the processed digital signal into an output analog signal. The signal processing method advantageously reduces the required memory capacity of the digital signal processor and permits a simplified circuit configuration to be adopted. Several corresponding apparatuses are also described.

Abstract: An analog-to-digital converter employs a sigma-delta modulator that produces a pulsed output with an average duty cycle that varies with an analog input to the modulator. A counter averages the modulator's output duty cycle, and feeds the averaged information onto a one-line transmission circuit for delivery to a remote location. Both the sigma-delta modulator and the counter are synchronized to the same local clock, so that the counter's duty cycle remains substantially constant even if the clock frequency varies. This allows for a simple clock configuration that can be integrated along with the sigma-delta modulator and counter on a single IC chip of reasonable size. When used for temperature sensing, the counter's output duty cycle provides an indication of the locally sensed temperature, independent of temperature-induced variations in the clock frequency.

Abstract: A structure and method of performing an analog-to-digital conversion uses a voltage generator which generates an analog reference signal in response to a clock signal. The analog reference signal is a ramp signal which varies between two on-chip supply voltages. A voltage divider circuit receives an analog input signal to be digitized and the analog reference signal. The voltage divider circuit creates an analog control signal equal to the sum of a predetermined fraction of the analog input signal and a predetermined fraction of the analog reference signal. The analog control signal is provided to a first digital buffer and the analog reference signal is provided to a second digital buffer. The first and second digital buffers provide digital control signals having a first logic state when the applied input signal is less than a threshold voltage and having a second logic state when the applied input signal is greater than the threshold voltage.

Abstract: A voltage to frequency converter including a first selector for receiving an input voltage and for generating an input current based on the control signal. The input current is proportional to the input voltage or an inverse polarity input voltage when the control signal designates plus, or minus integration period, respectively. The converter further includes a second selector for generating a reference current such that the reference current is on/off controlled based on the selection signal and a polarity of the reference current is determined by the control signal, and an integrator for integrating a resultant current of the input current and the reference current to obtain an integrated voltage. The integrator integrates the resultant current complementarily in a forward or in a reverse direction.

Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.

Abstract: A current-to-frequency converter which uses current balancing and pulse width modulation. An analog signal from a measurement instrument, such as an accelerometer, is integrated and transmitted to a pulse width modulator. The output from the pulse width modulator controls feedback signals which in turn control current balancing. The output of the pulse width modulating circuit is also connected to a counter which provides a digital output.

Abstract: An appparatus for receiving signals from any of a plurality of sensor types is provided and includes pull-up circuitry connected to a circuit input; data edge conditioning circuitry having a digital output and an input connected to said circuit input; and an analog output connected to said circuit input and said pull-up circuitry.

Abstract: An analogue to digital converter has input for receiving an analogue signal and a frequency modulator for modulating the frequency of a carrier signal in dependence upon the analogue input signal. A digital counter counts the time between successive events in the modulated signal to provide digital signals representative of the analogue input signal.

Abstract: A pulse circulating circuit includes inverting circuits each for inverting an input signal and outputting an inversion of the input signal. A time of signal inversion by each of the inverting circuits varies in accordance with a power supply voltage applied thereto. One of the inverting circuits constitutes an inverting circuit for starting which is controllable in inversion operation. The pulse circulating circuit circulates a pulse signal therethrough after the inverting circuit for starting starts to operate. An input terminal subjected to an analog voltage signal is connected to power supply lines of the respective inverting circuits for applying the analog voltage signal to the inverting circuits as a power supply voltage fed thereto. A counter serves to count a number of times of complete circulation of the pulse signal through the pulse circulating circuit.

Abstract: An analog-to-digital converter circuit is adapted to control the speed of an electric motor. The circuit in one form comprises a low-pass filter receiving an analog speed instruction voltage, a comparator, a microprocessor incorporating a timer, and an inverter that controls the speed of the motor. The comparator compares the output signal from the filter with a triangular wave having a given frequency and a given amplitude. The output signal from the comparator is applied to the microprocessor, which produces a digital signal corresponding to the speed instruction voltage, by making use of internal clock pulses. The speed of the motor is detected by an encoder. The microprocessor controls the inverter in such a way that the difference between the speed detected by the encoder and the speed indicated by the digital signal becomes null.

Abstract: A multi-channel analog-to-digital converter includes a counter (20) and a plurality of analog-to-digital conversion cells (10), each of which contain incremental discharge means (11-16) that store a charge proportional to the voltage value of an analog input signal and discharge that charge in increments upon the occurrence of the clock signal, also producing an active signal after the charge has been stored and before the incremental discharge is complete. A register (17) receives a count signal from the counter (20) and stores its value when the active signal goes inactive. A multiplexer (18) selects among the outputs of the plurality of analog-to-digital conversion cells (10) and supplies the selected output as a digital output signal.

Abstract: A microcontroller based analog-to-digital converter is disclosed. The microcontroller is coupled to an output of a comparator. The comparator includes an input for receiving an unknown analog voltage and an input coupled to a capacitor. The capacitor is also coupled to the microcontroller through a resistor. Based upon the output of the comparator, the microcontroller provides a pulsed input signal with a predetermined duty cycle to the capacitor. The duty cycles for "high" pulses and "low" pulses are individually set to match a selected input voltage range. The rate at which pulses are applied to the capacitor is adjusted until the voltage on the capacitor matches the input voltage being measured. The pulsed input signal is monitored to establish a pulse count. Based upon the pulse count, the unknown analog voltage value is converted to a corresponding digital voltage value.

Abstract: Method and apparatus for directly converting the value of an analog signal into a digital format for a prespecified number system. For analog to digital residue number conversion, a plurality of residue channels convert the analog value to a set of digitized residues corresponding to a prespecified set of residue bases.

Abstract: An analog to digital signal converter includes an integrator and a sample and hold circuit. Precisely repeatable timing signals for both the integrator and sample and hold circuit are provided by a microprocessor. The device provides low pass filtering without the phase lag normally associated with linear filters. The device allows one set of data to be acquired while the previous set of data is being digitized. The device is especially applicable to analysis of data generated by a spectrophotometer.

Abstract: A technique for reducing the undesirable effects of amplifier offset voltages in quantizers such as analog-to-digital converters and related devices. The quantizer of the invention has an array of input amplifiers for comparing an input signal with multiple reference voltages, an array of latches for registering output signals from the amplifiers, and signal summing circuitry connected between the amplifiers and the latches, to produce a set of modified amplifier outputs for input to the latches, each of the modified amplifier outputs being derived from a weighted sum of at least three amplifier outputs. In the event of a defect in one or more amplifiers causing unwanted amplifier offsets, the summing circuitry improves linearity without the need for paralleling of transistor components. In one embodiment of the invention, the summing circuitry includes a resistor ladder to which the amplifier outputs are connected and from which the modified outputs are derived.

Abstract: A voltage-to-frequency converter provides an output signal, the frequency of which is proportional to the instantaneous level of a reference-frequency signal, which is proportional to the output signal of a parameter-sensing circuit. An up-down frequency counter counts the output pulses of the voltage-to-frequency converter. An up-down control terminal coupled to the reference-frequency signal switches the counting direction of the up-down counter to demodulate the output signal of the voltage-to-frequency converter and to provide a digital output signal representative of the time integral of the amplitude of the parameter being sensed.An undersired input signal is reduced by subtracting a cancellation signal having the format of the undesired signal from the undesired input signal. The filter includes a subtractor, or difference circuit, the output of which is coupled to a voltage-to-frequency converter.

Abstract: A monolithic integrated high resolution analog-to-digital converter based on a charge balancing process, characterized in that the output of a charge balancing integrator is connected to the control input of a pulse width modulator. An output of the pulse width modulator controls the temporal activity of the feedback signal in the charge balancing integrator. The output of the pulsewidth modulator is also connected to a digital calculation circuit which evaluates the pulse width result of the conversion. The input of the analog-to-digital converter is connected to one input of the charge balancing integrator and the feedback signal from the pulse width modulator is connected to the other input.

Abstract: An integrating voltage-to-frequency converter and method for converting a DSB-SC signal into a frequency-encoded signal. The DSB-SC signal is demodulated using an up/down counter, the count direction of which is alternatively switched in synchronism with the phase polarity of a reference carrier signal for the DSB-SC signal. The converter includes an integrator, a comparator, and means for rebalancing the integrator circuit. Means for tracking and storing a partial-bit analog signal level at the output of the integrator are provided, where the partial-bit analog signal level is obtained just prior to a phase transition of the reference carrier signal. The count of the up/down counter is corrected thereby to account for the partial-bit analog signal information.

Abstract: An adaptive analogue-to-digital converter arrangement comprises an analogue-to-digital converter (21) preceded by a variable-gain amplifier (4). In order to provide an accurate measure of the relative gain of the amplifier at each gain setting the output signal of an a.c. reference signal source (12) is frequency-multiplexed with the arrangement input signal applied to an input (1). After conversion to digital form by means of the A/D converter (21) the multiplexed signal is separated into its two components by means of filters (23,24), these being directed to respective bit fields (2A,2B) of an output (2), the reference component after amplitude detection (25).

Abstract: A bipolar analog voltage is converted into a digital signal by sensing the polarity of the voltage and selectively supplying a bias voltage to an analog-to-digital converter, which can preferably be a charge balanced voltage to frequency converter, as a function of the sensed polarity. The voltage to frequency converter has a double valued variable frequency output with a discontinuity at zero volt such that the converter derives a maximum output frequency for a maximum positive voltage and also for a negative value slightly displaced from zero; the voltage to the frequency converter minimum output frequency is derived from positive voltages slightly greater than zero and for maximum negative voltages. The converter output frequency and the sensed polarity are supplied to a frequency to digital converter which derives an output signal having a bit representing the polarity of the analog voltage and additional bits indicative of the magnitude of the analog voltage.