Abstract: In an A/D conversion device, each delay unit in a pulse delay circuit has inverters INV of m×n stages (m, n are positive integers), a clock generator has m-delay lines, and each delay line has inverters INV of i×n stages (i=1, 2, . . . , and m). Those delay lines DL1 to DLm output sampling clocks CK1 to CKm. Each of those inverters INV has a same characteristic. In the A/D conversion device, the delay time in each of the delay lines DL1 to DLm is adjusted by the number of the inverters INV. It is thereby possible to provide the m-sampling clocks CK1 to CKm of a different phase ?T with one another, namely whose phases are preciously shifted by ?T with one another.

Abstract: Digital samples corresponding to a pulsed input signal are provided from an ADC to a memory for storage and to a pulse extraction circuit. The pulse extraction circuit detects the leading and trailing edges of pulses in the input signal. The digital samples are stored in both a Current memory buffer and a Next memory buffer. When a pulse trailing edge is detected, the Current buffer is stopped from storing further samples, the Next buffer becomes the Current buffer and a new buffer becomes the Next buffer. Digital data samples are then provided from the (previous) Current buffer after it has stopped storing samples.

Abstract: A TAD (time analog/digital) type of A/D converter has plural series-connected delay units each producing a delay in accordance with the level of a converter input voltage, with a first-stage delay unit receiving a pulse signal at commencement of each A/D conversion sampling interval, and a latch/encoder circuit detecting the total number of delay units traversed by the pulse signal by the end of the sampling interval, to obtain a numeric value expressing the input voltage level. To ensure uniformity of the delays of the delay units, these are formed using transistors of larger size than transistors of other circuits such as the latch/encoder circuit.

Abstract: The analog-to-digital converter directly acquires a supplied clock signal, generates a current control signal depending on the sampling frequency of the clock signal, so as to control a current value. Thus, it becomes possible to control the current to an optimal value according to the sampling frequency, irrespective of the clock signal generation means, achieving low power consumption in the analog-to-digital converter.

Abstract: The present invention shows a high speed ADC which can be implemented easily and with low cost into a pure digital integrated circuit. This is realized by converting the analog input voltage into a pulse signal and measuring the pulse signal in length with the help of a delay line and an edge detector. With an XOR gate the input pulse can be converted into two pulses of different lengths. With a special calculation circuitry the digital output value becomes independent of the reference frequency used.

Abstract: A self-calibrating sigma-delta converter (SCADC) functions in a calibration mode and in an operational mode. In the calibration mode, a test circuit of the SCADC generates test signals that are periodic rectangular voltage waveforms. Each test signal has a dc component with a precise voltage amplitude, as well as harmonic components. A low-pass filter of a sigma-delta converter (SDC) within the SCADC filters out the harmonic components. A digital calibration processing circuit within the SCADC uses the precise voltage amplitudes to generate digital correction factors that compensate for dc offset error, gain error and INL error of the SDC. In the operational mode, the SDC receives an analog operational signal and outputs an operational digital data stream. The digital calibration processing circuit uses the correction factors to compensate for dc offset error, gain error and INL error in the operational digital data stream and outputs a corrected digital data stream.

Abstract: A time-analog-to-digital converter (TAD) utilizes a time-to-digital approach for analog-to-digital conversion. The TAD includes two voltage-to-delay converters (VDCs), e.g., CMOS inverter chains, in order to increase the dynamic range of the TAD. Each VDC can handle a different range of input voltages. Comparators compare the input signal voltage to reference voltages corresponding to the different ranges of input voltage and a selector selects one of the VDC line outputs based on the range in which the input signal lies. A filter estimates the input signal voltage from a delay signal from the selected output.

Abstract: A technique of processing an input signal having an input signal phase is disclosed. The technique includes determining a number of transitions of the input signal within a period having a start and an end. The technique includes determining a relative beginning phase of the input signal at the start of the period, which includes generating a first reference signal having a first reference signal frequency and a first reference signal phase synchronized with the start of the period, and detecting a first time interval required for the input signal phase to have a first specified relationship to the first reference signal phase. The technique includes similarly determining a relative ending phase of the input signal at the end of the period. The technique includes determining an input signal temporal characteristic from the number of transitions and the relative beginning phase and the relative ending phase.

Abstract: A signal processing circuit can obtain a ratiometric output with high precision and high responsiveness in a relatively easy and simple way. A pulse generation circuit generates a pulse signal corresponding to an input signal. An integration part generates an integrated voltage having a time slope proportional to an input voltage with a duration specified by the pulse signal being set as an integration period. A hold part holds and outputs a difference voltage between a start voltage and an end voltage of the integrated voltage in the integration period. The integration period is specified at the timing of the pulse signal output from the pulse output circuit, and a ratiometric output is generated by sample holding the integral signal.

Abstract: The A/D converter has first and second PPDC circuits (pulse-phase-difference coding circuits). The first PPDC circuit performs A/D conversions on the reference voltage and on the voltage signal amplified by an amplifier in an alternating sequence, the amplifier using the reference voltage as a potential base thereof. The second PPDC circuit performs A/D conversions always on the reference voltage. The A/D-converted data set of the voltage signal outputted from the first PPDC circuit is corrected depending on the difference between the A/D-converted data set of the reference voltage outputted from the second PPDC circuit when the first PPDC circuit A/D-converts the reference voltage and the A/D-converted data set of the reference voltage outputted from the second PPDC circuit when the first PPDC circuit A/D-converts the voltage signal.

Abstract: A method and apparatus for measuring or converting voltage, the method comprising: applying an input voltage to a primary delay line; applying a reference voltage to a timer delay line; propagating a delay signal through the primary delay line; propagating a timer signal through the timer delay line; establishing a sampling period based on the timer signal propagation; and measuring an extent of delay signal propagation along the primary delay line during the established sampling period, the measured signal propagation extent being indicative of a difference between the input voltage and the reference voltage.

Abstract: An A/D converter has a pulse delay circuit including a plurality of inverting circuits to each of which an analog voltage signal is inputted through a first pair of power supply lines. Each of the inverting circuits has a first logic gate. The A/D converter has a logic circuit having a second logic gate and a second pair of power supply lines, the logic circuit operating based on a power supply voltage. At least one of a first range of a level of the voltage signal and a second range of the power supply voltage is set to prevent a tunneling current from flowing at least one of between the first paired power supply lines and between the second paired power supply lines when at least one of first and second logic gates operates.

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

Abstract: An A/D converter for driving a plurality of delay units forming a pulse delay circuit by an analog input signal Vin and digitalizing the number of delay units through which a pulse signal passes in the pulse delay circuit at predetermined timings, provided with a plurality of pulse position digitalizing units used for A/D conversion and inputting delay pulses from the delay units of the pulse delay circuit to the pulse position digitalizing units through an inverter group comprised of inverters with different inversion levels (switching threshold level) by different input timings. The digital data obtained by the pulse position digitalizing units are added by an adder.

Abstract: There is provided a frequency-digital signal conversion circuit for automatically converting a clock frequency into a digital signal. The frequency-digital signal conversion circuit includes: a frequency detecting unit for detecting a frequency of an input clock signal; a latch unit for sampling and latching an output of the frequency detecting unit; and a digital signal generating unit for receiving an output of the latch unit and generating a digital signal of a predetermined bits with respect to the frequency of the input clock signal.

Abstract: A VCO (110) can be configured to convert an analog input signal (105) to a digital output signal (125). In accordance with the inventive arrangements, the VCO can convert the analog input signal to at least one intermediate signal (130) having a frequency dependent on the analog input signal. A frequency detector (115) can be configured to determine a frequency of at least one intermediate signal. Subsequently, a mapping circuit (120) can be configured to map the determined frequency of the at least one intermediate signal to an output value representing the digital output signal (125).

Abstract: A frequency-to-current converter operative to convert a clock frequency to an output current is described; the frequency-to-current converter ensures that the output current increases linearly with the clock frequency. The frequency-to-current converter may be incorporated in analog-to-digital converters driven by clocks with variable frequencies. The frequency-to-current converter employs an integrator circuit, used to compare an input reference voltage and a current feedback into a sampling capacitor. At steady state, the feedback current is just sufficient to discharge the sampling capacitor to a fixed voltage. The core of the frequency-to-current conversion circuit includes one opamp, two capacitors, one feedback transistor and a few switches.

Abstract: The invention concerns a method for determining a numerical value for the duration of a periodically repeating pulsed signal. This method comprises the following steps: a) at time intervals, the period length of the signal is determined; b) at time intervals, a characteristic magnitude for the length of a pulse of that signal is determined; c) a numerical value that characterizes the signal is ascertained from the period length and the characteristic magnitude. Because of its shortness and accuracy, the method is particularly suitable for use in electric motors. A corresponding arrangement is also presented and described.

Abstract: A frequency-to-current converter operative to convert a clock frequency to an output current is described; the frequency-to-current converter ensures that the output current increases linearly with the clock frequency. The frequency-to-current converter may be incorporated in analog-to-digital converters driven by clocks with variable frequencies. The frequency-to-current converter employs an integrator circuit, used to compare an input reference voltage and a current feedback into a sampling capacitor. At steady state, the feedback current is just sufficient to discharge the sampling capacitor to a fixed voltage. The core of the frequency-to-current conversion circuit includes one opamp, two capacitors, one feedback transistor and a few switches.

Abstract: A multi-channel analog/digital (A/D) converter and a system includes a programmable memory on which a channel selection order is recorded, a channel selection unit which selects one of multiple channels according to the channel selection order recorded on the programmable memory, and a converting unit which converts an analog signal of the selected channel into digital data. With the A/D converter, a channel selection order and a sampling rate can be changed without changing the setup of hardware, and time delay can be reduced.

Abstract: A multi-channel superconducting digital router/signal processor (28) for processing and conditioning an analog input signal (12) and converting it to a digital output signal (26). The digital router/signal processor (28) includes a plurality of bandpass filters (11), a plurality of voltage control pulse generators (14), a plurality of pulse splitters (30), a plurality of pulse gates (20), a plurality of pulse combiners (32), a plurality of multiply-accumulator circuits (24), and a digital processing unit (36). The multiply-accumulator circuit (24) can be programmed to any octave of the analog input signal (12). This multi-channel implementation approach provides many conversion functions in a single assembly and is easily scaleable and configurable to meet a wide range of system requirements without having to go through new design/manufacturing cycles.

Abstract: According to the exemplary embodiments, a voltage or current-controlled oscillator is controlled in frequency by the signal (i.e., voltage or current) from a microphone. The frequency modulated signal is applied to a direct digital discriminator that produces a digital representation of the instantaneous frequency at the desired speech sampling rate. The digital discriminator may be formed, for example, by applying the oscillator signal to a direct phase digitizing circuit along with a reference frequency and calculating a sequence of instantaneous phases of the oscillator relative to the reference frequency. The phase sequence is then applied to a digital phase locked loop (or otherwise numerically differentiated) to generate a sequence of binary words representative of instantaneous frequency and therefore representative of the speech waveform.

Abstract: An array of transistor circuits is fabricated so that each transistor circuit in an array of transistor circuits has a switching threshold determined by intrinsic switching thresholds of at least one sensing transistor in a corresponding transistor circuit. The sensing transistors in a set of transistor circuits of the array can be fabricated to have common physical dimensions even though corresponding intrinsic switching thresholds of the transistor circuits can vary. Switching thresholds of the transistor circuits can vary based on an applied well bias voltage. Alternatively, the switching threshold of each transistor circuit can be set to a common value and a tapped delay line can be coupled to the transistor circuits. Consequently, an A/D converter device can be fabricated by coupling an encoder, and a calibration circuit if necessary, to the output of the array of transistor circuits.

Abstract: In a semiconductor device for inverter controlling that includes an AD converter and controls a pulse width of a multi-phase PWM signal on the basis of a digital value obtained by the AD converter, a timer starts counting time in response to a signal supplied from a counter used for generating a PWM signal when the counter has counted a given count value. A timer period of the timer is calculated on the basis of a duty set value stored in a duty set resistor included in a PWM signal generation circuit, and the timer period is stored in a timer period set resistor. The timer generates an AD conversion start factor signal when the timer has counted the timer period stored in the timer period set resistor, and the AD conversion start factor signal is output to the corresponding AD converter so as to start AD conversion. Accordingly, the AD conversion can be definitely started at a time of a predetermined specific ON/OFF combination of the PWM signal.

Abstract: A multiple receiver approach is disclosed for a pulse decoding communication system, which can enhance system robustness and increase information carrying capacity. Two or more receivers are used to produce groups of pulses from a received signal. In one embodiment, system robustness is enhanced by redundancy. In another embodiment, information capacity is increased by producing independent groups of pulses from one cycle of an analog waveform.

Abstract: In a device for analog-to-digital converting an input signal, the input signal is applied to a plurality of delay units constituting a pulse delay circuit in order to change a delay time to be given by the delay units. The number of delay units through which a pulse signal has passed during one period of sampling clocks is numerically expressed. The A/D conversion device has a plurality of pulse position numerizing units that is used for A/D conversion. Sampling clocks of which the phases are different from one another are applied to the respective pulse position numerizing units. An adder summates numerical data items produced by the respective pulse position numerizing units so as to generate final numerical data representing a result of A/D conversion.

Abstract: A signal processing apparatus includes a first signal processor which processes a first channel of signal; and a second signal processor which processes a second channel of signal independently from the processing by the first signal processor.

Abstract: Methods and apparatus for detecting ultra wide-band signals using circuitry having nonlinear dynamics characteristics are disclosed. The receiver circuit can be implemented using a simple tunnel diode or using an op-amp to provide dynamic characteristics. The detector can be used in a variety of modulation schemes, including but not limited to an ON-OFF keying scheme, an M-ary pulse position modulation scheme, and a pulse width modulation scheme. The approach requires only a single frame to detect the signal.

Abstract: An analog-to-digital (A/D) converter converts an analog input signal to a digital representation. The A/D converter has a voltage controlled current source, a Schmidt trigger, a counter, a capacitor, and a transistor switch. The analog input voltage controls the voltage controlled current source. The negative terminal of the current source is coupled to ground, and the positive terminal is coupled to the capacitor, the transistor, and the input of the Schmidt trigger. The other terminal of the capacitor and the drain of the transistor are coupled to a power supply voltage source. The output of the Schmidt Trigger is coupled to the input of the counter. The Reset clock is coupled to the reset terminals of the Schmidt trigger and the counter. The output of the counter represents the digital equivalent of the analog input.

Abstract: An A/D conversion apparatus includes four A/D conversion units, each comprising ring delay lines, pulse selectors for detecting the positions reached by pulse signals in the ring delay lines, encoders for converting the reached positions that are detected into ma-bit digital values, mb-bit counters for counting the number of times the pulse signals have circulated through the ring delay lines, and latch circuits for latching the results counted by the counters. A control circuit sends digital values obtained from the A/D conversion units to a signal processing circuit which adds up together the digital values to calculate a digital value having the number of bits larger than that of the initial digital value.

Abstract: A method and apparatus for detecting ultra wide-band (UWB) signals using multiple detectors having dynamic transfer characteristics. A receiver circuit is implemented using devices such as op-amps to provide the required dynamic characteristics. Detectors used in the UWB communication systems of the present invention utilize direct sequence spread spectrum (DSSS) technology for multiple access reception.

Abstract: A circuit includes a programmable delay circuit to provide a sequence of delayed pulses, an A/D circuit to convert a sequence of values into digital values sampled at times defined by the sequence of delayed pulses, and a jitter correction circuit to adjust the programmable delay circuit based on a sequence of digital values from the A/D circuit sampled at times defined by the sequence of delayed pulses.

Abstract: A method and apparatus for detecting ultra wide-band (UWB) signals using multiple detectors having dynamic transfer characteristics. A receiver circuit is implemented using devices such as op-amps to provide the required dynamic characteristics. Detectors used in the UWB communication systems of the present invention utilize direct sequence spread spectrum (DSSS) technology for multiple access reception.

Abstract: An analog input signal is inputted into a pulse delay circuit including a series combination of delay units. The analog input signal controls signal delay times provided by the respective delay units. A pulse signal is inputted into the pulse delay circuit. The pulse signal is transmitted in the pulse delay circuit while being sequentially delayed by the delay units. Detection is made as to a number of ones among the delay units through which the pulse signal has passed during a setting time from a moment at which the pulse signal is inputted into the pulse delay circuit. Information representative of a level of the analog input signal is generated in response to the detected number.

Abstract: An object of the present invention is to provide an analog-to-digital conversion device that uses pulse delay circuits to convert an input voltage into numerical data and that offers a high resolution in analog-to-digital conversion or a high analog-to-digital conversion rate. The analog-to-digital conversion device includes an analog-to-digital conversion unit having a pulse delay circuit composed of a plurality of delay units. The delay units are driven with a voltage produced by amplifying or shifting an input voltage. The number of delay units through which a pulse signal has passed during a predetermined sampling cycle is adopted as a digitized value of the input voltage. Herein, delay units constituting another pulse delay circuit are driven with a voltage produced by inversely amplifying or shifting the input voltage.

Abstract: A multiple receiver approach is disclosed for a pulse decoding communication system, which can enhance system robustness and increase information carrying capacity. Two or more receivers are used to produce groups of pulses from a received signal. In one embodiment, system robustness is enhanced by redundancy. In another embodiment, information capacity is increased by producing independent groups of pulses from one cycle of an analog waveform.

Abstract: A method of presenting audio information where changes in amplitude and changes in frequency in two channels (stereo) have the additional parameter of phase information added to re-create the feeling of a live performance. Also, all three parameters are converted into duty cycle modulation of a high frequency digital pulse. Conventional loudspeakers and the brain decode the signal to provide audio signals that contain more information than simply frequency and amplitude changes as a function of time.

Abstract: A method and apparatus for generating pulses that includes a circuit having a dynamical transfer function is disclosed. The circuitry exhibits oscillatory behavior when its operating point is forced to an unstable region of the transfer function by means of manipulating the transfer function. In an embodiment, a voltage source signal is used to manipulate the transfer function of the circuit. By manipulating the transfer function, the operating points can be dynamically set in the stable or the unstable region.

Abstract: A signal processor circuit that buffers a ground-referred, signal-dependent, current. A ground-referred node in the circuit is preferably maintained at a ground level. The ground-referred, signal-dependent, current is preferably buffered such that the ground-referred node is preferably maintained at a ground level independent of changes to the ground-referred, signal-dependent, current.

Abstract: A decoder for generating output pulses or oscillations in response to input analog waveforms includes a circuit having a variable operating point and having a transfer function characterized by an unstable operating region bounded by a first stable operating region and a second stable operating region. In one embodiment, the circuit is characterized by having a resistive input impedance. The analog waveform forces the operating point of the circuit into its unstable and stable regions to produce oscillatory and non-oscillatory behavior at the circuit's output.

Abstract: According to an embodiment of the present invention, an input signal is provided to an oscillator, which creates a count signal with a greater frequency than the input signal. The input signal triggers the oscillator to oscillate depending on the value of the input signal. The oscillator output is provided to a counter, which counts the number of oscillations undergone by the oscillator during a single period of the input signal or a number of periods of the input signal, whichever is desired. Since the oscillator frequency is greater than the frequency of the input signal, the oscillator effectively acts like a clock to time the input signal; the counter effectively acts to record the ‘time’ measured by the oscillator (clock). More formally, the counter generates a count value based upon the width of the input signal pulses. The counter output is provided to a decoder, which interprets the count generated by the counter.

Abstract: For the realization of a unipolar analog input range, in addition to the provision of an analog input sampling circuit having an input capacitor, a charge transfer circuit, an integrator having an integrating capacitor, a comparator, and a D-type flip-flop, there is further provided a reference voltage sampling circuit for selectively adding either of a subtraction and addition voltages which are different from each other to a sampled analog input voltage in response to a delayed comparator output. The reference voltage sampling circuit has a subtraction and addition capacitors differing in capacitance value from each other.

Abstract: A method and system for selecting implementation of a filter controller between a single conversion that ensures a fully-settled converted output and a continuous conversion of an input signal are disclosed. State machine determines whether convert start signal has a duration, which ends on or before a first occurrence of a conversion done on the input signal. Conversion done is an occurrence of when a bit set has been converted from the input signal. If convert start signal has a duration which ends on or before the first occurrence of conversion done, then state machine selects and implements single conversion of the input signal. Digital system ensures a fully-settled converted output by waiting for the filter to receive and filter a predetermined number of bit sets for a conversion output and then outputting the conversion output. Otherwise, state machine selects and implements continuous conversion of the input signal.

Abstract: An analog input voltage signal to be A/D-converted is supplied to a ring gate delay circuit including inverting circuits connected in series in a ring as a supply voltage thereto. The interval for which a pulse circulates the ring varies with the analog input voltage signal. The number of times circulation of the pulse and the position of the pulse for a predetermined interval are detected by a counter to provide upper bits and by a pulse position detector to provide lower bits of A/D conversion result of the analog input voltage signal, respectively. The counter and the pulse position detector are included in a coding process block which is driven by a constant voltage which is different from the analog input voltage signal to the ring gate delay circuit.

Abstract: Methods and apparatus for detecting ultra wide-band signals using circuitry having nonlinear dynamics characteristics are disclosed. The receiver circuit can be implemented using a simple tunnel diode or using an op-amp to provide dynamic characteristics. The detector can be used in a variety of modulation schemes, including but not limited to an ON-OFF keying scheme, an M-ary pulse position modulation scheme, and a pulse width modulation scheme. The approach requires only a single frame to detect the signal.

Abstract: The invention relates to a sensor signal converter for machine tools and production machines, and also robots, which generates pulsed signals from sensor values transmitted via a drive bus. The sensor signals (GU1, GU2) can be transmitted on the drive bus (AB1-AB4) in real time, can be converted into sensor-compatible pulsed signals by a sensor signal converter (GU1, GU2) in real time and can be sent to other appliances, optionally in real time. The data link (AB1-AB4) having real-time capability which can be used is an Ethernet having real-time capability.

Abstract: A multiple receiver approach is disclosed for a pulse decoding communication system, which can enhance system robustness and increase information carrying capacity. Two or more receivers are used to produce groups of pulses from a received signal. In one embodiment, system robustness is enhanced by redundancy. In another embodiment, information capacity is increased by producing independent groups of pulses from one cycle of an analog waveform.

Abstract: Methods and apparatus for varying and measuring the position of a micromachined electrostatic actuator using a pulse width modulated (PWM) pulse train are disclosed. One or more voltage pulses are applied to the actuator. In each of the pulses, a voltage changes from a first state to a second state and remains in the second state for a time tpulse before returning to the first state. The position of the actuator may be varied by varying the time &Dgr;tpulse. A position of the actuator may be determined by measuring a capacitance of the actuator when the voltage changes state, whether the time t is varied or not. An apparatus for varying the position of a MEMS device may include a pulse width modulation generator coupled to the MEMS device an integrator coupled to the MEMS device and an analog-to-digital converter coupled to the integrator. The integrator may measure a charge transferred during a transition of a pulse from the pulse generator.

Abstract: An analog input signal is inputted into a pulse delay circuit including a series combination of delay units. The analog input signal controls signal delay times provided by the respective delay units. A pulse signal is inputted into the pulse delay circuit. The pulse signal is transmitted in the pulse delay circuit while being sequentially delayed by the delay units. Detection is made as to a number of ones among the delay units through which the pulse signal has passed during a setting time from a moment at which the pulse signal is inputted into the pulse delay circuit. Information representative of a level of the analog input signal is generated in response to the detected number.

Abstract: A folding circuit is provided for outputting a periodic function representative of an analog input signal. The circuit includes at least two preamplifiers and a third differential amplifier circuit coupled to the preamplifier circuits for providing a bias current such that the flow of current is regulated through one of the preamplifier circuits at any given time, thereby providing a periodic function representative of an analog input signal.