Abstract: A drawing device includes a distinguish unit for distinguishing figure description information in scene data of each figure in a display screen, for tiles included in the display screen; an aggregation unit for aggregating a data size of the figure description information corresponding to the tiles; an address determination unit for determining a leading address in a memory area for storing the figure description information corresponding to each of the tiles, based on an aggregation result of each tile; and a memory write unit for sequentially writing, in the memory area, the figure description information distinguished as corresponding to the tiles, starting from the leading address determined for each corresponding tile, wherein the address determination unit determines the leading addresses so that the memory areas for storing the figure description information corresponding to the tiles are arranged in a physical address space in an order of drawing the tiles.

Abstract: Presented herein are systems, methods, and apparatus for displaying pictures. In one embodiment, there is presented a decoder system for decoding video data. The decoder system comprises a port and a transport processor. The port receives packets carrying encoded video data from a plurality of video streams. The transport processor adds a header to encoded video data from at least one of the packets. The header identifies a particular one of the plurality of video streams, wherein the at least one packet is from the particular one of the plurality of video stream.

Abstract: In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation misses in the display pipe (at least in most cases). The translation units may maintain translations in first-in, first-out (FIFO) fashion, and the display pipe fetch hardware may inform the translation unit when a given translation or translation is no longer needed. The translation unit may invalidate the identified translations and prefetch additional translation for virtual pages that are contiguous with the most recently prefetched virtual page.

Abstract: An image display device includes a timing controller capable of overdriving. The timing controller has three line buffers, an image reverse processing unit, and an overdrive unit. The first line buffer buffers first line data of a second frame, wherein the second frame is generated later than a first frame. The second line buffer buffers first compressed data. The image reverse processing unit estimates first and second line data of the first frame according to the first compressed data. According to the first and second line data of the first and second frames, the overdrive unit outputs first and second lines of interleaving data for an interleaving frame. The interleaving frame is inserted between the first and second frames. With the third line buffer, the timing controller outputs the first and second lines of interleaving data at different time point.

Abstract: There is provided an information processing device including: a light emitting unit to supply light to an operating means mounted on an IC card, the operating means being capable of switching display contents on a display unit of the IC card by a potential difference occurring due to photoelectric conversion; a communication unit to transmit given data to the IC card for causing the IC card to record the data; and a light emission adjusting unit to cause the data recorded on the IC card through the communication unit to be displayed on the IC card by adjusting the number of times of emitting light or a light emitting pattern from the light emitting unit.

Abstract: A method and apparatus for displaying image data on a display device is disclosed. In some embodiments, the method includes updating at least a portion of the display device based on image update data identifying pixels that changed from the preceding image to the following image.

Abstract: Addressing method for multiple chips is provided. Each chip includes an input enable terminal, an output enable terminal, a data input terminal, and a clock terminal. The output enable terminal of a previous stage is connected to the input enable terminal of a next stage. The method includes setting an initial address to an address of each chip via a system; setting a state of each chip to a disable state; enabling the state of a first-one chip among the chips to an enable state, and setting the first chip as a previous-stage chip; updating the address of the previous-stage chip; enabling a next-stage chip connected after the previous-stage chip, in which the system controls the output enable terminal of the previous-stage chip to output an enable signal to enable the next-stage chip, according to the address of the previous-stage chip; and the updating the address of the next-stage chip.

Abstract: An image display system includes: a frame buffer including plurality of lines; a memory controller conducting writing and reading operations with the frame buffer; an image data provider supplying image data to the memory controller and generating a writing address; a display controller generating a reading address and receiving image data that is read from the frame buffer by the memory controller; a tearing-protection bus arbiter storing a burst length, receiving the writing and reading addresses, and selectively outputting the writing and reading addresses; and a display device displaying the image data by the display controller. The reading address contains a start address for the reading operation and the writing address contains a start address for the writing operation.

Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. The coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.

Abstract: A method involving receiving an indication of a requirement to allocate at least one page for a process, where pages are associated with cache colors; generating a selection bitmap by performing a logical operation of a system available colors bitmap and a process bitmap, where the system available colors bitmap and the process bitmap each include one bit corresponding to each cache color, where each bit of the system available colors bitmap indicates whether a number of pages associated with a corresponding cache color that are available to be allocated is above a minimum threshold, and where each bit of the process bitmap indicates whether any pages associated with the corresponding cache color have been recently allocated for the process. The method also includes selecting, using the selection bitmap, a cache color; and allocating a page for the process, wherein the allocated page is associated with the selected cache color.

Abstract: An image processing system includes a memory for storing data associated with pixels of images, with the pixels having spatial coordinates in an image coordinate system having first and second axes; a processing device including a processor which processes the associated data; and an interface device which accesses in memory addresses associated with pixels of a block of pixels. In the interface device, access information is received indicating a base memory address, information regarding the dimensions of the block along the axes of the image coordinate system, and a storage method. At least one access rule is selected from multiple rules as a function of the storage method. The memory is accessed at the addresses associated with the pixels in the block, by applying the selected rule starting from the base address and taking into account the dimensions of the block.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: A self-addressing control unit system and method for controlling a sequence of or an array of display signs comprising of a remote or master controller and a plurality of control units interconnected by a physical or logical parallel electrical bus having multiple connections to transfer data or power between the plurality of control units; wherein the electrical bus further comprises of a main broadcast line, an addressing line and a feedback line to every control unit. The remote or master controller transmits an initial address to a first of the plurality of control units on the addressing line of the bus where a calculator or computer within each of the plurality of control units computes its own address by performing a mathematical operation that changes the initial address by adding a constant of one to the address received to produce its own new address.

Abstract: Apparatus, systems and methods for the simplification of 3D texture address computations based on aligned, non-perspective objects are disclosed. For example, a method is disclosed including receiving a texture address of a first pixel and determining a texture address of a second pixel by applying at least one offset to the texture address of the first pixel. Other implementations are also disclosed.

Abstract: Various exemplary embodiments provide methods of controlling frame memory, memory control circuits, and image processing apparatuses including the memory control circuits. Data representing values of pixels constituting each of a plurality of frames are received in an order of the frames, and data representing values of pixels constituting a previous frame are read from the frame memory and data representing values of pixels constituting a next frame are written to the frame memory. By reading first data representing values of a portion of the pixels constituting the previous frame from the frame memory before receiving of data representing values of pixels constituting the next frame starts, a delay time before starting to output data representing values of pixels of the previous frame can be shortened.

Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. Next the coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and on the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.

Abstract: Cross-environment rendering and user interaction support provide a seamless computing experience in a multi-operating system computing environment. The multi-operating system computing environment may include a mobile operating system and a desktop operating system running concurrently and independently on a mobile computing device. Real-time or instant display of an application running in the mobile operating system within an environment of the desktop operating system is provided by rendering application graphics for the application within the desktop operating system. A console application of the desktop operating system may access surface information for the application from shared memory and render the application within a console window of the computing environment associated with the desktop operating system. The mobile computing device may be a smartphone running the Android mobile operating system and a full desktop Linux distribution on a modified Android kernel.

Abstract: A digital display with image data storage memory that minimizes the impact of defective memory cells by remapping stored image data. Memory defects may be detected by automatic or visual testing. The digital display may perform a mapping process such that image data placed in the location of the defective storage cells is based on the significance of the data, both by bit and by color. The mapping process may operate on addressed rows of memory cells of the digital display.

Abstract: A hardware-based aperture compression system permits addressing large memory spaces via a limited bus aperture. Streams are assigned dynamic base addresses (BAR) that are maintained in registers on sources and destinations. Requests for addresses lying between BAR and BAR plus the size of the bus aperture are sent with BAR subtracted off by the source and added back by the destination. Requests for addresses outside that range are handled by transmitting a new, adjusted BAR before sending the address request.

Abstract: A system and method for generating an image on a display. The display includes a plurality of pixels from a vector description of a scene. The data is sampled from the vector description to provide data samples at locations defined in relation to the pixels. For example, the locations may include a first and second locations at the edges of the pixels, a third location at the corner of the pixels and a fourth location at the center of the pixels. The data samples are stored in a buffer and processed for each of the pixels to give an averaged data value. The image is then generated the image on the display by applying the averaged data value to each of the pixels. The calculation of the weighted averaged color value is repeated for each of the fragments in the buffer until all of the samples have been averaged.

Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.

Abstract: A table-based driving circuit for displays that switches between a normal operational mode and a read table block mode. The driving circuit comprises an address sequencer and a memory. The memory comprises the full table of individual sequences, such as interlacing or color-sequential sequence. In the read table mode, the next upcoming addresses are read, i.e. are downloaded, from the memory into an address table register in the address sequencer. In the normal operational mode, the address sequencer generates the addresses for the video data to be stored in the memory or to be displayed.

Abstract: A map distribution system includes a map distribution server that distributes map data to a navigation device. The server includes a first table having entries that each include update data in correspondence with an ID for the update data and an ID for each other update data upon which the update data depends, a second table having entries that each include an area ID of an area of the map data in correspondence with a version of the area and the ID for each update data that is applied in the version of the area, and an update manager that refers to the second table to select the ID for each update data required for updating an area selected based on input from the navigation device and the required ID for each other update data upon which any update data required for updating the area selected depends.

Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.

Abstract: Stochastic dithering may be used to reduce the size of the frame buffer and the complexity of the D/A Converters (DACs) in the drive circuitry that are used in a video display system. Hardware for stochastic dithering can be simplified when pixel data is presented in raster order. The hardware adds algebraic noise to the image to be dithered, and thresholds the result.

Abstract: A “Variable-Rate Perfect Hasher” maps sparse variable-rate data of one or more dimensions into a hash table using a perfect hash function. In various embodiments, perfect hash tables are populated by first computing offset table address for each data point of a domain of sparse variable-rate data elements. Offset vectors are then computed for each offset table address based in part on the size of each data element by evaluating offset vectors in order of a sum of the data point addresses mapping to each offset vector. These offset vectors are then stored in the offset table. For each data point, the corresponding offset vector is then used to compute a hash table address. Data elements are then perfectly hashed into the hash table using the computed hash table addresses. The resulting hash tables support efficient random access of the variable-sized data elements stored therein.

Abstract: A data processing apparatus generates a memory address corresponding to a first memory, and interpolates data read out from the first memory. The data processing apparatus selects a part of the memory address, checks if the first memory stores data corresponding to the selected part of the memory address, and transfers the data, for which it is determined that the first memory does not store the data, and which corresponds to the part of the memory address, from a second memory to the first memory. The data processing apparatus determines to change a part to be selected of the memory address based on the checking result indicating that the first memory does not store the data corresponding to the selected part of the memory address, and changes the part of the memory address corresponding to the characteristics of the memory address.

Abstract: One embodiment of the present invention sets forth a technique for a program to access multi-dimensional formatted graphics surface memory. Multi-dimensional memory objects called “surfaces” stored in a user-specified data or pixel format and arranged in a graphics optimized layout are accessed by programs using surface instructions. A set of memory access instructions e.g., load, store, reduce, and atomic, referred to as surface instructions, may be used to access the surfaces. Coordinate bounds checking is performed with configurable clamping. Caching behavior may also be specified by the surface instructions. Data format conversion and packing to a specified storage format is supported for store, reduction, and atomic surface instructions. Data format conversion and unpacking from a specified storage format is supported for loads and atomic surface instructions.

Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.

Abstract: Disclosed herein are methods, apparatuses, and systems for accessing vertex data stored in a memory, and applications thereof. Such a method includes writing vertex data of primitives into contiguous banks of a memory such that the vertex data of consecutively written primitives spans more than one row of the memory. Vertex data of two consecutively written primitives are read from the memory in a single clock cycle.

Abstract: Presented herein are a system, method, and apparatus for retrieving an object from memory. The object can be stored in a manner, such that the first byte of the object and the last byte of the object are in the middle of the memory data words. The object is retrieved by a direct memory access controller. The direct memory access controller, when provided with a read transaction with the starting address and the ending address of the object, retrieves the data words storing the object, and overwrites the portions of the data word that precede and follow the object.

Abstract: Addressing method for multiple chips is provided. Each chip includes an input enable terminal, an output enable terminal, a data input terminal, and a clock terminal. The output enable terminal of a previous stage is connected to the input enable terminal of a next stage. The method includes setting an initial address to an address of each chip via a system; setting a state of each chip to a disable state; enabling the state of a first-one chip among the chips to an enable state, and setting the first chip as a previous-stage chip; updating the address of the previous-stage chip; enabling a next-stage chip connected after the previous-stage chip, in which the system controls the output enable terminal of the previous-stage chip to output an enable signal to enable the next-stage chip, according to the address of the previous-stage chip; and the updating the address of the next-stage chip.

Abstract: A flat panel display device and a picture quality controlling method thereof is provided. The flat panel display device includes a display panel. A memory stores location information about a panel defect location on the display panel and a compensation value to be dispersed for a plurality of frame periods. A compensating part detects the data to be displayed at the panel defect location and adjusts the data to be displayed at the panel defect location with the compensation value from the memory.

Abstract: A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D graphics pipeline are patchable. A scheduler includes a decode table, an expansion table, and a resource table that are each patchable. The decode table translates high level instructions to an appropriate microcode sequence. The patchable expansion table expands a high level instruction to a program of microcode if the high level instruction is complex. The resource table assigns the units for executing the microcode. Addresses within each of the tables can be patched to modify existing instructions and create new instructions. That is, contents in each address in the tables that are tagged can be replaced with a patch value of a corresponding register.

Abstract: A system and method for storing a multidimensional array of data, such as a two dimensional (2-D) array of video data, in a non-contiguous memory space. The system and method maps individually indexed elements of a multidimensional array of data from a source device into blocks of non-contiguous memory available in a destination memory system, even when the destination blocks are small and/or their size does not correlate in any way to the dimensions of a source buffer. In particular, the blocks of non-contiguous memory may be as small as a single element of the data indexed in the 2-D array.

Abstract: A digital image displaying system includes a DPF and an electronic device communicating with the DPF. The DPF has identification information. The electronic device includes a DPF detecting submodule, a image storing submodule for storing digital image files, a DPF managing submodule, and an information transmitting submodule. The DPF detecting submodule detects identification information of the at least one DPF, the DPF managing submodule stores the identification information therein, the information transmitting submodule transmits network location paths of the digital image files of the image storing submodule to the at least one DPF, the at least one DPF receives the network location paths and displays the digital image files stored in the image storing submodule according to the network location paths. A method for displaying digital image files is also provided.

Abstract: A video scaler may include a scaler core and an output memory having a reduced size. An image processing apparatus may include a video scaler with a scaler core and an output memory with a reduced size. The scaler core may scale input image data and store the scaled image data in the output memory. The image processing apparatus may read image data from the output memory a reduced storage time.

Abstract: A memory device, a signal processing apparatus, and an image signal processing apparatus and signal processing methods configured to perform matching processing with a small amount of calculation and accurately detecting motion vectors, provided with a memory for converting by using a feature including a pixel value in a certain block range having a focused pixel at its center as an address based on information of a reference frame stored in a second frame memory; and a matching portion for reading storage information of the ME memory by using a feature of a focused pixel included in information of a current frame supplied from a first frame memory as a feature address, calculating a distance between the focused pixel in the current frame and a feature address (position coordinates) read from the ME memory, and detecting differential coordinates based on position information having the minimum distance from a plurality of candidates as motion vectors of the focused pixel.

Abstract: A display control device includes a memory that stores display data to be displayed on a display section, an operation section that specifies a display area of the display section where the display data is displayed, an address setting section that sets a setting address value with respect to a memory address of the display data stored in the memory, an address specifying section that specifies a read start address value of the display area with respect to the memory address based on a first operation amount of the operation section, and a specified address changing section that changes, when the read start address value is equal to the setting address value, the read start address value to a different address value.

Abstract: An image displaying device comprises a reproduction list creating unit for creating a group of image data within a prescribed range in which a frame number “1” is included and the frame number increases as a first reproduction list and for creating a group of image data within a prescribed range in which a largest frame number is included and the frame number decreases as a second reproduction list, a display controlling unit for reproducing and displaying image data of a frame to be reproduced registered in the second reproduction list in the case that the frame number is set in a direction along which the frame number decreases below the frame number “1” while image data registered in the first reproduction list is reproduced.

Abstract: A method of generating a stream of non-contiguous memory addresses representing contiguous points in logical space is described. The method comprises: generating initializing parameters describing the contiguous points in the logical space; configuring a memory address engine with the initializing parameters; performing an algorithm in the memory address engine according to the initialising parameters to produce a plurality of non-contiguous memory addresses; and collating the non-contiguous memory addresses into the stream of memory addresses for output to a data memory. The present invention has particular application to SIMD processing techniques where there are a plurality of memory address engines.

Abstract: Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory to store corresponding data; a first processor to separate the action script from other data; and a second processor to convert a plurality of descriptive elements of the action script into a plurality of operational codes, and to perform an operation corresponding to an operational code of the plurality of operational codes using the corresponding data to generate pixel data for the graphical image. In exemplary embodiments the second processor further is to parse the action script into the plurality of descriptive elements and the corresponding data, and to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

Abstract: The invention relates to a address calculation unit (15) for region based image processing tasks, where a processing unit (15) processes the data and exchanges the processed data between a global memory (11) and a local memory (12), wherein the address calculation of region-based algorithms is performed by the address calculation unit in parallel to the date processing of the and the actual processing of data.

Abstract: A method and apparatus for hardware rotation is described. In one embodiment, the invention is an apparatus. The apparatus includes a direct access address translation component. The apparatus also includes a frame buffer coupled to the direct access address translation component. The apparatus further includes a 2D coordinate translation component. The apparatus also includes a 2D engine coupled to the 2D coordinate translation component and to the frame buffer. The apparatus further includes a 3D engine. The apparatus also include a 3D coordinate translation component coupled to the 3D engine and the frame buffer. As will be appreciated, further embodiments of the invention are within the spirit and scope of the claimed invention, and the specific details of a specific embodiment as described need not be present in all embodiments of the invention.

Abstract: A computer system in which a graphics accelerator unit manages page faulting of texture data invisibly to the host processor.

Abstract: In the display of an image including a fixed background image and a variation image of the background image, at least one of the amount of data to be held and the amount of work to be processed is reduced. A display control device acquires pixel description data including a combination of position information for specifying a position on a pixel array and address information for specifying an address in an image storage unit of image data which is displayed at the position specified by the position information. Furthermore, the display control device reads out the image data from the address of the image storage unit specified by the address information and specifies the position on the pixel array specified by the image description data to the display to input the read out image data.

Abstract: A semiconductor device includes a data acquisition unit which acquires first graphic data including a first drawing position in a drawing region, and acquires second graphic data including a second drawing position different from the first drawing position in the drawing region located later than the first graphic data, a detector which detects positions in a first direction in the drawing region of the first drawing position and the second drawing position, and a controller which causes drawing information at the first drawing position and drawing information at the second drawing position to be continuously stored in a memory when the positions of the first drawing position and the second drawing position in the first direction are similar.

Abstract: A display controller includes a memory storing at least three frames of image data, a write starting address register to which a write starting address is set, a read starting address register to which a read starting address is set, and a rotation control section performing control for reading out from the memory image data corresponding to an image whose orientation is rotated. When writing of the image data to the area designated by the write starting address is completed, the write starting address is updated and the previous value of the updated write starting address is set to the read starting address register. The image data corresponding to the rotated image is read out by the rotation control section 40 from an area of the memory designated by the read starting address, and then supplied to a display driver.