Abstract: The latency of a PSRAM is set according to its current state when receiving an external command. If the PSRAM is not executing a specific operation or has completed the specific operation while meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a first latency. If the PSRAM is executing the specific operation or has completed the specific operation before meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a second latency larger than the first latency.

Abstract: A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

Abstract: The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array. Further, erase signal generation circuitry is configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses. The erase signal generation circuitry is further configured to issue said erase signal in said asserted state if the control signal does not take the form of said pulse signal.

Abstract: Apparatuses and methods for capturing data in a memory are disclosed herein. An apparatus may include a command path and a data capture logic. The command path may be configured to receive a command signal and to delay the command signal with a delay based, at least in part, on a plurality of propagation delays. The data capture logic may be coupled to the command path and configured to receive the delayed command signal and a data strobe signal. The data capture logic may further be configured to capture data according to the data strobe signal responsive, at least in part, to receipt of the delayed command signal.

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate, or combination thereof.

Abstract: A method for reading data from a plurality of DRAM devices connected to common command, address, and data busses. A clock signal is provided to the plurality of DRAM devices. A read command and address to the plurality of DRAM devices on the command and address busses in synchronization with the clock signal. A read clock signal is provided to the plurality of DRAM devices to initiate a read operation in one of the plurality of DRAM devices that is selected by the address. The one DRAM device delays the read clock signal by an amount based on a speed of the one of the plurality of DRAM devices to generate. First delayed read clock and second delayed read clock signals are provided. The read data is received on the data bus in synchronization with the second delayed read clock signal.

Abstract: A glitch circuit includes an SR flip-flop where a received input clock is operatively coupled to set and reset inputs of the flip-flop, respectively. A configurable delay circuit receives an input signal, and an output of the delay circuit provides a delayed signal. The configurable delay circuit includes a plurality of switchable taps, each providing an increment of delay to the input signal. The delay circuit input is operatively coupled to an output of the flip flop, and an output of the delay circuit is operatively coupled to the inputs of the flip-flop. The glitch circuit captures a first signal transition of the input clock and blocks all other transitions from propagating through the flip-flop during a selected delay period so as to provide on an output of the flip-flop, the glitch-free output clock.

Abstract: A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value.

Abstract: A semiconductor memory apparatus includes a data alignment control signal generation unit configured to output a data alignment control signal by generating a pulse when a tuning mode signal is enabled, and generate the data alignment control signal as a count pulse is inputted after the data alignment control signal generated by the tuning mode signal is outputted; a timing control block configured to determine a delay amount according to delay codes, generate a delay control signal by delaying the data alignment control signal, and output a timing control signal by latching the delay control signal at an enable timing of a data output control signal; a delay time control block configured to generate the delay codes; and a data alignment unit configured to convert parallel data into serial data, and change a data sequence of the serial data in response to the timing control signal.

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract: A data output circuit of a semiconductor device includes: a pattern data generation unit configured to generate pattern data in response to a bank selection signal, a variable delay unit configured to delay a source signal, which is generated in response to the bank selection signal, by a delay time corresponding to a delay control signal, a pattern control signal generation unit configured to generate a pattern control signal in response to an output signal of the variable delay unit, and a delay time control block configured to generate the delay control signal in response to the phases of the pattern control signal and the pattern data.

Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.

Abstract: A memory device includes a decoder circuit configured to activate a setting signal and a write signal if a setting command is applied when a reference mode is set; a delay circuit configured to delay and to generate a delayed write signal; and a setting circuit configured to perform a setting operation in response to the delayed write signal and an input signal of a predetermined pad at the time of setting of the reference mode and to perform the setting operation in response to the setting signal when the reference mode is not set.

Abstract: A system includes a first chip configured to supply a training command and a second chip configured to transfer to the first chip a measured time for performing an operation in response to the training command.

Abstract: A mechanism is presented memory circuits, such a NAND-type flash memories, to autonomously protect themselves from temporary and short power drops. A detection mechanism looks for the supply voltage to drop below a function voltage for a period of time. When such an event occurs, a suspend mechanism is activated, and after completing the last micro-operation (such as a program pulse) the memory freezes. When power is again stable at an operational level, the suspended operation is resumed. The memory controller can then be notified upon occurrence of such voltage drop by polling a special status bit. Examples of how the pausing can be implemented include altering of clock signals and suspending sub-phases of larger operations.

Abstract: An integrated circuit may include memory interface circuitry for communicating with off-chip memory. The memory interface circuitry may receive data signals and data strobe signals from different memory devices via respective data ports and data strobe ports. The memory interface circuitry may be operable in at least first and second modes. In the first mode, data signals from each memory device may be received at two respective data ports while the data strobe signal from one memory device is used to clock the data signals at two corresponding read capture registers. In the second mode, data signals from first and second memory devices may be received via first and second data ports, respectively. The data strobe signal from the first memory device may be ignored while the data strobe signal from the second memory device is used to clock the data signals at two corresponding read capture registers.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: A nonvolatile memory device is provided comprising a memory cell array including first and second memory cells. Data is stored at the first memory cell. The device further comprises an access control circuit configured to read the data stored at the first memory cell and to subsequently perform a data processing operation on the second memory cell contemporaneously with a reprogramming operation performed on the first memory cell. The reprogramming operation on the first memory cell is selectively performed based on a determination whether a state of the first memory cell is changed while the data stored at the first memory cell is read.

Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.

Abstract: An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal.

Abstract: A device includes a plurality of memory areas each including a plurality of memory cells required to perform refresh of information stored therein by a plurality of sense amplifiers, a first control circuit determining, in connection with one refresh requirement signal at a time, a number of refresh-target memory areas to produce a determined number, a second control circuit controlling, in accordance with the one refresh requirement signal at a time, refresh operation with respect to the refresh-target memory areas, and a third control circuit adjusting, in connection with the refresh operation, an active time-out time interval according to the determined number. The active time-out time interval indicates a time interval from a first time instant when the sense amplifiers are activated to a second time instant when word lines related to the refresh-target memory areas are inactivated.

Abstract: Systems and methods are disclosed relating to semiconductor memory devices. According to some exemplary implementations, there are provided innovations associated with power and ground pads in devices such as static random access memory (“SRAM”) devices and dynamic random access memory (“DRAM”) devices. Moreover, the systems and/or methods may include features such as minimization of simultaneous switching outputs (SSO) effects relating to echo clock circuitry.

Abstract: The first input circuit detects an input signal to output a first output signal having the same phase as the input signal. The second input circuit is configured to detect a first strobe signal to output a second output signal. The third input circuit is configured to detect a second strobe signal as a reversed signal of the first strobe signal to output a third output signal. A data latch circuit includes a first latch circuit and a second latch circuit. It is configured to latch the first output signal in either one of the first latch circuit or the second latch circuit according to the first output signal, the second output signal and the third output signal. It also allows the other one of the first latch circuit or the second latch circuit to input the first output signal thereto.

Abstract: A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed.

Abstract: In embodiments of the invention, a memory circuit includes a static random access memory (SRAM), rows of M sense amplifiers, a global read precharge tracking control circuit controlling a precharge of global read lines, a sense amplifier output tracking circuit generating a reset sense amplifier signal for the sense amplifier control circuits, and a read delay circuit generating a trigger signal for the global read precharge tracking control circuit and the sense amplifier output tracking circuit and performing a fixed delay tracking of a read operation in a read cycle. A dummy global read line is coupled to the global read precharge tracking control circuit and returns from a half way to the top of the SRAM forming a tracking dummy global read line that determines a completion of the precharge of the global read lines before the sense amplifiers start discharging the global read lines in the read cycle.

Abstract: Electronic apparatus, systems, and methods can include a delayer having an inverter chain, where each inverter of the chain can be operatively regulated using current generators to control variation of the delay time of the delayer. In various embodiments, current generators can be arranged to provide reference voltages to each inverter stage of an inverter chain. Additional apparatus, systems, and methods are disclosed.

Abstract: A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code value of the delay control code in sequential synchronization with a plurality of delayed clocks obtained by delaying the external clock as large as predetermined delay amounts, respectively, delay the shifted read command as large as the variable delay amount, and output the result of delay as an output enable flag signal.

Abstract: A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication delayed by both a delay locked loop and latency delays stored in latency control circuits. An upstream clock generation circuit generates a clock signal from the received command indication delayed by the delay locked loop and capture indications from the latency control circuits.

Abstract: A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information.

Abstract: Disclosed herein is a device that includes a command decoder and a latency counter. The command decoder generates a first internal command in response to a first internal clock signal. The latency counter includes: a gate control signal generation unit generating output gate signals in response to a second internal clock signal; delay circuits each receiving an associated one of the output gate signals and generating an associated one of input gate signals; and a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command in response to one of the output gate signals. Each of the delay circuit includes a first delay element that operates on a first power supply voltage and a second delay element that operates on a second power supply voltage different from the first power supply voltage.

Abstract: A method includes presenting multiple memory circuits to a system as a virtual memory circuit having at least one characteristic that is different from a corresponding characteristic of one of the physical memory circuits; receiving, at an interface circuit, a first command issued from the system to the virtual memory circuit; and in response to receiving the first command, 1) directing a copy of the first command to a first physical memory circuit of the multiple physical memory circuits, and 2) performing a power-saving operation on at least one other physical memory circuit of the multiple physical memory circuits.

Abstract: The invention provides a memory apparatus and a signal delay circuit thereof. The signal delay circuit provided by present disclosure includes an input inverter, a first inverter, a capacitor, a first transistor, a second inverter and output inverter. The input inverter receives an input signal and output a signal to the first inverter. The capacitor coupled to an output terminal of the first inverter. The second terminal of the first transistor coupled to the output terminal of the first inverter and the first terminal of the first transistor coupled to an operating voltage. An input terminal of the second inverter is coupled to the output terminal of the first inverter and an output terminal of the second inverter is coupled to the control terminal of the first transistor. The output inverter is used to generate a delayed output signal.

Abstract: A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.

Abstract: A semiconductor device may include an internal circuit configured to perform write operations in response to each of a plurality of write commands, wherein the plurality of write commands are sequentially input to the internal circuit, a first pulse generation unit configured to generate a first pulse activated during a first delay amount in response to a write command, a second pulse generation unit configured to generate a second pulse activated during the first delay amount in response to a delayed write command out of the plurality of write commands after a second delay amount from the activation time of the first pulse, and a transfer control unit configured to prevent commands other than the plurality of write commands from being transferred to the internal circuit during a sum of the activation period of the first pulse and the activation period of the second pulse.

Abstract: An operation control method of a semiconductor memory device includes executing a Delay Locked Loop (DLL) locking in response to a DLL reset signal and measuring a loop delay of a DLL. The operation control method further includes storing measured loop delay information and DLL locking information; and performing a delay control of a command path using the stored loop delay information and DLL locking information independent of the DLL, during a latency control operation.

Abstract: Clock circuits and apparatus containing such are useful in clock synchronization and skew adjustment. Such clock circuits may include a delay line coupled to receive an input signal, wherein the delay line comprises a plurality of delay elements, and wherein at least two delay elements of the plurality of delay elements differ in unit time delay. Such clock circuits may further include a phase detector coupled to receive the input signal and a signal generated from an output signal of the delay line. The phase detector may be configured to compare the input signal to the generated signal and to adjust a length of the delay line to synchronize the input signal and the generated signal.

Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

Abstract: A semiconductor device comprises: a control signal generating circuit that generates and outputs a control signal that is in an active state during a period around at least one of rising edges and falling edges of a clock signal; and a data input circuit that is controlled to be in an active state, in which a data signal can be received, while the control signal is in an active state, and otherwise controlled to be in an inactive state.

Abstract: Disclosed are a memory system and an associated operating method. In the system, a first memory array comprises first memory cells requiring a range of time delays between wordline activating and bitline sensing. A delay signal generator delays an input signal by a selected time delay (i.e., a long time delay corresponding to statistically slow memory cells) and outputs a delay signal for read operation timing to ensure read functionality for statistically slow and faster memory cells. To accomplish this, the delay signal generator comprises a second memory array having second memory cells with the same design as the first memory cells. Transistors within the second memory cells are controlled by a lower gate voltage than transistors within the first memory cells in order to mimic the effect of higher threshold voltages, which result in longer time delays and which can be associated with the statistically slow first memory cells.

Abstract: To provide a semiconductor device which can perform initialization to a first state of two states of the first state and a second state, and which can generate a signal having a potential corresponding to the initialized first state. The present invention is the semiconductor device which can perform initialization to “0” (a first state) of two states of “0” and “1” (a second state), and which can generate a signal having a potential corresponding to initialized “0”. The semiconductor device 10 includes a plurality of flip-flop circuits 2 that are connected in parallel and which can hold the two states of “0” and “1”; and an AND circuit 3 which generates and outputs a signal having a potential corresponding to “0” when a state held in at least one flip-flop circuit 2 among the flip-flop circuits 2 is “0”. The AND circuit is connected to the flip-flop circuits 2.

Abstract: A data storage apparatus includes: a memory configured to store data; an input delay circuit configured to input a set of data of a plurality of bits into the memory at different timings between the plurality of bits by adding different delays to the plurality of bits in the set of data or by adding different delays to bits in bit groups obtained by grouping the plurality of bits in units of a consecutive bits; and an output delay circuit configured to obtain an original set of data, which is the set of data before the input delay circuit adds the different delays, by adding, to the plurality of bits in the set of data output from the memory, delays having a pattern opposite that of the delays added by the input delay circuit.

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a first electrode, and a second semiconductor chip including a second electrode connected to the first electrode. One of the first and second semiconductor chips includes a first temperature sensor circuit generating a first detection signal, the first detection signal taking a first level when a temperature is equal to or higher than a first temperature, the first detection signal taking a second level when the temperature is lower than the first temperature; and a first delay code generation circuit outputting a first delay code signal in response to the first level of the first detection signal, and outputting a second delay code signal different from the first delay code signal in response to the second level of the first detection signal.

Abstract: A controller, includes a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data, at least one external terminal among the plurality of external terminals being configured to be capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.

Abstract: A delay circuit of the present disclosure includes a first delay unit and a second delay unit which are connected in series and delay an input signal to generate a delayed signal. The first delay unit includes a first signaling pathway, and changes, based on a first delay control value, a first amount of delay to be provided to the input signal by switching signaling pathways for transmitting the input signal that are within the first pathway. The second delay unit includes a second signaling pathway, and changes, based on a second delay control value, a second amount of delay to be provided to the input signal without switching the second signaling pathway for transmitting the input signal.

Abstract: A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a sequence of read commands so that a delayed version of a dqs signal toggles continuously. The method delays a core clock signal to sample the delayed dqs signal at different delay increments until a 1 to 0 transition is detected on the delayed dqs signal. This core clock delay is recorded as “A.” The method delays the core clock signal to sample the core clock signal at different delay increments until a 0 to 1 transition is detected on the core clock signal. This core clock delay is recorded as “B.” The optimum delay value is computed from the A and B delay values.

Abstract: A synchronous semiconductor memory device includes a first delay locked loop circuit and a second delay locked loop circuit. The first delay locked loop circuit has a first delay line and generates a first clock hat is delay-synchronized with a clock applied as a signal for a data output timing control. The second delay locked loop circuit has a second delay line and generates a second clock that is delay-synchronized with the clock. The first delay locked loop circuit consumes less power than the second delay locked loop circuit, and the second delay locked loop circuit has less jitter than the first delay locked loop circuit. The first and second delay locked loop circuits operate at different logic levels for a delay synchronization operation.

Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

Abstract: An operating method of a delay locked loop (DLL) circuit for a semiconductor memory device is disclosed. The DLL circuit may include a plurality of sub-circuits. The method may include calculating an additive latency value based on predetermined parameters, and controlling a set of the plurality of sub-circuits of the DLL circuit to be maintained in a turn-off state based on the calculated additive latency value, during a period of time after the semiconductor device receives an operation command in a power saving mode.

Abstract: A semiconductor device which can reduce the peak value of the rush current generated during a transition from resume mode to normal mode. The semiconductor device has a plurality of daisy-chained memory modules. Each of the memory modules includes a memory array, a switch for controlling, in resume mode, source voltage supply to a constituent element of the memory module, and a delay circuit which receives a resume control signal ordering a transition from resume mode to normal mode and outputs a resume control signal delayed from the inputted resume control signal to the memory module of the next stage.

Abstract: A latency control circuit includes a clock delay configured to output a plurality of serial delay signals obtained by serially delaying an input clock signal with the same intervals, a deviation information generating unit configured to generate a deviation information on the basis of a delay value, which the clock signal undergoes in a chip, and latency information, a clock selector configured to output a plurality of clock selection signals based on the plurality of serial delay signals and the deviation information, a command signal processing unit configured to generate a read signal based on an input command signal, and output a variable delay duplication signal by variably delaying the read signal, and a latency shifter configured to output a latency signal by combining the plurality of clock selection signals with the variable delay duplication signal.