Delay Patents (Class 365/194)
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Patent number: 9225561Abstract: A pipelined decision feedback equalizer (DFE) includes a programmable digital-to-analog converter (DAC) configured to provide a programmable voltage to a plurality of decision feedback equalized (DFE) sections, a capacitive element associated with each DFE section, the capacitive element coupled to an input connection by a first switch and coupled to an output connection by a second switch, clock logic configured to control the first switch and the second switch so that a predefined voltage signal is applied to the capacitive element at a predefined time such that a charge corresponding to the predefined voltage signal is applied to the capacitive element, the clock logic causing the second switch to couple the capacitive element to the output connection so as to apply the voltage on the capacitive element as a filter coefficient to a summing element.Type: GrantFiled: May 30, 2013Date of Patent: December 29, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Jade Michael Kizer, Robert B. Roze
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Patent number: 9209145Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.Type: GrantFiled: November 21, 2014Date of Patent: December 8, 2015Assignee: SK Hynix Inc.Inventors: Chang Kun Park, Seong Hwi Song, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang, Hae Rang Choi, Ji Wang Lee, Jae Min Jang
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Patent number: 9208902Abstract: An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.Type: GrantFiled: October 29, 2009Date of Patent: December 8, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Beena Pious, Xiaowei Deng, Wah Kit Loh, Jon Lescrenier
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Patent number: 9202596Abstract: A semiconductor device includes: a plurality of fuse arrays each including a plurality of fuses; a selection block which selects one fuse array among the fuse arrays in response to values of a group of bits of a repair code; a code alignment block which aligns disposition of bits other than the group of bits of the repair code, wherein the alignment disposition is changed based on the fuse array selected in the selection block; and an operation block which controls an operation of the fuse array selected in the selection block in response to a repair command and an output code of the code alignment block.Type: GrantFiled: November 26, 2014Date of Patent: December 1, 2015Assignee: SK Hynix Inc.Inventors: Seon-Ki Cho, Yong-Ho Kong
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Patent number: 9203606Abstract: A clock recovery circuit for recovering a clock signal from a clock-embedded data signal, a data receiving device for recovering a clock signal and a data signal from a clock-embedded data signal, and a data transmitting and receiving system for improving the protocol of a clock-embedded data signal. The data transmitting and receiving system includes a data transmitting device configured to transmit a clock-embedded data signal in which an embedded clock signal is embedded in a data signal; and a data receiving device configured to recover a clock signal corresponding to the embedded clock signal from the clock-embedded data signal.Type: GrantFiled: July 5, 2013Date of Patent: December 1, 2015Assignee: SILICON WORKS CO., LTD.Inventors: Yun Tack Han, Kwang Il Oh
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Patent number: 9197395Abstract: A system for forwarding a sample rate clock along with data. In one embodiment, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter.Type: GrantFiled: August 21, 2014Date of Patent: November 24, 2015Assignee: Samsung Display Co., Ltd.Inventors: Amir Amirkhany, Nasrin Jaffari
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Patent number: 9190123Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller is suitable for generating command signals and address signals. The semiconductor device is suitable for electrically disconnecting a first local line from a second local line in response to an input control signal enabled in a read mode. The read mode is set according to a logic combination of the command signals. Further, the semiconductor device is suitable for sensing and amplifying a data on the first local line or the second local line according to the address signals to output the amplified data through an input/output line.Type: GrantFiled: February 10, 2014Date of Patent: November 17, 2015Assignee: SK Hynix Inc.Inventor: Min Su Kim
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Patent number: 9183896Abstract: A deep sleep wakeup signal is received at a first memory bank. A first gated memory array supply voltage is increased in response to the receiving the deep sleep wakeup signal at the first memory bank. The first memory array supply voltage is applied to a first memory array. The deep sleep wakeup signal is forwarded to a second memory bank in response to determining the first gated memory array supply voltage has reached a specified voltage.Type: GrantFiled: June 30, 2014Date of Patent: November 10, 2015Assignee: International Business Machines CorporationInventors: Chad A. Adams, Thinh V. Luong, Jesse D. Smith
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Patent number: 9183125Abstract: A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed.Type: GrantFiled: December 19, 2011Date of Patent: November 10, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Kevin M. Brandl, Oswin E. Housty, Edoardo Prete, Gerald Talbot
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Patent number: 9177622Abstract: Electronic apparatus, systems, and methods can include a delayer having an inverter chain, where each inverter of the chain can be operatively regulated using current generators to control variation of the delay time of the delayer. In various embodiments, current generators can be arranged to provide reference voltages to each inverter stage of an inverter chain. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: October 27, 2014Date of Patent: November 3, 2015Assignee: Micron Technology, Inc.Inventor: Marco Sforzin
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Patent number: 9158330Abstract: Methods and apparatuses for processing systems capable of compensating for data skew are disclosed. An example apparatus can include delay circuitry that includes a plurality of delay devices each being individually adjustable to produce an individual delay for each data line with each data line including branches of different lengths leading to different memory devices, and memory control circuitry coupled to the delay circuitry and configured to determine, for each data line, an individual delay based on an optimized critical window, the optimized critical window being based on multiple chip select signals.Type: GrantFiled: November 15, 2012Date of Patent: October 13, 2015Assignee: Marvell Israel (M.I.S.L) LTD.Inventors: Eldad Bar-Lev, Aaron Landau
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Patent number: 9154313Abstract: A network relay apparatus includes: a clock generation circuit, a processing circuit, a load detector and a clock cutoff circuit. The clock generation circuit is configured to generate a clock signal having periodical clock pulses. The processing circuit is configured to operate in synchronism with the clock pulses, in order to process data that is to be relayed by the network relay apparatus. The load detector is configured to detect a load of processing by the processing circuit. The clock cutoff circuit is configured to cut off supply of the clock pulses from the clock generation circuit to the processing circuit in order to partially eliminate the clock pulses at a rate corresponding to the load detected by the load detector and to provide the clock signal having the partially eliminated clock pulses to the processing circuit.Type: GrantFiled: December 19, 2012Date of Patent: October 6, 2015Assignee: Alaxala Networks CorporationInventor: Tomohiko Kono
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Patent number: 9148136Abstract: A semiconductor apparatus includes a duty cycle correction block and a delay locked loop. The duty cycle correction block generates a duty corrected clock by correcting a duty cycle of an internal clock, adjusts a phase of a rising edge of the duty corrected clock when a delay locked loop is reset, and adjusts a phase of a falling edge of the duty corrected clock when the delay locked loop is locked. The delay locked loop receives an external clock to output the internal clock, and delays the external clock by a variable delay amount to output the internal clock when the adjustment of the phase of the rising edge of the duty corrected clock by the duty cycle correction block is completed.Type: GrantFiled: March 18, 2013Date of Patent: September 29, 2015Assignee: SK Hynix Inc.Inventor: Young Suk Seo
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Patent number: 9135206Abstract: An integrated circuit device transmits to a dynamic random access memory (DRAM) one or more commands that specify programming of a digital control value within the DRAM, the digital control value indicating a termination impedance that the DRAM is to couple to a data interface of the DRAM in response to receiving a write command and during reception of write data corresponding to the write command, and that the DRAM is to decouple from the data interface after reception of the write data corresponding to the write command. Thereafter, the integrated circuit device transmits to the DRAM a write command indicating that write data is to be sampled by a data interface of the DRAM during a first time interval and that cause the DRAM to couple the termination impedance to the data interface during the first time interval and decouple the termination impedance from the data interface after the first time interval.Type: GrantFiled: December 4, 2014Date of Patent: September 15, 2015Assignee: Rambus Inc.Inventors: Kyung Suk Oh, Ian P. Shaeffer
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Patent number: 9104635Abstract: According to some embodiments, a method and apparatus are provided to determine a worst-case setup and hold bit pattern stream associated with a load on a bus, and determine a time shift to apply to an incoming bit pattern being conveyed relative to a DLL associated with the load.Type: GrantFiled: December 28, 2011Date of Patent: August 11, 2015Assignee: Intel CorporationInventors: Oseghale O. Uduebho, Adam J. Norman
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Patent number: 9105326Abstract: A method of writing a memory cell includes, during a write cycle, causing a voltage level at a power terminal of the memory cell to change from a supply voltage level toward a first voltage level. The voltage level at the power terminal of the memory cell is maintained at the first voltage level for a first predetermined duration. The voltage level at the power terminal of the memory cell is maintained at a second voltage level for a second predetermined duration, where the second voltage level is between the first voltage level and the supply voltage level. During the write cycle, the voltage level at the power terminal of the memory cell is caused to change from the first voltage level toward the supply voltage level.Type: GrantFiled: May 30, 2014Date of Patent: August 11, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Huei Chen, Li-Wen Wang, Chih-Yu Lin
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Patent number: 9105315Abstract: A semiconductor memory storage device for storing data including: a plurality of storage cells, each storage cell including an access control device configured to provide the storage cell with access to or isolation from a data access port in response to an access control signal. Access control circuitry includes: access switching circuitry configured to connect a selected access control line to a voltage source; and feedback circuitry configured to feedback a change in voltage on the access control line to the access switching circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line in response to the feedback circuitry providing a feedback signal indicating that the access control line voltage has attained a predetermined value.Type: GrantFiled: July 23, 2012Date of Patent: August 11, 2015Assignee: ARM LimitedInventors: Betina Hold, Kenza Charafeddine, Yves Thomas Laplanche
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Patent number: 9094183Abstract: A receiving circuit includes a clock input portion configured to buffer a first pattern signal and configured to retard the buffered first pattern signal by a first delay time to generate an input clock signal, a data input portion configured to buffer a second pattern signal and configured to retard the buffered second pattern signal by a second delay time to generate an input data signal, and a comparator configured to compare a phase of the input clock signal with a phase of the input data signal to generate a comparison signal for adjusting the second delay time.Type: GrantFiled: December 18, 2012Date of Patent: July 28, 2015Assignee: SK hynix Inc.Inventor: Sang Yeon Byeon
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Patent number: 9082506Abstract: An operating method of a delay locked loop (DLL) circuit for a semiconductor memory device is disclosed. The DLL circuit may include a plurality of sub-circuits. The method may include calculating an additive latency value based on predetermined parameters, and controlling a set of the plurality of sub-circuits of the DLL circuit to be maintained in a turn-off state based on the calculated additive latency value, during a period of time after the semiconductor device receives an operation command in a power saving mode.Type: GrantFiled: March 11, 2014Date of Patent: July 14, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Tae-Sik Na
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Patent number: 9082504Abstract: A semiconductor memory device which stores refresh period information thereby adjusting a refresh period and a method of operating the same. The semiconductor memory device includes a cell array and a refresh information storing unit. The cell array includes one or more cell regions each having a plurality of memory cells. The refresh information storing unit is configured to store first information including a first refresh period and second information including a second refresh period in correspondence to each of the cell regions. Memory cells included in each of the cell regions are refreshed at the first refresh period according to the first information in a first refresh time band and are refreshed at the second refresh period according to the second information in a second refresh time band.Type: GrantFiled: July 5, 2013Date of Patent: July 14, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Sik Kim, Jung-Bae Lee
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Patent number: 9065453Abstract: A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.Type: GrantFiled: November 25, 2013Date of Patent: June 23, 2015Assignee: Silicon Image, Inc.Inventors: Farshid Aryanfar, Hae-Chang Lee, Kun-Yung Chang, Ting Wu, Carl Werner, Masoud Koochakzadeh
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Patent number: 9064556Abstract: A pseudo dual port (PDP) memory is disclosed having a write driver that selectively precharges only one of a bit line and a complement bit line in a bit line pair responsive to a bit value to be written into an accessed bitcell while discharging a remaining one of the bit line and the complement bit line. In this fashion, the cleanup time between a read operation and a write operation during a read/write clock cycle is advantageously reduced.Type: GrantFiled: October 23, 2013Date of Patent: June 23, 2015Assignee: QUALCOMM IncorporatedInventors: Chirag Gulati, Lakshmikantha Holla Vakwadi, Sei Seung Yoon
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Patent number: 9060024Abstract: Normalizing security event data from multiple different network agents. The data from the multiple different agents is categorized and tagged with a descriptor that includes information about the nature of the event. Multiple different events from multiple different devices can therefore be evaluated using a common format which is common for the multiple different devices from different vendors.Type: GrantFiled: April 6, 2009Date of Patent: June 16, 2015Assignee: Log Storm Security, Inc.Inventor: Rajesh Patel
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Patent number: 9058898Abstract: The present invention discloses an efficient way to read data from a memory device by aligning an internal clock of the memory interface circuit with the read data strobe signal from the memory device by delaying the internal clock along with control signals for reading the memory device before transmitting them to the memory device, wherein the internal clock of the memory controller can sample the read data from the memory device directly without using a FIFO device between the internal clock and the read data strobe so as to reduce latency of reading data from the memory device. For example, the memory device can be a double-data-rate (DDR) DRAM device, and the control signals includes command and address signals of the DDR DRAM device.Type: GrantFiled: April 21, 2014Date of Patent: June 16, 2015Assignees: Global Unichip Corp., Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Ming-Jing Ho, Shih-Lun Chen, Yu-Ming Sun
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Publication number: 20150146492Abstract: The semiconductor device includes an input clock generator and a data input unit. The input clock generator generates an input clock signal including a first pulse and a second pulse, wherein the first pulse is generated in response to a write signal and a write latency signal and the second pulse is generated in response to an external command signal and a burst length signal. The data input unit receives data and generates first input data in response to the first pulse of the input clock signal and receives the data and generates second input data in response of the second pulse of the input clock signal.Type: ApplicationFiled: April 11, 2014Publication date: May 28, 2015Applicant: SK hynix Inc.Inventor: Yong Suk JOO
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Patent number: 9042190Abstract: Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit.Type: GrantFiled: February 25, 2013Date of Patent: May 26, 2015Assignee: MICRON TECHNOLOGY, INC.Inventors: Daniele Vimercati, Riccardo Muzzetto
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Patent number: 9042189Abstract: A semiconductor memory device includes: a burst start signal generation unit configured to generate a first burst start signal by delaying a write pulse by a first period, generate a second burst start signal by delaying the write pulse by a second period, and selectively transmit the first or second burst start signal as a select burst start signal in response to a test signal; an input control signal generation unit configured to generate an input control signal in response to the first burst start signal; and a write command generation unit configured to generate a write driver enable signal in response to the select burst start signal.Type: GrantFiled: January 24, 2012Date of Patent: May 26, 2015Assignee: SK Hynix Inc.Inventor: Yin Jae Lee
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Patent number: 9042188Abstract: A memory controller transmits a data signal, a data strobe signal and a mask signal to a memory, wherein each transition of the data strobe signal indicates a sample point for the data signal and the mask signal indicates a validity of the data signal. A mask signal training procedure is carried out comprising three steps. Writing first and second values to the memory for a predetermined plurality of transitions of the data strobe signal with the mask signal set to indicate that the first data signal is valid and the second data signal is valid except for a selected transition of the predetermined plurality. Reading from the memory for the predetermined plurality of transitions of the data strobe signal. Determining a timing offset for the mask signal for which the value read at the selected transition matches the first value.Type: GrantFiled: April 1, 2013Date of Patent: May 26, 2015Assignee: ARM LimitedInventors: Gyan Prakash, Nidhir Kumar
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Patent number: 9036436Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., 1/2, 1/4 or 1/8 of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.Type: GrantFiled: May 3, 2012Date of Patent: May 19, 2015Assignee: Rambus Inc.Inventors: Akash Bansal, Yohan U. Frans, Kishore V. Kasamsetty, Todd Bystrom, Simon Li, Arun Vaidyanath
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Patent number: 9036434Abstract: A method of adjusting read timing of a random access memory. The method includes providing a Column Address Strobe (CAS) value for defining an CAS latency (CL) of the random access memory; generating a shift margin according to the CAS latency and a reference latency; generating a read command for accessing the random access memory; dynamically generating a Column Select (CS) signal and adjusting output timing of the CS signal according to the shift margin, after the read command is generated.Type: GrantFiled: October 31, 2013Date of Patent: May 19, 2015Assignee: Nanya Technology CorporationInventor: Shun-Ker Wu
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Patent number: 9036435Abstract: The semiconductor apparatus includes a reference delay value check unit configured to receive a source signal and delay the source signal to generate a reference delay signal; a process delay value check unit configured to receive the source signal and delay the source signal to generate a process delay signal; and a signal generation unit configured to receive the reference delay signal and the process delay signal, receive an input signal, and variably delay the input signal based on the reference delay signal and the process delay signal to generate an output signal.Type: GrantFiled: August 1, 2013Date of Patent: May 19, 2015Assignee: SK Hynix Inc.Inventors: Heat Bit Park, Kee Teok Park
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Publication number: 20150131392Abstract: A semiconductor integrated circuit includes a memory having bit cells; and a frequency detector outputting a switching signal to switch a test mode from first to second test modes. Further, the memory includes an internal clock generator generating an internal clock in synchronization with the external clock; a writing part writing data into the bit cells based on the internal clock; a delayed clock generator generating a delayed clock by adding a designated delay to the internal clock; a first selector inputting the internal clock and the delayed clock, and, when the frequency of the high-speed clock is less than a designated frequency, selecting the delayed clock based on the switching signal; and a reading part reading the data of the bit cells based on the delayed clock.Type: ApplicationFiled: November 10, 2014Publication date: May 14, 2015Inventor: KATSUAKI AIZAWA
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Patent number: 9030896Abstract: A control circuit for a bit-line sense amplifier may include: a bank active signal generator configured to generate an internal active signal and a bank active signal; and a sense amplifier enable signal generator configured to determine a skew in response to the internal active signal, and set an output time of a sense amplifier enable signal by delaying the bank active signal according to the determined skew.Type: GrantFiled: February 6, 2014Date of Patent: May 12, 2015Assignee: SK Hynix Inc.Inventor: Byeong Cheol Lee
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Patent number: 9030892Abstract: There is disclosed a data reading device in which data of a nonvolatile storage element is reflected in a circuit to be regulated, with a minimum necessary delay width after turning a power on or after reset cancellation, and wrong writing due to a static electricity is prevented. A delay circuit is additionally disposed to output a delayed data reading signal after a signal of turning the power on or a signal of the reset cancellation is generated. A delay time T2 and a static electricity convergence time T1 are set so as to keep a relation of T1<T2.Type: GrantFiled: October 30, 2012Date of Patent: May 12, 2015Assignee: Seiko Instruments Inc.Inventors: Kotaro Watanabe, Makoto Mitani
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Patent number: 9030242Abstract: A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code value of the delay control code in sequential synchronization with a plurality of delayed clocks obtained by delaying the external clock as large as predetermined delay amounts, respectively, delay the shifted read command as large as the variable delay amount, and output the result of delay as an output enable flag signal.Type: GrantFiled: September 24, 2014Date of Patent: May 12, 2015Assignee: SK Hynix Inc.Inventor: Kyung Hoon Kim
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Publication number: 20150124540Abstract: A system including a circuit integrated with a semiconductor is provided. The system includes a first data line, a second data line, and a first sense amp configured to sense and amplify data of the first data line. The first sense amp is also configured to transfer the amplified data to the second data line in response to a third control signal. The system also includes a control signal generation circuit configured to generate a first control signal for controlling a precharge of the first data line and a second control signal for controlling a reset of the second data line in response to a preparatory signal and a third control signal. The third control signal is generated in response to the first control signal and the second control signal.Type: ApplicationFiled: January 27, 2014Publication date: May 7, 2015Applicant: SK hynix Inc.Inventor: Hyun Gyu LEE
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Patent number: 9025410Abstract: A semiconductor memory device may be effectively evaluated by a test that compares the phase of an internally generated control signal with the phase of an internally generated clock signal. Specifically, if the phase of the internal data strobe signal IDQS is synchronized with the phase of the internal clock signal ICLK through the test, the data strobe signal DQS may also be synchronized with the external clock signal CLK. Thus, the test may prevent certain critical parameters, for example, AC parameter tDQSCK, from being out of an allowable range over PVT (process, voltage, and temperature variation). The test helps ensure that the semiconductor memory device will operate properly in read mode.Type: GrantFiled: March 18, 2013Date of Patent: May 5, 2015Assignee: SK Hynix Inc.Inventor: Shin Ho Chu
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Patent number: 9025402Abstract: A semiconductor memory apparatus may include a memory bank, row decoders, and an intersection region circuit. The row decoder may be configured to select a dummy block and a plurality of sub blocks based on row address signals, a bank select signal, and a dummy delayed bank select signal. The intersection region circuit may delay the bank select signal and may generate a delayed bank select signal and a dummy delayed bank select signal.Type: GrantFiled: March 18, 2014Date of Patent: May 5, 2015Assignee: SK Hynix Inc.Inventor: Doo Chan Lee
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Patent number: 9025400Abstract: A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A data bus is shared by the memory units and transfers data from the memory units or to the memory units. A timing controller includes a delay time unit shared by the memory units sharing the data bus. The timing controller is configured to output a control signal for driving the memory units after a predetermined delay time elapses since receiving an input signal.Type: GrantFiled: August 31, 2012Date of Patent: May 5, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Fujita, Katsuhiko Hoya
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Patent number: 9026833Abstract: In order to reduce occurrence of a fetching error of a digital signal, caused by a power-source noise, there is provided a semiconductor device provided with a switching circuit for executing a switching operation according to a pulse control signal and a digital signal hold circuit for fetching a digital signal. The digital signal hold circuit includes a mask signal generation circuit for generating a mask signal from the pulse control signal, the mask signal being for use in keeping the digital signal from being fetched during a time period of power-source noise occurrence caused by the switching operation, and the digital signal is not fetched during the time period of power-source noise occurrence while the digital signal is fetched during a time period of power-source noise nonoccurrence.Type: GrantFiled: February 29, 2012Date of Patent: May 5, 2015Assignee: Renesas Electronics CorporationInventor: Yuki Higuchi
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Patent number: 9025401Abstract: A semiconductor memory device includes a bulk voltage generation circuit configured to interrupt driving of a bulk voltage in response to an exit signal which is generated in synchronization with a time at which a power-down mode is ended, and discharge charges of a first node from which the bulk voltage is outputted, in response to the exit signal; and an internal circuit including a MOS transistor which is supplied with the bulk voltage.Type: GrantFiled: August 9, 2013Date of Patent: May 5, 2015Assignee: SK Hynix Inc.Inventor: Mi Hyun Hwang
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Patent number: 9021293Abstract: A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.Type: GrantFiled: November 15, 2013Date of Patent: April 28, 2015Assignee: Uniquify, IncorporatedInventors: Jung Lee, Mahesh Goplan
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Publication number: 20150109866Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.Type: ApplicationFiled: December 22, 2014Publication date: April 23, 2015Inventor: ERIC LEE
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Patent number: 9013935Abstract: Data input circuits are provided. The data input circuit includes a drive clock signal generator, a data transmitter and a write driver. The drive clock signal generator is configured to shift and delay a final clock signal generated in response to a pulse of a sampled clock signal and configured to generate a drive clock signal in response to the delayed final clock signal. The data transmitter is configured to output input data signals as write input data signals in response to the drive clock signal. The write driver is configured to receive the write input data signals in response to the drive clock signal to drive signals on global lines.Type: GrantFiled: March 18, 2013Date of Patent: April 21, 2015Assignee: SK Hynix Inc.Inventor: Min Chang Kim
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Patent number: 9013949Abstract: The present disclosure relates to a method and system for controlling memory access. In particular, a method for controlling memory access includes, in response to receiving a write request operative to write data to at least one memory cell of a plurality of memory cells, increasing a word line voltage above a nominal level after a predetermined delay following the receipt of the write request. A disclosed system includes a word line driver operative to increase a word line voltage above a nominal level during a write access after a predetermined delay in response to a write request.Type: GrantFiled: December 19, 2011Date of Patent: April 21, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Russell Schreiber, Vikram Suresh
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Publication number: 20150103584Abstract: A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay stage, the first delay stage and the second delay stage each having an input port electrically coupled to a signal source, and (2) a delay path select circuit electrically coupled between the first delay stage and the second delay stage, and operable to select between a delay path including the first delay stage and another delay path including the first delay stage and the second delay stage.Type: ApplicationFiled: October 15, 2013Publication date: April 16, 2015Applicant: Nvidia CorporationInventors: Hwong-Kwo Lin, Lei Wang, Spencer Gold, Zhenye Jiang
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Publication number: 20150103608Abstract: A device including input and output nodes, first and second input circuits coupled in parallel to each other between the input and output nodes. The first input circuit includes a first circuit unit coupled between the input and output nodes, the first circuit unit is configured to be activated when a first selection signal supplied thereto takes an active level and deactivated when the first selection signal takes an inactive level. The first circuit unit is configured to respond to a change of a control signal, which is received from a control circuit, from a first logic level to a second logic level and the first circuit unit is configured to change the first selection signal from the active level to the inactive level after a lapse of a first period.Type: ApplicationFiled: December 18, 2014Publication date: April 16, 2015Inventors: Kazutaka Miyano, Hiroyuki Inage
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Patent number: 9007855Abstract: A method of calibrating a data signal receiver configured to receive a multi-bit data signal and an associated data strobe signal, wherein transitions of the data strobe signal indicate sample points for the multi-bit data signal.Type: GrantFiled: December 24, 2012Date of Patent: April 14, 2015Assignee: ARM LimitedInventors: Nidhir Kumar, Gyan Prakash, Muniswara Reddy Vorugu
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Patent number: 9007852Abstract: A semiconductor integrated circuit includes: a latch unit configured to latch data in response to an input control signal; and a latch control unit configured to determine whether or not any one of first and second memory areas is successively accessed, and adjust timing of the input control signal.Type: GrantFiled: September 5, 2013Date of Patent: April 14, 2015Assignee: SK Hynix Inc.Inventor: Jae Il Kim
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Patent number: 9007849Abstract: A buffer control circuit of a semiconductor memory apparatus includes a delay unit configured to determine delay amounts for a command in response to a plurality of command latency signals, delay the command according to a clock, and generate a plurality of delayed signals; and a buffer control signal generation unit configured to receive the plurality of command latency signals and the plurality of delayed signals, and generate a buffer control signal.Type: GrantFiled: December 7, 2012Date of Patent: April 14, 2015Assignee: SK Hynix Inc.Inventor: Choung Ki Song