Abstract: A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.

Abstract: A circuit and method for implementing an adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.

Abstract: The present invention classifies all critical paths into two basic types: a series critical path and a feedback critical path, and divides each of wave-pipelined circuits into two components: a static logic part, called critical path component (CPC), and a dynamic logic part, formalized into four wave-pipelining components (WPC) shared by all wave-pipelined circuits. Each wave-pipelining ready code in HDL comprises two components: a WPC instantiation and a CPC instantiation wire-connected and linked by a new link statement. Each WPC has new wave constants which play the same role as generic constants do, but whose initial values are determined and assigned by a synthesizer after code analysis, so designers can use after-synthesization information in their code before synthesization for wave-pipelining technology.

Abstract: A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.

Abstract: A detection device includes a drive circuit of a physical quantity transducer, a synchronization signal output circuit, and a detection circuit that performs detection of a physical quantity signal based on a physical quantity. The synchronization signal output circuit includes a delay locked loop (DLL) circuit that includes: a delay control circuit that outputs a delay control signal and a delay circuit that includes a plurality of delay units in which a delay time is controlled by the delay control signal; an adjustment circuit that includes at least one delay unit in which a delay time is controlled by the delay control signal, and outputs a signal obtained by delaying an input signal based on the output signal from the drive circuit to the DLL circuit; and an output circuit that outputs the synchronization signal based on multi-phase clock signals from the DLL circuit.

Abstract: Methods of operating integrated circuit devices include logically combining an output signal indicating whether an operation is being performed with the logic level of a command signal line to generate a command signal to control circuitry of the integrated circuit device having the logic level of the command signal line when the output signal indicates that the operation is not being performed, and having a particular logic level when the output signal indicates that the operation is being performed. Integrated circuit devices include a command signal management circuit to provide a logic level of a particular command signal to control circuitry of the integrated circuit device when control signals indicate a desire to allow the particular command signal, and to provide a particular logic level to the control circuitry when the control signals indicate a desire to block the particular command signal.

Abstract: A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively.

Abstract: A display device includes a display portion, a hold capacitor, a write transistor writing a drive voltage corresponding to a video signal to the hold capacitor, a drive transistor driving the display portion in accordance with the drive voltage written to the hold capacitor, and a pulse width adjusting portion adjusting a width of a pulse signal causing a drive pulse used to drive at least one of the write transistor and the drive transistor so as to correspond to an environmental change.

Abstract: Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes sequentially programming a plurality of delay trim settings into a delay circuit of a data path. The data path can include a data latch coupled to the delay circuit. A clock is coupled to the data latch to clock data into the data latch. Transitions of the data are substantially aligned with transitions of the clock. An output of the data latch is read after each delay trim setting is programmed. A boundary is determined between a first output state of the data latch and a second output state of the data latch wherein the boundary is associated with a particular delay trim setting of the plurality of delay trim settings. The particular delay trim setting is programmed into the delay circuit.

Abstract: Various implementations described herein are directed to an integrated circuit for implementing low power input gating. In one implementation, the integrated circuit may include a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal. The integrated circuit may include a latch device configured to latch the control input of the memory. The integrated circuit may include a latch enable device coupled between the chip enable device and the latch device. The latch enable device may be configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory.

Abstract: A transient voltage collapse circuit provides a reference voltage for an SRAM (static random access memory). The SRAM receives a first reference voltage and a second reference voltage higher than the first reference voltage. The transient voltage collapse circuit provides the first reference voltage to the SRAM via a voltage supply line. The transient voltage collapse circuit maintains the voltage supply line at a first voltage level during a power save mode of the SRAM. The transient voltage collapse circuit increases the voltage of the voltage supply line during a write operation of the SRAM. The increase in the voltage of the supply line reduces the gap between first reference voltage and the second reference voltage, thereby assisting with the write operation of the SRAM.

Abstract: Apparatuses and methods are described for meeting timing and latency requirements using staggered clocking within the command path.

Abstract: A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin.

Abstract: A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.

Abstract: A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to a plurality of word lines and the plurality of bit lines, and an input/output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and to output the temporarily stored data to an external device. The nonvolatile memory device further includes control logic configured to set a status of the nonvolatile memory device to a ready state after the sensing data is dumped to the input/output buffer and before recovery of the cell array from a bias voltage of the sensing operation is complete.

Abstract: A driving apparatus includes a control circuit configured to generate a voltage region control signal enabled for a predetermined time according to a command signal; and a driving circuit configured to provide an internal voltage by selecting a dead zone of the internal voltage according to the voltage region control signal.

Abstract: A semiconductor device includes a control signal generating unit, a first address generating unit, and a second address generating unit. The control signal generating unit generates a read/write control signal and a selection control signal in response to an active signal. The first address generating unit generates a first address signal in response to the selection control signal and a second address signal. The second address generating unit generates the second address signal in response to the read/write control signal and the first address signal.

Abstract: A method for controlling a memory includes causing a data de-skewer to operate in a writing mode, at the data de-skewer, receiving a first signal, and skewing the first data signal by a first compensation skew, causing the data de-skewer to operate in a reading mode, at the data de-skewer, receiving a second signal, and skewing the second signal by a second compensation skew, wherein the first signal is representative of a bit from a byte that is to be written to the memory, and wherein the second signal is representative of a bit from a byte that has been read from the memory.

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Abstract: A Programmable Resistive Device (PRD) memory that can be read under low voltage is disclosed. The PRD includes at least one Programmable Resistive Element (PRE) having one end coupled to a first supply voltage line and the other end coupled to at least one selector and at least one read selector. The read selector includes at least one read source line (SLR) and/or one read enable (ENR) coupled to a second and/or a third supply voltage lines, respectively. The read selector includes at least one MOS device built by core logic device. The PRE in the at least one PRD cells can be configured to be readable by applying voltages to the first, second, and/or the third voltage supply lines to thereby sense the PRE resistance to a logic state. The programmable resistive element can have at least one element in an OTP, MTP, floating gate device, anti-fuse, or emerging memory such as PCRAM, RRAM, or MRAM, etc.

Abstract: A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.

Abstract: A clock generator is provided that is immune to skew between bits in digital words generated by a multi-phase receiver.

Abstract: A method and apparatuses for generating a reference voltage are disclosed. One example apparatus includes a current source coupled to a first power supply. The current source supplies a first current. A reference memory cell is coupled to the current source at a reference node. The reference memory cell has a select device comprising a chalcogenic semiconductor material. A clamp circuit is coupled between the reference memory cell and a second power supply. The clamp circuit is configured to control a second current such that when the first current and second current are substantially equal, the reference voltage generated at the reference node tracks a threshold voltage of the select device.

Abstract: A semiconductor apparatus includes a control block configured to control a pulse width of a column select signal in response to a precharge command from an external; and a coupling block configured to electrically couple bit lines and data lines according to the column select signal. A semiconductor apparatus includes a control block configured to generate a drive signal in response to a write command and generate an overdrive signal in response to a precharge command; and a driver configured to drive data lines with a first voltage in response to the drive signal and overdrive the data lines with a second voltage higher than the first voltage in response to the overdrive signal.

Abstract: Methods and apparatus for the selection and/or configuration of scrambling operations to accommodate e.g., both scrambling and non-scrambling connections (such as to e.g., legacy type devices). In one embodiment, media interface devices (such as e.g., HDMI (High-Definition Multimedia Interface)) devices may provide enhanced scrambling capabilities; solutions disclosed herein provide, among other things, support for both enhanced scrambling capable devices and legacy devices, and enable a device to determine the scrambling capabilities of a connected device.

Abstract: A semiconductor memory apparatus may include: a command decoder configured to decode an external command and output the decoded command as an internal command; a command transmitter configured to determine a delay time in response to a voltage level of an external voltage being applied to the semiconductor memory apparatus, delay the internal command by the determined delay time, and output the delayed internal command as a delayed command; and a data storage area configured to receive the delayed command, and perform an operation according to the delayed command.

Abstract: According to one embodiment, a storage device includes a storage medium, a DLL circuit, a latch circuit, and a delay amount adjustment circuit. The DLL circuit gives a predetermined amount of delay to an inputted clock signal, the latch circuit latches data outputted from the storage medium in accordance with the clock signal delayed in the DLL circuit, the delay amount adjustment circuit adjusts the delay amount that the DLL circuit is to give to the clock signal based on a latch result by the latch circuit.

Abstract: A memory device may include a plurality of word lines each word line being operably coupled to one or more memory cells; a peripheral circuit suitable for performing first and second refresh operations to the plurality of word lines; wherein the first refresh operation is suitable for preserving stored data for a majority of the memory cells of the memory device and the second refresh operation is suitable for preserving stored data of one or more weak memory cells.

Abstract: Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active clock signal to a command path for a first portion of a command cycle for a command of back-to-back commands. The command path decodes the command and provides an output command signal responsive to the clock signal. The method further includes providing an inactive clock signal to the command path for a second portion of the command cycle for the command of the back-to-back commands.

Abstract: An audio signal encoding apparatus includes a processor to quantize an audio signal, to obtain a characteristic of reverberation masking that is exerted on a sound represented by the audio signal by reverberation of the sound generated in a reproduction environment by reproducing the sound, and to control a quantization step size of the audio signal that quantized based on the characteristic of the reverberation masking.

Abstract: A voltage converter includes a power supply circuit configured to generate an output voltage based on an input voltage in response to a control signal, and a power supply control circuit configured to generate the control signal based on a reference clock signal and the output voltage.

Abstract: A main body ECU as a slave node includes a switch. The switch is under OFF state when a prohibition signal is outputted from a verification ECU as a master node and under ON state when the prohibition signal is not outputted. The switch is inserted in a reception path between a receive port of a microcomputer of the main body ECU and a receiver of a transceiver that is connected with a communication bus. When the switch is under OFF state, a reception signal outputted by the transceiver is not inputted into the microcomputer of the main body ECU. Therefore, the microcomputer is not activated even if an activation frame is transmitted to the communication bus; this enables the main body ECU to maintain a sleep mode.

Abstract: An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

Abstract: A data strobing circuit may include: an operating speed detection unit configured to detect an operating speed of a semiconductor apparatus according to a clock signal, and generate a control signal with a different value depending on the detected operating speed; and a strobe signal generation unit configured to adjust a delay time and pulse width of a read pulse according to the control signal and output an adjusted signal as a strobe signal.

Abstract: A semiconductor memory device includes: a burst start signal generation unit configured to generate a first burst start signal by delaying a write pulse by a first period, generate a second burst start signal by delaying the write pulse by a second period, and selectively transmit the first or second burst start signal as a select burst start signal in response to a test signal; an input control signal generation unit configured to generate an input control signal in response to the first burst start signal; and a write command generation unit configured to generate a write driver enable signal in response to the select burst start signal.

Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

Abstract: A memory device including a first cell block including a plurality of word lines and first to Kth (K is a natural number) redundancy word lines, a second cell block including a plurality of word lines and (K+1)th to Nth (N is a natural number greater than K) redundancy word lines, and a control unit suitable for performing control so that the first to Nth redundancy word lines replace the word lines of the first or second cell block, refreshing the word lines of the first and the second cell blocks simultaneously in a first section, and sequentially refreshing the first to Nth redundancy word lines in a second section.

Abstract: A signal control circuit includes: a delay acquisition circuit configured to obtain a first delay amount to be added to an input signal for aligning timing of rise of the input signal with timing of fall or rise of a reference signal and a second delay amount to be added to the input signal for aligning timing of fall of the input signal with timing of the fall or the rise of the reference signal; and a ratio calculation circuit configured to calculate a duty ratio of the input signal based on a difference between the first delay amount and the second delay amount.

Abstract: A semiconductor apparatus may include a read path configured to transmit data from the semiconductor apparatus in response to a read command and at least one read operation control signal, and an operation control circuit configured to receive a plurality of divided clock signals and the read command to identify the one of the plurality of divided clock signals that is relatively better matched to the received read command to manage timings associated with at least one of the read operation control signals.

Abstract: In an example, the present invention provides a computing system. The system has a memory interface device comprising a counter, a dynamic random access memory device coupled to the memory interface device. The device comprises a plurality of banks, each of the banks having a subarray, each subarray having a plurality of memory cells. The device has a data interface coupled to the plurality of banks. The device has an address interface coupled to the plurality of banks, and a particular pre-charge command configured to be transferred to the memory interface device. The counter is adapted to count a measured time duration from a first time when data are available at the data interface to a second time when a pre-charge command is received by the address interface.

Abstract: A differential memory device includes of memory locations having a direct memory cell and a complementary memory cell. A corresponding method includes receiving a request of reading a selected data word associated with a selected code word, reading a differential code word representing a differential version of the selected code word, verifying the differential code word according to an error correction code, setting the selected data word according to the differential code word in response to a positive verification. The method further includes reading at least one single-ended code word representing a single-ended version of the selected code word, verifying the single-ended code word according to the error correction code, and setting the selected data word according to the single-ended code word in response to a negative verification of the differential code word and to a positive verification of the single-ended code word.

Abstract: A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.

Abstract: A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.

Abstract: A method and apparatus for reducing a number of delay elements used in providing a delayed data strobe signal is disclosed. The method includes determining a number of delay elements of a master delay locked loop (DLL) needed to provide a calibrated delay of a clock signal (i.e. the data strobe). The method also include determining an integer number of half clock periods within the calibrated delay, and determining a second number of delay elements within the calibrated delay. If the integer number of half clock periods within the calibrated delay is zero, a slave DLL may be programmed with the first number of delay elements. However, if the number of half clock periods is non-zero, then a third number of delay elements is calculated by subtracting the second number of delay elements from the first number. Thereafter, the slave DLL is programmed with the third number of delay elements.

Abstract: A delay and calibration circuit for an input/output determines an appropriate delay by trying a range of different delays, and for each delay, determining the number of times that a given data sequence is accurately received. The data sequence may be a command, address, host data, or other data. Appropriate delays may be found for different temperatures.

Abstract: A semiconductor device includes a normal test signal generator and a termination signal generator. The normal test signal generator is suitable for generating a first enablement signal and a first pulse signal in response to an external command signal when a first code signal and a second code signal have a predetermined logic combination. Further, the normal test signal generator is suitable for decoding a first test address signal and a second test address signal to generate first to fourth normal test signals. The termination signal generator is suitable for receiving the first pulse signal during an enablement period of the first enablement signal to generate a first termination signal which is enabled when a predetermined signal among the first to fourth normal test signals is generated.

Abstract: A memory device, a memory system, and operating methods thereof are provided. The method of operating the memory device, which includes a first memory cell and a second memory cell neighboring the first memory cell, includes counting a disturbance value of the second memory cell each time the first memory cell is accessed, updating a disturbance count value of the second memory cell based on the counting, adjusting a refresh schedule based on the disturbance count value of the second memory cell, a desired threshold and a maximum disturbance count value, and resetting the disturbance count value of the second memory cell and the maximum disturbance count value when the second memory cell is refreshed according to the adjusted refresh schedule.

Abstract: A deep sleep wakeup signal is received at a first memory bank. A first gated memory array supply voltage is increased in response to the receiving the deep sleep wakeup signal at the first memory bank. The first memory array supply voltage is applied to a first memory array. The deep sleep wakeup signal is forwarded to a second memory bank in response to determining the first gated memory array supply voltage has reached a specified voltage.

Abstract: A static random access memory (SRAM) device includes a memory array of a plurality of memory cells, a controller that receives an external clock signal formed by a succession of external pulses and generates an internal clock signal formed by a succession of internal pulses, and a driving circuit that receives the internal clock signal. The controller is operable in a first mode, wherein the controller generates, for each external pulse, a corresponding internal pulse and the controller controls the driving circuit so that the driving circuitry carries out one access to the memory array for each internal pulse. The controller is further operable in a second mode, wherein the controller generates, for each external pulse, a pair of internal pulses, and the controller controls the driving circuitry so that, for each pair of internal pulses, the driving circuitry writes a first data item in a set of memory cells, and then reads the set of memory cells, so as to acquire a second data item.

Abstract: In a recording apparatus, a generating unit generates a timing signal by delaying a clock signal. A control unit controls so that a predetermined command is output multiple times to a storage device and each piece of data sent by the storage device in response to the multiple predetermined commands is received in accordance with the timing signal having a different delay amount for each of the multiple predetermined commands. A detection unit detects, in order of the delay amounts, a range of the delay amounts of the timing signals for which predetermined data has been successfully received. A setting unit sets, in a case where a plurality of the ranges have been detected by the detection unit, a single delay amount in a single predetermined range among the plurality of ranges, as the delay amount of the timing signal.