Abstract: A semiconductor memory device may include: a memory cell array; a first address controller configured to receive a first command and a first address and generate a first control signal in response to the first command; and a second address controller configured to receive a second address and a second command inputted at the same time as the first command, and generate a second control signal in response to the second command.

Abstract: Apparatuses and method for adjusting a path delay of a command path are disclosed. In an example apparatus, a command path configured to provide a command from an input to an output includes an adjustable delay. The adjustable delay is configured to add delay to the command path delay, wherein the delay of the adjustable delay is based at least in part on a phase relationship between a feedback signal responsive to the command propagating through the command path and a clock signal. An example method includes configuring a command path to add delay to a command path delay to provide an internal write command signal to perform a write operation on write data corresponding to the internal write command, and propagating the write data corresponding to the internal write command through a data path without further delaying the write data to match the command path delay.

Abstract: A semiconductor memory device includes a delay locked loop configured to generate a delay locked loop (DLL) clock signal by delaying an external clock signal by a first delay time and generate a feedback clock signal by delaying the DLL clock signal by the second delay time, wherein the first delay time corresponds to a phase difference between the external clock signal and the feedback clock signal and an output enable control circuit configured to generate an output enable signal in response to CAS latency information and the first and second delay times after the delay locked loop performs a locking operation.

Abstract: A method for reading data from a plurality of DRAM devices connected to common command, address, and data busses. A clock signal is provided to the plurality of DRAM devices. A read command and address to the plurality of DRAM devices on the command and address busses in synchronization with the clock signal. A read clock signal is provided to the plurality of DRAM devices to initiate a read operation in one of the plurality of DRAM devices that is selected by the address. The one DRAM device delays the read clock signal by an amount based on a speed of the one of the plurality of DRAM devices to generate. First delayed read clock and second delayed read clock signals are provided. The read data is received on the data bus in synchronization with the second delayed read clock signal.

Abstract: Semiconductor devices are provided. The semiconductor device includes a charge controller, a delay unit and a discharger. The charge controller controls an amount of electric charges on a first node to output a drive signal through the first node. The delay unit includes a capacitor coupled to the first node and retards the drive signal to generate an output signal. A delay time of the drive signal is controlled according to an amount of electric charges of the first node. The discharger discharges the electric charges of the first node when the amount of electric charges of the first node is equal to a predetermined value.

Abstract: A method of avoiding a write collision in single port memory devices from two or more independent write operations is described. A first write operation having a first even data object and a first odd data object is received from a first data sender. A second write operation having a second even data object and a second odd data object is received from a second data sender at substantially the same time as the first write operation. The second write operation is delayed so that the first even data object writes to a first single port memory device at a different time than the second even data object writes to the first single port memory device. The second write operation is delayed so that the first odd data object writes to a second single port memory device at a different time than the second odd data object.

Abstract: A semiconductor device includes a first controlled chip and a control chip stacked therewith. The first controlled chip includes a first circuit outputting a data signal in response to a synchronization signal, an input/output circuit outputting the data signal to a data terminal in synchronization with a delayed synchronization signal, and a replica circuit replicating an output circuit and outputting a replica signal to a first replica terminal in synchronization with the delayed synchronization signal. The control chip includes a first control circuit outputting a synchronization signal and receiving a data signal, a delay adjustment circuit delaying the synchronization signal and outputting the same as a delayed synchronization signal, a phase comparator circuit comparing the phases of the replica signal and the synchronization signal, and a delay control circuit controlling the delay amount of the delay adjustment circuit based on a comparison result of the phase comparator circuit.

Abstract: Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error.

Abstract: A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined and set using controller circuits according to a dynamic calibration procedure performed from time to time. In the system, determining and setting the control settings for the read data delay circuits for providing CAS latency compensation is performed independently and parallely in each of a plurality of byte lanes.

Abstract: A memory device is provided comprising an array of memory cells. During a read operation, voltage on a read bit line will transition towards a second voltage level if a data value stored in that activated memory cell has a first value, and sense amplifier circuitry will then detect this situation. If that situation is not detected, the sense amplifier circuitry determines that the activated memory cell stores a second value. Bit line keeper circuitry is coupled to each read bit line and is responsive to an asserted keeper pulse signal to pull the voltage on each read bit line towards the first voltage level. Keeper pulse signal generation circuitry asserts the keeper pulse signal at a selected time. The selected time is such that the voltage on the associated read bit line will have transitioned to the trip voltage level before the keeper pulse signal is asserted.

Abstract: A method is provided for relaying data to a memory array operating in synchronization with a clock signal having a first transition edge. A data strobe signal having a second transition edge corresponding to the first transition edge is provided. A first signal is provided. The data is latched into the first signal at a first time point lagged behind the first transition edge by a first time interval until a second time point in response to the first transition edge for relaying the data of the first signal to the memory array when the second transition edge appears earlier than the first transition edge.

Abstract: A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.

Abstract: Disclosed herein is a device that includes: a data strobe terminal; a data terminal; a first output driver coupled to the data strobe terminal; a second output driver coupled to the data terminal; and a data control circuit configured to enable the first and second output drivers to function as termination resistors in different timings from each other.

Abstract: A read time tracking mechanism (RTTM) for ensuring sufficient read time is provided. The read time tracking mechanism includes a read tracking circuit, which includes a tracking bit line (TBL) tracking circuit with one or more tracking cells, and a tracking word line (TWL). The RTTM also includes a sense amplifier enable (SAE) timing device configured to change the logic threshold of tracking WL (TWL) to delay the timing of signal change of TWL when necessary to ensure sufficient read time. The read time tracking mechanism is used to provide sufficient read time for memory arrays with various configurations, prepared under various process conditions, and operated under various voltages, and temperatures.

Abstract: A memory controller coupled to a memory chip having a number of sub-arrays of memory cells is configured to determine a configuration of the memory chip. The memory controller is configured to read the sub-array configuration of the memory chip and to detect sub-array level conflicts between external commands and refresh operations. The memory controller keeps one or more non-conflicting pages open during the refresh operations.

Abstract: Command paths, apparatuses, and methods for providing a command to a data block are described. In an example command path, a command receiver is configured to receive a command and a command buffer is coupled to the command receiver and configured to receive the command and provide a buffered command. A command block is coupled to the command buffer to receive the buffered command. The command block is configured to provide the buffered command responsive to a clock signal and is further configured to add a delay before to the buffered command, the delay based at least in part on a shift count. A command tree is coupled to the command block to receive the buffered command and configured to distribute the buffered command to a data block.

Abstract: A memory interface circuit, which controls capture timing of data provided from a memory according to a strobe signal provided from the memory, includes a control unit that controls an activation timing of an internal strobe gate signal, which masks the strobe signal when being deactivated, by delaying the internal strobe gate signal by a first period shorter than one cycle time of a clock signal to generate an internal strobe gate adjustment signal, and by adjusting an activation timing of the adjustment signal. A detection unit outputs a detection signal, when the strobe signal changes from a first potential to a second potential higher than the first potential, or when the first potential of the strobe signal continues for a second period or longer. The control unit adjusts the activation timing of the adjustment signal in accordance with the detection signal.

Abstract: A semiconductor device includes a data bus inversion (DBI) decision unit suitable for deciding whether a DBI operation mode is performed, based on a read data, and generating a DBI decision signal corresponding to a result of the decision; an output control unit suitable for generating an arrangement control signal in which a delay amount of time for the decision is reflected, in a DBI operation mode; a data synchronization unit suitable for synchronizing the read data with the arrangement control signal and output the synchronized read data and inverted signals of the synchronized read data, in the DBI operation mode; and a data output unit suitable for selectively outputting the synchronized read data and the inverted signals of the synchronized read data, to an external in response to the DBI decision signal, the arrangement control signal and an output control signal, in the DBI operation mode.

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract: A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row.

Abstract: A semiconductor apparatus includes a phase detecting unit that continuously detects a first delay amount during a read operation, based on a phase difference between an external clock signal and an internal clock signal; a generating unit that generates a second control signal by delaying a first control signal by a second delay amount that when added to the first delay amount, the sum is a specific time period, a valid time period of the first control signal starts when the read operation starts and is at least to equal a read time for one data signal and less than the specific time period that is from the start of the read operation until output of a received data signal; and a delay control unit that delays the data signal by the first delay amount detected at a start of a valid time period of the generated second control signal.

Abstract: A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.

Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.

Abstract: A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell.

Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, a plurality of word lines, each word line being coupled to an associated row of memory cells, and a plurality of bit lines, each bit line being coupled to an associated column of memory cells. Access circuitry is coupled to the word lines and the bit lines in order to perform access operations in respect of selected memory cells within the array. Control circuitry controls operation of the access circuitry and includes self-timed path (STP) delay circuitry. The control circuitry employs the delay indication when controlling the access circuitry to perform said access operations. Voltage supply control circuitry switches the voltage supply to at least one portion of the STP delay circuitry between a peripheral voltage supply and an array voltage supply dependent on a control signal.

Abstract: A latency control device and a semiconductor device including the same are disclosed. The latency control device includes: a code setting unit configured to output a plurality of coding signals by setting a code value having a specific delay amount in response to a code signal; a latch unit configured to latch a command signal for a predetermined time; a period control unit configured to control a delay amount of a period signal in response to an output signal of the latch unit; a selection unit configured to output an oscillation signal synchronized with the clock signal in response to the selection signal, or synchronize the oscillation signal with an output signal of the period control unit; a register unit configured to output a plurality of period signals by dividing the oscillation signal; and a comparator configured to compare the plurality of coding signals with the plurality of period signals so as to output the self-latency signal.

Abstract: A device includes a control circuit that triggers a first operation every time a specific signal is supplied thereto, and that triggers a second operation in place of the first operation in response to the first specific signal supplied after the number of the first operation performed has reached a predetermined number.

Abstract: A semiconductor device includes a command combination circuit suitable for generating a combined level signal driven in synchronization with a write command and an internal write command; and a column selection circuit suitable for generating a pulse signal which includes a pulse generated at a level transition time of the combined level signal, and a column select signal.

Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

Abstract: A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures.

Abstract: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.

Abstract: A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.

Abstract: Among other things, techniques for facilitating a write operation to a bit cell are provided. A pulse generator initializes lowering of an internal voltage level associated with a bit cell that is to be written to by a write operation. In this way, the bit cell is placed into a writeable voltage state, such that a potential of the bit cell can be overcome by the write operation. A voltage detector sends a reset signal to the pulse generator based upon the pulse generator lowering the internal voltage level past a reset trigger level. Responsive to receiving the reset signal, the pulse generator initializes charging of the internal voltage level to an original voltage level. In this way, the lowering of the internal voltage level is controlled so that one or more other bit cells are not affected (e.g., suffer data retention failure) by the relatively lower internal voltage level.

Abstract: An embodiment of the invention discloses an electronic device for reducing degradation in NMOS circuits in a tracking circuit. A first multiplexer selects, based on N bits from a row address in a memory array, which tracking circuit from a group of 2N tracking circuits will be used to provide a signal develop time for a memory cell in the memory array using a dummy word line signal. A second multiplexer selects, based on the N bits from the row address for a memory array, which output from the tracking circuits is used to enable the sense amp enable signal.

Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

Abstract: A semiconductor device is disclosed which comprises a clock generating circuit generating first and second divided clocks by dividing an input clock by first and second division number, respectively, and a counter circuit including a shift register having a plurality of stages that sequentially shifts an input signal and outputs an output signal delayed based on setting information. The counter circuit individually controls operation timings of the stages of the shift register by selectively supplying either of the first and second divided clocks to each stage of the shift register, and either of signals from the stages of the shift register is extracted and outputted as the output signal.

Abstract: A memory controller coupled to a memory chip having a number of sub-arrays of memory cells is configured to determine a configuration of the memory chip. The memory controller is configured to read the sub-array configuration of the memory chip and to detect sub-array level conflicts between external commands and refresh operations. The memory controller keeps one or more non-conflicting pages open during the refresh operations.

Abstract: A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code value of the delay control code in sequential synchronization with a plurality of delayed clocks obtained by delaying the external clock as large as predetermined delay amounts, respectively, delay the shifted read command as large as the variable delay amount, and output the result of delay as an output enable flag signal.

Abstract: A latency control device and a semiconductor device including the same are disclosed. The latency control device includes: a code setting unit configured to output a plurality of coding signals by setting a code value having a specific delay amount in response to a code signal; a latch unit configured to latch a command signal for a predetermined time; a period control unit configured to control a delay amount of a period signal in response to an output signal of the latch unit; a selection unit configured to output an oscillation signal synchronized with the clock signal in response to the selection signal, or synchronize the oscillation signal with an output signal of the period control unit; a register unit configured to output a plurality of period signals by dividing the oscillation signal; and a comparator configured to compare the plurality of coding signals with the plurality of period signals so as to output the self-latency signal.

Abstract: A semiconductor device includes a command decoder configured to decode a command and generate a composite command; a first generation block configured to generate a first control signal for performing a first operation based on the composite command; a delay control block configured to delay the composite command by a predetermined time and output a delayed composite command; and a second generation block configured to generate a second control signal for performing a second operation based on the delayed composite command.

Abstract: A method of retiming a circuit that includes a RAM having data stored therein, a register following the RAM, and registers preceding the RAM for registering input, address and enable signals of the RAM includes pushing a value in the register following the RAM back into a memory location in the RAM, pushing back data stored in the RAM and initial values in the registers preceding the RAM to accommodate the value pushed back from the register following the RAM, and setting new values in the registers preceding the RAM so that, on a first clock cycle after retiming, the circuit assumes a condition before retiming. The method also may be used to configure a programmable logic device with a user logic design.

Abstract: A data strobe control device is disclosed, which relates to a technology for controlling a data write path of a semiconductor memory device. The data strobe control device includes: a plus-mode controller configured to output a first control signal for controlling a first mode and a plus on-the-fly signal upon receiving a plus-mode signal and an on-the-fly signal; an on-the-fly controller configured to output a second control signal for controlling a second mode according to the on-the-fly signal and an operation signal; a path controller configured to latch an address in response to the second control signal during the second mode, latch the address in response to the first control signal during the first mode, and accordingly output an address latch signal; and a strobe pulse generator configured to output a strobe control signal synchronized with a control clock signal in response to the address latch signal and a burst length signal.

Abstract: Methods and apparatuses for adjusting data strobe signals are disclosed. An example apparatus may include a control circuit that is configured to receive an address and a strobe signal. The control circuit may further be configured to delay the strobe signal based, at least in part on the address to provide a delayed strobe signal. The example apparatus may further include a sense amplification circuit coupled to the control circuit. The sense amplification circuit may be configured to sense signals responsive, at least in part, to receipt of the delayed strobe signal.

Abstract: A power management method includes receiving a first command with first address indicating a first high power operation that is immediately executed in a first memory die, after receipt of the first command, receiving a second command with a second address indicating a second high power operation, such that an immediate execution of the second high power operation would overlap the first high power operation, and delaying execution of second high power operation through a first waiting period that ends upon completion of the first high power operation, while applying a reference voltage to a second word line of the second memory die indicated by the second address.

Abstract: A current flowing through a voltage line and/or a data line in a column of a tracking circuit is determined. A threshold tracking time delay of the tracking circuit is determined. Based on the determined current handled by the voltage line and/or the data line and the determined threshold tracking time delay, a plurality of columns in the tracking circuit, a number of first cells in each column of the plurality of columns, and a number of second cells in the each column of the plurality of columns are determined.

Abstract: Disclosed herein is a device includes a command generation circuit that activates first and second command signals, an internal circuit that includes a plurality of transistors that are brought into a first operation state when at least one of the first and second command signals is activated, and an output gate circuit that receives a first signal output from the internal circuit, the output gate circuit being configured to pass the first signal when the second command signal is deactivated and to block the first signal when the second command signal is activated.

Abstract: In some embodiments, disclosed herein are approaches for facilitating voltage controlled slaved (or replica) clock circuits such as voltage controlled delay lines (VCDLs) off of a master clock generator. In such systems, one or more control (or bias) voltages are generated to control a master clock generator such as a master DLL. One or more “slave” circuits may be controlled off of the master's control voltage so that their clocks replicate desired traits of the master clock.

Abstract: Disclosed herein is a device that includes a clock generation circuit that generates an internal clock signal during a normal operation and stops generation of the internal clock signal during a wafer-level burn-in test, a clock tree line that transmits the internal clock signal, and a selector that supplies a dummy clock signal, which is different from the internal clock signal, to the clock tree line during the wafer-level burn-in test.

Abstract: A solid state storage device receives a device sleep signal and a power signal from a host. The solid state storage device includes a control chip, a sleep control circuit, and a regulator. If the device sleep signal is activated, the control chip temporarily stores a system parameter into a flash memory module and then generates an acknowledge signal. The sleep control circuit receives the power signal, the device sleep signal and the acknowledge signal. If both of the device sleep signal and the acknowledge signal are activated, the sleep control circuit generates a disable state and a wake-up state. Moreover, if the power signal is received by the regulator and the sleep control circuit generates the disable state, the regulator stops providing a supply voltage to the control chip, so that the solid state storage device enters a sleep mode.

Abstract: According to an embodiment, a load adjusting circuit adjusts the load of an inverter circuit based on a threshold voltage of a first conductive type transistor provided on the inverter circuit, and a driving force adjusting circuit adjusts the driving force of the inverter circuit based on the threshold voltage of the first conductive type transistor.