Abstract: A semiconductor device may include: a first receiver configured to receive a chip select signal from a receiving node to which a termination resistor is coupled and configured to generate a first internal chip select signal; a command pulse generation circuit configured to generate a command pulse for entering into a self-refresh operation based on an internal command address and the first internal chip select signal; and an operation control circuit configured to, when the semiconductor device enters the self-refresh operation based on the command pulse, generate a resistor value change signal that adjusts the value of the termination resistor.

Abstract: An integrated circuit includes a clock control circuit coupled to a reference clock signal node and a plurality of circuits including a voltage regulator, a digital circuit, and an analog circuit. The voltage regulator, in operation, supplies a regulated voltage. The clock control circuit, in operation, generates a system clock. Input/output interface circuitry is coupled to the plurality of circuits and a common input/output node. The input/output interface circuitry, in operation, selectively couples one of the plurality of circuits to the common input/output node.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: A printed circuit board may include a controller socket, first and second sockets provided on a top surface, third and fourth sockets provided on a bottom surface, and first, second, and third branching points. The first branching point may be spaced apart from the controller socket by a first distance in a horizontal direction parallel to the top surface and may be electrically connected to the controller socket. The second branching point may be spaced apart from the first branching point by a second distance longer than the first distance and may be electrically connected to the first branching point, the first and third sockets. The third branching point may be spaced apart from the first branching point by a third distance longer than the first distance and may be electrically connected to the first branching point, the second and fourth sockets.

Abstract: The present document discloses a transmission arrangement for coupling an amplifier to a transmission medium. An input node of the amplifier is couplable to a transmitter and an output node of the amplifier is couplable to a terminal of the transmission medium. The transmission arrangement may comprise a first branch coupled between the input node of the amplifier and an intermediate node which is couplable to a receiver. The transmission arrangement may further comprise a second branch coupled between the output node of the amplifier and the intermediate node. In particular, the first branch comprises a first capacitive element, while the second branch comprises a second capacitive element. Furthermore, at least one of the first and second branches further comprises a phase matching circuit coupled in series with the respective capacitive element.

Abstract: A bus driver module with controlled circuit is connected to a controller area network bus for generating a high side output or a low side output, comprising a transition controlled circuit and an output driver. The transition controlled circuit comprises a first pathway controlled unit connected in parallel with a second pathway controlled unit for generating a side switching voltage. The output driver is connected in series with the transition controlled circuit and receives the side switching voltage so as to accordingly generate the output bus signal. Each of the first and second pathway controlled unit comprises a plurality of switches and can be activated depending on an input signal. By controlling the switches of the first or second pathway controlled unit to be sequentially turned on and off successively, the side switching voltage is characterized by a smooth phase transition, low common mode noise and better EMI performances.

Abstract: A transmission device according to the disclosure includes: a controller that selects one of a plurality of operation modes; and a first transmitter that includes a first capacitance setting section that sets a load capacitance in accordance with an operation mode selected by the controller, and is configured to be able to output, to a first output terminal, a first signal having a signal format according to the selected operation mode, among a plurality of signal formats.

Abstract: An inter-die data transfer system includes a receiver circuit in a receiver die coupled to a sender circuit in a sender die through a bus. The receiver circuit includes a safe sample selection circuit and a latency adjustment circuit. The safe sample selection circuit receives from the sender circuit a plurality of training data signals, and determines a safe sample selection signal for a first bit of the bus. The latency adjustment circuit determines a latency adjustment selection signal for the first bit of the bus. A user data safe sample is selected using the safe sample selection signal from a plurality of user data samples associated with a first user data input signal associated with the first bit of the bus. Latency adjustment is performed to the user data safe sample to generate a first user data output signal using the latency adjustment selection signal.

Abstract: Embodiments of the invention provide a command-oriented method to lower power consumption of PHY during idle time periods. The idle time periods occur because HBM Commands have certain timing windows where there is no data transmission on DFI data signals between the memory controller and the PHY data slice. These windows may be utilized to power down the PHY data slice data path through DFI signal handshaking. In contrast to the conventional low power mode, this method provides an advanced low power mode that can further reduce power consumption in different modes at each suitable idle time based on different command types.

Abstract: A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may perform a calibration operation for setting a resistance value of the output circuit. The calibrations circuit may perform the calibration operation by being coupled, through a signal transmission line, to a reference resistor provided in another semiconductor device.

Abstract: Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.

Abstract: Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.

Abstract: A circuit for testing a memory includes a complementary charge trap memory cell, which includes a first transistor and a second transistor. A logical value of the cell corresponds to respective states of the first transistor and the second transistor. The circuit further includes a first bitline coupled to the first transistor, where the first transistor is configured to apply a first voltage to the first bitline. The circuit includes a second bitline coupled to the second transistor, where the second transistor is configured to apply a second voltage to the second bitline. The circuit also includes a sense circuit configured to output, prior to programming of the complementary charge trap memory cell, a logical high signal or a logical low signal in response to the first voltage on the first bitline and the second voltage on the second bitline.

Abstract: A semiconductor apparatus may include an on-die termination (ODT) enable signal generator configured to enable an ODT enable signal in response to a data strobe signal, or enable the ODT enable signal in response to a command latch enable signal and an address latch enable signal. The semiconductor apparatus may include an ODT circuit configured to perform an ODT operation in response to the ODT enable signal.

Abstract: A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.

Abstract: A through silicon via (TSV) repair circuit is provided. The TSV repair circuit includes at least two transmission control switches and at least two transmission path modules. Two transmission control switches transmit an input signal of a first chip or a second chip to one of two terminals in each of the transmission path modules according to a switch signal. Each transmission path module includes at least two data path circuits and corresponding TSVs. Each data path circuit includes an input driving circuit, a short-circuit detection circuit and a leakage current cancellation circuit. The short-circuit detection circuit detects whether to detect whether short-circuit on the TSV and a silicon substrate is present and generate a short-circuit detection output signal. The leakage current cancellation circuit to avoid a leakage current generated by a first level voltage to flow into the silicon substrate according to the short-circuit detection output signal.

Abstract: Semiconductor systems are provided. The semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device generates an input calibration signal during a mode register write operation and receives an output data and an output calibration signal to control a recognition point of a logic level of the output data according to a delay time of the output calibration signal during a read operation. The second semiconductor device stores the input calibration signal therein during the mode register write operation and outputs the output calibration signal and the output data during the read operation.

Abstract: A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal.

Abstract: A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.

Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Abstract: According to one embodiment, there are provided a memory which is provided on a circuit board, a controller which is provided on the circuit board and controls the memory, and a signal line which is formed on the circuit board and configured to perform data transmission between the controller and the memory, in which a width of the signal line in the place where the signal line is led out from the memory is large compared with a place disposed under the memory.

Abstract: A semiconductor apparatus includes a memory chip which includes: a memory area; a data input/output block configured to communicate with the memory area; and a data transmission/reception block configured to connect one of a plurality of channels and a pad to the data input/output block, wherein the plurality of channels are configured to input and output normal data to and from another chip, and the pad is configured to input and output test data.

Abstract: A semiconductor device including a control signal generator and an internal refresh signal generator is provided. The control signal generator generates first and second control signals, one of which is selectively enabled in response to temperature code signals and mode set signals after a pulse of an internal refresh signal is outputted by the internal refresh signal generator. The temperature code signals are obtained from temperature signals. The internal refresh signal generator outputs a refresh command signal as the internal refresh signal when the first control signal is enabled. Further, the internal refresh signal generator outputs the refresh command signal as the internal refresh signal at a moment that the refresh command signal is inputted thereto by a predetermined number of times when the second control signal is enabled.

Abstract: Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting.

Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

Abstract: A semiconductor memory apparatus includes a boundary circuit unit positioned between a low voltage page buffer and a high voltage page buffer and having circuits configured to electrically couple the low voltage page buffer and the high voltage page buffer. The boundary circuit unit includes: a first boundary circuit unit having first and second transistors configured to receive data of a corresponding memory cell area through a signal transmission line selected from a plurality of signal transmission lines extended and arranged along a first direction for each column; a second boundary circuit unit disposed adjacent in the first direction from the first boundary circuit unit and having the plurality of signal transmission lines extended and arranged thereon; and an active region where the first transistor is formed and an active region where the second transistor is formed are isolated from each other.

Abstract: A semiconductor device comprises transmission lines, inverting circuits, first, second and third switches, global sense amplifiers, and a control circuit. The first switch switches between the transmission line and the input of the inverting circuit, the second switch switches between the transmission line and the output of the transmission line, and the third switch switches between the adjacent transmission lines. The control circuit turns off the first and second switches so that the transmission lines are brought into a floating state in a state where signals of the transmission lines are held in the inverting circuits by the global sense amplifiers. After charge sharing of the transmission lines occurs by turning on the third switches within a predetermined period, the control circuit turns off the second switches so that the transmission lines are inverted and driven via the inverting circuits and the second switches.

Abstract: A device includes a control circuit that triggers a first operation every time a specific signal is supplied thereto, and that triggers a second operation in place of the first operation in response to the first specific signal supplied after the number of the first operation performed has reached a predetermined number.

Abstract: A storage medium including a plurality of memory cells, a plurality of transmission lines, a driving module and a floating detection module is disclosed. The memory cells store data. The transmission lines are coupled to the memory cells. The driving module accesses the memory cells via the transmission lines. The floating detection module includes a reset unit, a plurality of connectors and a detector. The reset unit is coupled to a detection line. Each of the connectors is coupled between one of the transmission lines and the detection line. The detector determines whether a state of at least one of the transmission lines is a floating state according to a level of the detection line.

Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.

Abstract: A system includes a first chip configured to supply a training command and a second chip configured to transfer to the first chip a measured time for performing an operation in response to the training command.

Abstract: Semiconductor modules are provided. The semiconductor module includes semiconductor chips with one or more ranks. The semiconductor module includes a mode register configured for storing a first information signal whose logic level is set or determined according to a number of the ranks and an on-die termination (ODT) controller configured for generating an internal control signal for activating an ODT circuit in response to the first information signal. The internal control signal is enabled during a read operation or disabled during a write operation.

Abstract: The data transmission circuit includes: a plurality of local bit line pairs through which data is read simultaneously; a plurality of voltage change detection circuits provided for the plurality of local bit line pairs; a global bit line pair; a plurality of column selection circuits configured to select one of the local bit line pairs and connect the selected local bit line pair to the global bit line pair; and a sense amplifier connected to the global bit line pair. The sense amplifier is controlled by a sense amplifier activation signal to which the outputs of the plurality of voltage change detection circuits are connected, whereby the voltage of a selected read data line pair is amplified using discharge of a non-selected read data line pair, to achieve high-speed read.

Abstract: A shift register structure is presented that can be used in fixed or variable rate serial to parallel data conversions. In an 1 to N conversion, data is received off an m-bit serial data bus and loaded into a N by m wide latch, before being transfer out onto an (N×m)-wide parallel data bus. Based on information on how of the N m-bit wide data units are to be ignored, the data will be clocked out at a variable rate. When loading data off the serial bus into the latch, upon refresh the current data is loaded into all N units of the latch, with one less latch being loaded at each subsequent clock. When the content of a unit of latch is to be ignored on the parallel bus, that unit is closed at the same time as the preceding unit so that it is left with redundant data.

Abstract: A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.

Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.

Abstract: A system is provided for transmitting signals. The system comprises a first processing unit, a cache memory, and a package. The first processing unit comprises a first ground-referenced single-ended signaling (GRS) interface circuit and the second processing unit comprises a second GRS interface circuit. The cache memory comprises a third and a fourth GRS interface circuit. The package comprises one or more electrical traces that couple the first GRS interface to the third GRS interface and couple the second GRS interface to the fourth GRS interface, where the first GRS interface circuit, the second GRS interface, the third GRS interface, and the fourth GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.

Abstract: A semiconductor apparatus includes a multi-chip module which multi-chip module comprises a first and a second chips. The semiconductor apparatus comprises a first data line in the first chip to carry first read data; a first controller, in the first chip, configured to generate first output data on a first output data line in the first chip based on the first read data transmitted from the first data line; a first data transmitter configured to electrically connect the first output data line to the second chip.

Abstract: A memory circuit device having at least one test element interconnecting memory sections can include at least one first switch coupled to a first memory section between a first node within a tested section and an intermediate node, a test switch coupled between the intermediate node and a forced voltage node, and a second switch coupled between the intermediate node and a second node; wherein the forced voltage node is selectively coupled to receive a forced voltage substantially the same as a voltage applied to the second node, and the second node is coupled to at least a second memory section.

Abstract: A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines.

Abstract: An operating method of a nonvolatile memory device is provided which includes receiving a command sequence; detecting whether the input command sequence accompanies an impedance calibration operation; and if the input command sequence accompanies the impedance calibration operation, simultaneously performing an operation corresponding to the input command sequence and the impedance calibration operation.

Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.

Abstract: A semiconductor memory system configured to exchange signals through channels may include a memory control device configured to have a plurality of channels, a plurality of memory devices configured to be connected to each of the plurality of channels, wherein the plurality of channels share at least one of the plurality of memory devices.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: A data signal is sampled by generating a read enable signal at a first semiconductor device which is intended for a second semiconductor device. A read enable signal with at least some I/O pad delay included is obtained, including by passing the read enable signal intended for the second semiconductor device at least partially through an input/output (I/O) pad on the first semiconductor device. At the first semiconductor device, a data signal from the second semiconductor is sampled using the read enable signal with at least some I/O pad delay included.

Abstract: A semiconductor device according to the present invention includes plural core chips CC0 to CC7 to which mutually different pieces of chip identification information LID are allocated, and an interface chip IF that controls the core chips CC0 to CC7. The interface chip IF receives address information ADD for specifying a memory cell, and supplies in common a part of the address information to the core chips CC0 to CC7 as chip selection information SEL to be compared with the chip identification information LID. With this configuration, it appears from a controller that an address space is simply enlarged. Therefore, an interface that is same as that for a conventional semiconductor memory device can be used.

Abstract: A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology.

Abstract: Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.

Abstract: Correction of duty cycle distortion of DQ and DQS signals between a memory controller and a memory is corrected by determining a duty cycle correction factor. The duty cycle distortion is corrected by applying the duty cycle correction factor to the plurality of differential DQS signals. The duty cycle distortion is corrected across a plurality of differential DQS signals between the memory controller and the bursting memory.