Abstract: A semiconductor memory device includes a first clock input unit for generating a first clock signal based on a signal at an intersection of a system clock signal and an inverted system clock signal; a second input unit for generating a second clock signal based on a signal at an intersection of the system clock signal and a reference signal; a third input unit for generating a third clock signal based on a signal at an intersection of the inverted system clock signal and the reference signal; a delay unit for generating a delay clock signal by delaying the first clock signal in response to a delay control signal; and a clock delay control unit for generating the delay control signal in response to a phase difference between the second clock signal and the delay clock signal or a phase difference between the third clock signal and the delay clock signal.

Abstract: A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.

Abstract: A memory system and method is discussed. The memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.

Abstract: In an embodiment, an improved charge pump circuit is provided to control a threshold voltage increase of a charge transmission transistor during a charge transfer period, and to prevent a latch-up generation during a charge non-transfer period. A charge transmission transistor transmits the voltage of a boosting node to a high voltage generation terminal in response to the voltage of a control node. In a bulk connection switch, during the charge transfer period the high voltage generation terminal is connected to the bulk of the charge transmission transistor and during the charge non-transfer period the bulk is connected to the low voltage, being lower than that of the voltage appearing at the boosting node of the charge transmission transistor or the high voltage generation terminal. Charge transmission efficiency and pumping operation reliability are improved, increasing the reliability of data access operations in a semiconductor memory device, for example.

Abstract: A semiconductor memory device reduces power consumption during a refresh operation. The semiconductor memory device comprises a voltage generator, a sensing controller, an output driver and a data transmitter. The voltage generator is configured to generate an internal power voltage, which is lower during a power saving mode than during a normal mode, for a peripheral area. The sensing controller is configured to generate a control signal corresponding to a level of the internal power voltage. The output driver is configured to drive a transmitting data by using an output voltage. The data transmitter is configured to convert an inputting data into the transmitting data by using the internal power voltage or convert the inputting data into the transmitting data by using the output voltage in response to the control signal.

Abstract: Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of devices by providing for an interface having inputs and/or outputs that are adjustably delayed. This allows embodiments of the present invention to sense the signal delay and utilize adjustable input or output delays to correct the signal timing relationships such that correctly timed communication signals are received by the internal circuitry of the device. In one embodiment of the present invention, a register is utilized to adjust the timing delay of individual input and/or output signals for the device. This increases the robustness of the device and its resistance to communication or data corruption, allowing larger ranges of environmental conditions and input capacitances of systems or communication busses to be tolerated.

Abstract: Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the data value of the floating-gate memory cell at power-up or upon request. A latch driver circuit can write data values to the fuse latch without affecting the data value stored in the floating-gate memory cell. The fuse circuits can further utilize the same structure, pitch, bit-line organization and word-line organization as the memory device's memory array. As the fuse circuits can utilize the same structure and organization, the data value of the fuse circuit can be programmed, erased and read using the same data path as the regular memory array.

Abstract: Provided is a memory system having a multi-drop bus structure. The memory system includes a bus, a memory controller in which a port connected to the bus is terminated by a resistor having a first impedance value, a connector connected to a point having the first impedance value from the memory controller on a bus line, and a memory module connected to the connector. The memory module includes a first load connected to the connector and having the first impedance value, a second load connected to the first load and having a second impedance value, a first chip in which a port connected to the second load is terminated by a resistor having the second impedance value, a via hole penetrating a printed circuit board of the memory module between the first load and the second load, a third load connected to the via hole and having the second impedance value, and a second chip in which a port connected to the third load is terminated by a resistor having the second impedance value.

Abstract: A memory device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information associated with the output data. The input and output auxiliary information include inverting codes, parity codes, temperature information or time delay information. The input and output auxiliary information are transferred to and from the memory device on the same terminals that the input data and the output data are transferred.

Abstract: A semiconductor memory device for broadening a data I/O window includes: a buffer driving block for generating a buffer driving signal in response to an additive delay signal and a CAS delay signal, wherein an activation period of the buffer driving signal is determined based on the additive delay signal and a combination of delayed additive delay signals; and a data buffer for receiving an external data at an activation of the buffer driving signal.

Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Abstract: A multi-port memory device improves efficiency of a global data drive by controlling the global data bus to transmit data in a predetermined range. The multi-port memory device includes a global data bus; transmitters and receivers; a termination unit for controlling the global data bus to transmit the data in a range between a first voltage and a second voltage in response to an active mode signal; and a voltage generator for generating the first and the second voltages. The first voltage is higher than a ground voltage and the second voltage is lower than a power supply voltage.

Abstract: A method and apparatus are provided for active termination control in a memory by an module register providing an active termination control signal to the memory. The module register monitors a system command bus for read and write commands. In response to detecting a read or write command, the module register generates an active termination control signal to the memory. The memory turns on active termination based on information programmed into one or more mode registers of the memory. The memory maintains the active termination in an on state for a predetermined time based on information programmed into one or more mode registers of the memory.

Abstract: The data for being processed are transmitted by utilizing a daisy chain constitution using a plurality of semiconductor integrated circuit devices each having an input terminal for receiving an input signal containing any one of an instruction, a data, a position where the data exists or a timing signal, and an output terminal for producing a signal formed in an internal circuit in response to the input signal or fed through the input terminal, wherein among the plurality of semiconductor integrated circuit devices, the output terminal of the semiconductor integrated circuit device in the preceding stage and the corresponding input terminal of the semiconductor integrated circuit device of the next stage are connected together.

Abstract: The invention provides an improved memory system that addresses signal degradation due to transmission line effects. The improved memory system includes a first buffer, at least one first memory device coupled to the first buffer, and a plurality of signal traces. The first buffer and memory device are mounted on a motherboard. Likewise, the plurality of signal traces is routed on the motherboard. Doing so eliminates stub loads that cause signal reflection that, in turn, result in signal degradation.

Abstract: Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell array. Since the parity data is generated by a parity generation circuit, it is difficult to write a desired pattern to the parity cell array. The regular data and the parity data are exchanged with each other by a switch circuit, so that the regular data can be written to the parity cell array and the parity data can be written to the regular cell array. This enables the write of desired data to the parity cell array. A test of the parity data can be easily conducted. In particular, a leakage test or the like between memory cells can be easily conducted.

Abstract: A memory circuit 10 includes: a feed-through input terminal 13 for inputting a signal different from a signal to be inputted when reading and writing memory cells; an intermediate buffer circuit 14 provided between regions where the memory cells are arranged, for relaying the signal inputted through the feed-through input terminal 13; and a feed-through output terminal 15 for outputting the signal relayed by the intermediate buffer circuit 14. Connections between the feed-through input terminal 13 and the intermediate buffer circuit 14 and between the intermediate buffer circuit 14 and the feed-through output terminal 15 are established by feed-through wires 16, 17, respectively. The feed-through wires 16, 17 are not connected to either a wire to be used when reading and wiring the memory cells, or the memory cells.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: A method and apparatus are provided for active termination control in a memory by an module register providing an active termination control signal to the memory. The module register monitors a system command bus for read and write commands. In response to detecting a read or write command, the module register generates an active termination control signal to the memory. The memory turns on active termination based on information programmed into one or more mode registers of the memory. The memory maintains the active termination in an on state for a predetermined time based on information programmed into one or more mode registers of the memory.

Abstract: A method and apparatus are provided for active termination control in a memory by a module register providing an active termination control signal to the memory. The module register monitors a system command bus for read and write commands. In response to detecting a read or write command, the module register generates an active termination control signal to the memory. The memory turns on active termination based on information programmed into one or more mode registers of the memory. The memory maintains the active termination in an on state for a predetermined time based on information programmed into one or more mode registers of the memory.

Abstract: A memory device for reducing the number of data read lines needed in a memory device. Specifically, multiple helper flip-flops are used to prefetch data in a memory device. The helper flip-flops are configured to latch one or two of the data bits from a 4-bit prefetch in an alternating periodic fashion, thereby necessitating fewer data lines.

Abstract: A method and apparatus are provided for active termination control in a memory by a module register providing an active termination control signal to the memory. The module register monitors a system command bus for read and write commands. In response to detecting a read or write command, the module register generates an active termination control signal to the memory.

Abstract: A method and apparatus are provided for active termination control in a memory. The memory turns on active termination based on information programmed into one or more mode registers of the memory. The memory maintains the active termination in an on state for a predetermined time based on information programmed into one or more mode registers of the memory.

Abstract: A pseudo-synchronous temporary storage element transports data between two system blocks with different clock systems by pseudo-synchronizing the clock edges of the two clock signals. The pseudo-synchronization circuit may be an integral part of a storage element, a separate pseudo-synchronization device, or a discrete add-on circuit to an off the shelf storage element device.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: A current mode output driver and output current control method of controlling an output current using a gate voltage are provided. The current mode output driver, which outputs data read from a memory core to a transmission line, includes a gate voltage control circuit, a bias circuit, and a driver circuit. The gate voltage control circuit generates a predetermined gate voltage in response to a current control signal. The bias circuit outputs the gate voltage as a first enable signal in an active mode, and outputs a ground voltage as a second enable signal in a standby mode. The driver circuit drives a predetermined output current in response to the first enable signal, outputs the predetermined output voltage to the transmission line according to the data, and stops its operation in response to the second enable signal. The gate voltage control circuit changes the level of the gate voltage according to a value of the current control signal and output the changed result.

Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Abstract: Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the data value of the floating-gate memory cell at power-up or upon request. A latch driver circuit can write data values to the fuse latch without affecting the data value stored in the floating-gate memory cell. The fuse circuits can further utilize the same structure, pitch, bit-line organization and word-line organization as the memory device's memory array. As the fuse circuits can utilize the same structure and organization, the data value of the fuse circuit can be programmed, erased and read using the same data path as the regular memory array.

Abstract: A synchronous memory device and a synchronous multi-port memory device preventing a skew between data and data strobe signal according to data transmission path is disclosed. In order to eliminate such a position dependence, the synchronous memory device and the synchronous multi-port memory device adopt a scheme of transmitting the data strobe signal together with the data. If a data driving block transmits the data capture pulse together with the data, the data and the data capture pulse pass the same delay without regard to the data transmission/reception blocks, thus preventing the occurrence of the skew. In other words, the present invention adopts a source synchronization scheme, which is used at an outside of the conventional synchronous DRAM, into the memory device. Specifically, the present invention can be applied to a synchronous multi-port memory device having a plurality of independent ports.

Abstract: Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to write the data directed to at least one row through a write operation causing the data to written to the row of sense amplifiers versus from the row of memory cells, directly, and to store an indication that the data cached by the row of sense amplifiers is dirty.

Abstract: A method for providing a shared write driver is provided. The method includes providing a write driver for a memory array. The memory array comprises a plurality of memory columns. The write driver is coupled to the plurality of memory columns.

Abstract: Each memory block of a memory device a plurality of memory cells connected to a plurality of bit line pairs, a column selecting circuit, and a pre-charge and write control circuit. The column selecting circuit includes a plurality of CMOS transmission gates, each CMOS transmission gate including an NMOS transistor connected between one bit line of a bit line pair and a sense bit line of a sense bit line pair, and a PMOS transistor connected between the one bit line and one of the write bit lines of a write bit line pair. During a write operation, only the NMOS transistor of a selected one of the CMOS transmission gates is turned on, and the PMOS transistor of the selected CMOS transmission gate and the PMOS and NMOS transistors of all of the CMOS transmission gates except the selected one are all turned off.

Abstract: A semiconductor memory device having a bank for storing a data and a port as a data I/O terminal includes a transmitter for delivering the data inputted from the port; a global data bus for flowing an appearing current corresponding to the data outputted from the transmitter; and a receiver for sensing the appearing current by using a current-mirror and delivering the data corresponding to the sensed appearing current into the bank, wherein a swing range of a data bus voltage in response to the appearing current is narrower than a gap between a supply voltage and a ground.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: A circuit topology for high-speed memory access. In one embodiment, an electronic circuit includes a memory controller. The memory controller is coupled to a memory module by a first plurality of transmission lines. The memory module may include a second plurality of transmission lines coupled to the first plurality. The memory module further includes a first memory bank coupled to the second plurality of transmission lines and a third plurality of transmission lines. A second memory bank may be coupled to the third plurality of transmission lines. Each of the first, second, and third pluralities of transmission lines may be part of a common bus.

Abstract: In a memory device which is used with the memory device connected to a data bus, the memory device includes an active termination circuit for terminating the memory device when the active termination circuit is electrically put into an active state and for unterminating the memory device when the active termination circuit is electrically put into an inactive state. The memory device further includes a control circuit for controlling the active termination circuit to electrically put the active termination circuit into the active state or the inactive state.

Abstract: The invention provides a semiconductor integrated circuit device having a signal transmission path realizing high speed and low power consumption with a simple configuration. The device has a signal transmission path for transmitting a signal by discharging one of first signal lines corresponding to complementary input signals in a plurality of first signal lines precharged by a precharge circuit, and a self reset circuit for detecting the discharge level of the pair of signal lines corresponding to the complementary signals out of the plurality of first signal lines and operating the precharge circuit at a timing later than the period of discharging.

Abstract: A memory system includes a memory device that includes an active termination circuit. The memory system further includes a controller circuit that includes a frequency control circuit that is configured to modulate a system clock between a first frequency value and a second frequency value, greater than the first frequency value, responsive to a control signal. The controller circuit is further configured to determine an active termination value for the active termination circuit responsive to the system clock at the first frequency value, and to apply commands to the memory device responsive to the system clock at the second frequency value.

Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Abstract: A signal delay control circuit for use in a semiconductor memory device is disclosed. The circuit includes a first reference voltage generating unit for generating a first reference voltage; a second reference voltage generating unit for generating a second reference voltage that is lower than the first reference voltage; a control signal generating unit for generating a clock signal to drive input and output operations of internal circuits; and an impedance circuit in circuit with the first and second reference voltage generating units for generating a plurality of reference voltages to be applied to the internal circuits wherein the reference voltages are set in accordance with a distance between the control signal generating unit and the respective one of the internal circuits.

Abstract: A nonvolatile switch has: an input terminal; an output terminal; a selection terminal; a first and a second biasing terminal; a memory element of flash type, having a first conduction region connected to the first biasing terminal and a second conduction region connected to the second biasing terminal; a pass transistor, having a first conduction region connected to the input terminal and a second conduction region connected to the output terminal; and a common floating gate region and a common control gate region, which are capacitively coupled together. The memory element and the pass transistor share the common-gate regions, and the common control gate region is connected to the selection terminal.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: N-channel MOS transistors in a read gate circuit have respective sources connected to a sense amplifier activation line of a sense amplifier, not to a ground node. A read column selection line is selected prior to activation of the sense amplifier. Accordingly, paired read data lines are driven simultaneously with the activation of the sense amplifier.

Abstract: A semiconductor integrated circuit, comprising: a first output driving part which outputs a data signal in sync with a reference clock signal; a second output driving part which outputs a data strobe signal prescribing a timing of said data signal; and a driving control part which separately controls driving ability of said first and second output driving parts.

Abstract: A nonvolatile semiconductor memory with a plurality of banks in which copy back is performed between banks. An input circuit accepts input of a copy back command which requests a data transfer in the memory. When the copy back command is input from the input circuit, a judgment circuit judges whether a source and a destination are in the same bank. If the judgment circuit judges that the source and the destination are in the same bank, a first transfer circuit transfers data in the same bank. If the judgment circuit judges that the source and the destination are in different banks, a second transfer circuit transfers data between the two different banks.

Abstract: A method of communicating between a memory and circuitry on an integrated circuit is disclosed. The method comprises converting a first input signal from the memory to a first differential output signal dependent upon the first input signal. The first input signal is a full swing signal. The first differential output signal is propagated to the circuitry using a pair of first signal lines. Finally, at the circuitry, the first differential output signal is converted into a first received signal, which is a full swing signal.

Abstract: N-channel MOS transistors in a read gate circuit have respective sources connected to a sense amplifier activation line of a sense amplifier, not to a ground node. A read column selection line is selected prior to activation of the sense amplifier. Accordingly, paired read data lines are driven simultaneously with the activation of the sense amplifier.

Abstract: A memory controller initiates a first memory access in response to receipt of a first memory access request. The memory controller receives a second memory access request and initiates a second memory access in response to receipt of the second memory request prior to completing the first memory access.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: Systems and methods provide common mode termination for input/output circuits. For example, common mode termination may be provided to a bank of input/output circuits by programmably coupling a bus to each pair of input/output circuits. The bus provides a path to ground for common mode signals through a capacitor or, alternatively, the bus may be designed to provide or assist in providing the necessary capacitance.