Abstract: Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.

Abstract: Correction of duty cycle distortion of DQ and DQS signals between a memory controller and a memory is corrected by determining a duty cycle correction factor. The duty cycle distortion is corrected by applying the duty cycle correction factor to the plurality of differential DQS signals. The duty cycle distortion is corrected across a plurality of differential DQS signals between the memory controller and the bursting memory.

Abstract: A memory chip includes a plurality of storage elements. A method of controlling the memory chip includes receiving a plurality of target values from a memory controller. Each target value of the plurality of target values received from the memory controller corresponds to a respective one of the plurality of storage elements. The method further includes, for each storage element of the plurality of storage elements, adjusting a measurable parameter of the storage element until the measurable parameter of the storage element reaches the target value corresponding to the storage element received from the memory controller.

Abstract: An on-die termination (ODT) circuit of a memory device comprising: a memory device having a memory core having a memory cell array; a data input/output pin connected to the memory core through a data buffer; and an on-die termination (ODT) circuit, comprising: a termination circuit configured to provide a termination impedance at the input/output data pin, the termination circuit having a switching device that selectively connects a termination impedance to the input/output data pin based on the presence of an asynchronous control signal (ACS), wherein the ACS is generated based on the presence of a memory WRITE command.

Abstract: An integrated circuit device can include a plurality of test elements, each comprising at least one first switch coupled between a node within a tested section and an intermediate node, a test switch coupled between the intermediate node and a forced voltage node, and a second switch coupled between the intermediate node and an output node; wherein the forced voltage node is coupled to receive a forced voltage substantially the same as a test voltage applied to the output node in a test mode.

Abstract: A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of each of the words. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data has a large number of words transmitted from one circuit to another circuit over a wide parallel bus.

Abstract: A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.

Abstract: A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

Abstract: The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. The interface chip receives address information to specify memory cells and commonly supplies a part of the address information as chip selection information for comparison with the chip identification information to the plural core chips. As a result, since the controller recognizes that an address space is simply enlarged, the same interface as that in the semiconductor memory device according to the related art can be used.

Abstract: A memory module comprises a plurality of semiconductor memory devices each having a termination circuit for a command/address bus. The semiconductor memory devices are formed in a substrate of the memory module, and they operate in response to a command/address signal, a data signal, and a termination resistance control signal.

Abstract: A memory device including variable resistance elements comprises a plurality of memory cells configured to store data; a first signal transmission/reception unit and a second signal transmission/reception unit configured to transmit a signal to the memory cells or receive a signal from the memory cells; a first transmission line arranged to couple first ends of the memory cells to the first signal transmission/reception unit; and a second transmission line configured to couple second ends of the memory cells to the second signal transmission/reception unit, wherein a first resistance of a first signal path coupled between the first and second signal transmission/reception units through a first memory cell of the memory cells is substantially equal to a second electrical resistance of a second signal path coupled between a second memory cell and the first and second signal transmission/reception units through a second memory cell of the memory cells.

Abstract: A memory module includes a command/address (CA) register, memory devices, and a module resistor unit mounted on a circuit board. The centrally disposed CA register drive the memory devices one or more internal CA signal(s) to arrangements of memory devices using multiple CA transmission lines, wherein the multiple internal CA transmission lines are commonly terminated in the module resistor unit.

Abstract: An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to the external pin. The termination control unit varies the termination impedance in response to a plurality of bits of strength code associated with a data rate.

Abstract: A data processing system includes a first semiconductor device that has a plurality of blocks each including plural data, and a second semiconductor device that has a first control circuit controlling the first semiconductor device, and the first control circuit issues a plurality of commands to communicate with the first semiconductor device in units of access units including a plurality of first definitions that define a plurality of burst lengths indicating numbers of different data, respectively, and a plurality of second definitions that define correspondences between certain elements of data among the plural data included in the blocks, respectively, and arrangement orders in the numbers of different data that constitute the burst lengths, respectively, and communicates with the first semiconductor device through the plural data in the numbers of different data according to the first and second definitions.

Abstract: A nonvolatile memory device includes: a data transmission line configured to transmit internal configuration data; a data path control unit configured to control a data transmission path direction of the data transmission line according to control of a test signal; and a configuration data latch unit configured to latch a signal transmitted through the data transmission line or drive a latched signal to the data transmission line, according to control of the test signal.

Abstract: A data input circuit includes a valid strobe signal generation circuit and a data strobe signal counter. The valid strobe signal generation circuit is configured to remove a pulse of an internal strobe signal generated and generate a valid strobe signal. The pulse may have been generated during a preamble period. The data strobe signal counter is configured to count the valid strobe signal according to burst length information and generate a write latch signal for aligning data at a time of a write operation.

Abstract: A memory device including variable resistance elements comprises a plurality of memory cells configured to store data; a first signal transmission/reception unit and a second signal transmission/reception unit configured to transmit a signal to the memory cells or receive a signal from the memory cells; a first transmission line arranged to couple first ends of the memory cells to the first signal transmission/reception unit; and a second transmission line configured to couple second ends of the memory cells to the second signal transmission/reception unit, wherein a first resistance of a first signal path coupled between the first and second signal transmission/reception units through a first memory cell of the memory cells is substantially equal to a second electrical resistance of a second signal path coupled between a second memory cell and the first and second signal transmission/reception units through a second memory cell of the memory cells.

Abstract: A semiconductor memory device includes a pattern data generator configured to generate certain pattern data in a training operation mode, and an output driver configured to drive the pattern data to output training data with a slew rate corresponding to an external command in the training operation mode.

Abstract: A memory chip including a plurality of storage elements, a receiver and a program module. Each of the storage elements has a measurable parameter. The receiver receives N target values from a memory controller, where N is an integer greater than zero. The programming module adjusts corresponding measurable parameters of N storage elements of the plurality of storage elements to the N target values.

Abstract: A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.

Abstract: A repair circuit of a semiconductor apparatus includes a transmission control unit configured to generate first through nth (n is an integer equal to or greater than 2) control signals in response to a repair information signal, and enable all mth through nth control signals when the repair information signal indicating an mth (m is an integer equal to or greater than 1 and equal to or less than n) TSV is inputted; transmission units configured to allocate transmission paths for first through nth signals to first through nth TSVs and a repair TSV in response to the first through nth control signals; and receiving units configured to receive the signals transmitted from the first through nth TSVs and the repair TSV in response to the first through nth control signals.

Abstract: A memory system having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data, associated with a write command, to the first memory device, and a second signal line coupled to the second memory device to provide second data, associated with the write command, to the second memory device. A control signal path is coupled to the first and second memory devices and the termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component. A third signal line is provided to convey a clock signal that indicates when the write command propagating on the control signal path is to be sampled by the first and second memory devices.

Abstract: A semiconductor memory device having a multi-chip package structure providing active termination control. The semiconductor memory device includes first and second memory chips sharing a data I/O bus. The first memory chip includes a first chip enable (CE) port determining whether the first memory chip is activated, and a second CE port monitoring whether the second memory chip is activated. An active termination unit is turned ON only when the first and second chips are deactivated.

Abstract: A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines.

Abstract: A data output circuit of a semiconductor memory device includes a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data, and an alignment control signal generating unit configured to generate the plurality of alignment control signals in response to a burst-type information and a seed address group, wherein the alignment control signal generating unit generates the alignment control signals to swap data in a swap mode where the burst-type is a certain type and bits of the seed address group are certain values.

Abstract: A semiconductor memory includes a word line coupled to memory cells that transmits a word line signal; at least one word repeater circuit that includes a first load circuit disposed on the word line; a first dummy word line disposed along the word line that transmits a first dummy word line signal; at least one dummy repeater circuit that includes a second load circuit disposed on the first dummy word line; bit lines coupled to the memory cells; column switches that couple the bit lines to data lines, respectively; a column selection line disposed along the word line that transmits a column selection signal for controlling each column switch; and at least one column repeater circuit disposed on the column selection line that outputs the column selection signal in synchronization with the first dummy word line signal input to the first dummy repeater circuit.

Abstract: Embodiments of the present invention provide impedance matching between a Field Programmable Gate Array (FPGA) and memory modules in a semiconductor storage device (SSD) system architecture. Specifically, a set (at least one) of memory modules is coupled to an FPGA. A damping resistor is placed at the impedance mismatching point to reduce signal noise.

Abstract: An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module may include a first memory having a first ODT circuit to receive the first ODT signal, and a second memory having a second ODT circuit to receive the first ODT signal. The first ODT signal may disable the ODT circuit of the first memory when the first memory is to be ACTIVE.

Abstract: A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology.

Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.

Abstract: A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.

Abstract: A data transmission circuit includes: a driving voltage generation unit configured to generate a driving voltage having a lower level than an external driving voltage; a switch unit configured to transmit the driving voltage when any one of a write enable signal and a read enable signal is enabled; and a data transmission unit configured to be driven by receiving the driving voltage, transmit a signal of a DQ pad as data in response to the write enable signal, and transmit the data to the DQ pad in response to the read enable signal.

Abstract: A microelectronic assembly can include first and second microelectronic packages mounted to opposed surfaces of a circuit panel. Each package can include a substrate having first, second, and third apertures extending therethrough, first, second, and third microelectronic elements each having a surface facing the first surface of the substrate and a plurality of contacts aligned with at least one of the apertures, a plurality of terminals exposed at the second surface in a central region thereof, and leads connected between the contacts of each microelectronic element and the terminals. The apertures of each substrate can have first, second, and third axes extending in directions of their lengths. The first and second axes can be parallel to one another. The third axis can be transverse to the first and second axes. The terminals of each package can be configured to carry all of the address signals transferred to the respective package.

Abstract: A system, method, and computer program product are provided for driving a memory circuit. In one embodiment, the memory circuit is driven utilizing a first resistance value in a first mode of operation. Further, in a second mode of operation, the memory circuit is driven utilizing a second resistance value. In another embodiment, a device is provided for driving a memory circuit without active termination utilizing a resistor.

Abstract: Semiconductor memory device for high-speed data input/output includes a first serializer configured to partially serialize input 8-bit parallel data to output first to fourth serial data, a second serializer configured to partially serialize the first to fourth serial data to output fifth and sixth serial data and a third serializer configured to serialize the fifth and sixth serial data to output seventh serial data.

Abstract: An image forming apparatus includes an image receiving unit configured to receive image data, a sender identifying unit configured to identify a sender of the received image data, a check unit configured to check whether the identified sender corresponds to a predetermined sender, a management information providing unit configured to provide management-purpose image data obtained by encoding management information for controlling at least one of a transmission operation for transmitting an image scanned from a printout and a copy operation for copying an image scanned from a printout, and a print unit configured to print the management-purpose image data together with the received image data in response to a check result by the check unit indicating that the identified sender corresponds to the predetermined sender.

Abstract: Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.

Abstract: A data driver is presented in which the data driver includes a termination/pull-up driver and a pull-down driver. The termination/pull-up driver is configured to perform a termination operation and a pull-up operation at the same time for a data output terminal during an active interval of a semiconductor memory. The pull-down driver is configured to be activated when the semiconductor memory performs a read operation, and configured to pull down the output terminal in response to a level of an input data.

Abstract: A method for initializing a memory device is provided. The method includes a step for transmitting at least N+1 clock cycles to the memory device, wherein the N is an amount of bits of output serial data of the memory device. During a clock cycle of the at least N+1 clock cycles, a first start/stop signal is transmitted to the memory device. During another clock cycle of the at least N+1 clock cycles, a second start/stop signal is transmitted to the memory device.

Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Abstract: A skew detection circuit includes a data sensing block configured to sense a first data that is transferred earliest and a last data that is transferred latest among a plurality of data which are transferred through different transfer paths, and generate a sensing result signal; and a detection signal generation block configured to compare an output signal of the data sensing block with a certain time, and generate a skew detection signal.

Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.

Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

Abstract: A semiconductor apparatus includes a memory array configured to store write data transmitted through data transmission lines and transmit stored data to the data transmission line as read data; a data write unit configured to drive the write data to the data transmission lines in response to a data write command; and a data read unit configured to sense the read data transmitted through the data transmission lines in response to a data read command when a data verification signal is deactivated and sense the write data transmitted through the data transmission lines in response to the data write command when the data verification signal is activated.

Abstract: A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology.

Abstract: A semiconductor memory chip includes: a driving voltage reception unit configured to receive a power supply voltage and a ground voltage; a first data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive first data to output the driven first data through a first data line; a second data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive second data to output the driven second data through a second data line; and a MOS transistor coupled between the first data line and the second data line.

Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Abstract: A memory device is connected through an interface to a memory controller. The controller's reference voltage is set based on a driver's impendence of the memory device during driver training. The voltage is applied to a reference resistor pair at the controller and changed until the voltage level switches. The voltage is then set at the reference resistor pair of the controller.

Abstract: A semiconductor device comprises transmission lines, inverting circuits, first, second and third switches, global sense amplifiers, and a control circuit. The first switch switches between the transmission line and the input of the inverting circuit, the second switch switches between the transmission line and the output of the transmission line, and the third switch switches between the adjacent transmission lines. The control circuit turns off the first and second switches so that the transmission lines are brought into a floating state in a state where signals of the transmission lines are held in the inverting circuits by the global sense amplifiers. After charge sharing of the transmission lines occurs by turning on the third switches within a predetermined period, the control circuit turns off the second switches so that the transmission lines are inverted and driven via the inverting circuits and the second switches.

Abstract: A semiconductor memory module (1) includes a circuit substrate (2), a first (100), a second (200), a third (300) and a fourth (400) rank of memory chips (3), a first register (10) and a second register (20). The first register (10) and the second register (20) each comprise a first input (11, 21) for receiving a respective chip select signal (CS0, CS2), a second input (12, 22) for receiving a respective other chip select signal (CS1, CS3) at least one third input (13, 23) for receiving command/address signals (CA), and at least one third output (16, 26).