Abstract: Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer.

Abstract: Resistance memory device and apparatus, a fabrication method thereof, an operation method thereof, and a system including the same are provided. The resistance memory device may include a data storage unit and a first interconnection connected to the data storage unit. A first access device may be connected in series with the data storage unit and a second access device may be connected in series with the first access device. A second interconnection may be connected to the second access device. A third interconnection may be connected to the first access device to drive the first access device and a fourth interconnection connected to the second access device to drive the second access device.

Abstract: A method is provided for fabricating stripe structures. The method includes providing a substrate; and forming a to-be-etched layer on the substrate. The method also includes forming a hard mask pattern having a first stripe on the to-be-etched layer; and forming a photoresist pattern having a stripe opening on the to-be-etched layer and the hard mask pattern having the first stripe. Further, the method includes forming a polymer layer on a top surface and side surfaces of the photoresist pattern to reduce a width of the stripe opening; forming hard mask patterns having a second stripe by etching the hard mask pattern having the first stripe using the photoresist pattern having the polymer layer as an etching mask; and forming the stripe structures by etching the to-be-etching layer using the hard mask pattern having the second stripe as an etching mask until the substrate is exposed.

Abstract: Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array.

Abstract: A method for implementing a system containing at least one memory device including a plurality of non-volatile memory cells each including a phase-change material configured to change state reversibly between at least an amorphous state and a crystalline state having different electrical resistances. The method includes steps of manufacturing the memory cells, including the formation of a layer of a phase-change material having an original amorphous state at the end of the steps of manufacturing the memory cells. The method for implementing the embedded system includes, after the steps of manufacturing the memory cells, at least the following steps: (i) pre-programming the memory device consisting of an electrical recrystallization of a selection of memory cells from their original amorphous state; and (ii) assembling the pre-programmed memory device in the system during which the device is subjected to a temperature of between 240° C. and 300° C.

Abstract: A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.

Abstract: A switching element for resistive-switching memory (ReRAM) provides a controllable, consistent filament break-point at an abrupt structural discontinuity between a layer of high-k high-ionicity variable-resistance (VR) material and a layer of low-k low-ionicity VR material. The high-ionicity layer may be crystalline and the low-ionicity layer may be amorphous. The consistent break-point and characteristics of the low-ionicity layer facilitate lower-power operation. The defects (e.g., oxygen or nitrogen vacancies) that constitute the filament originate either in the high-ionicity VR layer or in a source electrode. The electrode nearest to the low-ionicity layer may be intrinsically inert or may be rendered effectively inert. Some electrodes are rendered effectively inert by the creation of the low-ionicity layer over the electrode.

Abstract: A semiconductor structure comprising a fuse/resistor structure over a functional layer having a substrate. The fuse/resistor structure includes a via, a first interconnect layer, and a second interconnect layer. The via is over the functional layer and has a first end and a second end vertically opposite the first end, wherein the first end is bounded by a first edge and a second edge opposite the first edge and the second end is bounded by a third edge and a fourth edge opposite the third edge. The first interconnect layer includes a first metal layer running horizontally and contacting the first end and completely extending from the first edge to the second edge. The second interconnect layer includes a second metal layer running horizontally and contacting the second end of the via and extending past the third edge but reaching less than half way to the fourth edge.

Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a first insulating layer formed on a semiconductor substrate, the first insulating layer having a first hole formed therein. A switching device is formed in the first hole. A second insulating layer is formed over the first insulating layer and the second insulating layer includes a second hole. A lower electrode is formed along a surface of the second insulating layer that defines the second hole. A spacer is formed on the lower electrode and exposes a portion of the surface of the lower electrode. A variable resistance material layer is formed in the second hole, and an upper electrode is formed on the variable resistance material layer.

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and a resistive switching layer connected in series with this resistor. The resistor is configured to prevent over-programming of the cell by limiting electrical currents through the resistive switching layer. Unlike the resistive switching layer, which changes its resistance in order to store data, the embedded resistor maintains a substantially constant resistance during operation of the cell. The embedded resistor is formed from tantalum nitride and silicon nitride. The atomic ratio of tantalum and silicon may be specifically selected to yield resistors with desired densities and resistivities as well as ability to remain amorphous when subjected to various annealing conditions. The embedded resistor may also function as a diffusion barrier layer and prevent migration of components between one of the electrodes and the resistive switching layer.

Abstract: The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (114) an electrically insulating first cover layer (120) which partly or fully covers the top capacitor electrode (118) and is made of a lead-containing dielectric material, and a top barrier layer (122) on the first cover layer. The top barrier layer serves for avoiding a reduction of lead atoms comprised by the first cover layer under exposure of the first cover layer to a reducing substance. An electrically insulating second cover layer (124) on the top barrier layer has a dielectric permittivity smaller than that of the first cover layer establishes a low parasitic capacitance of the cover-layer structure. The described cover-layer structure with the intermediate top barrier layer allows to fabricate a high-accuracy resistor layer (126.1) on top.

Abstract: A method of manufacturing a nonvolatile memory device that is a variable resistance nonvolatile memory device, which has good consistency with a dual damascene process that is suitable for the formation of fine copper lines and which enables large capacity and high integration. This method includes: forming a variable resistance element, a contact hole and a line groove; and forming a current steering layer of a bidirectional diode element above interlayer insulating layers and a variable resistance layer to cover the line groove without covering a bottom surface of the contact hole.

Abstract: Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel oxide that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device.

Abstract: A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.

Abstract: The present disclosure includes memory cell structures and method of forming the same. One such method includes forming a memory cell includes forming, in a first direction, a select device stack including a select device formed between a first electrode and a second electrode; forming, in a second direction, a plurality of sacrificial material lines over the select device stack to form a via; forming a programmable material stack within the via; and removing the plurality of sacrificial material lines and etching through a portion of the select device stack to isolate the select device.

Abstract: Films having a comb-like structure of nanocolumns of Sm2O3 embedded in a SrTiO3 formed spontaneously on a substrate surface by pulsed laser deposition. In an embodiment, the nanocolumns had a width of about 20 nm with spaces between nanocolumns of about 10 nm. The films exhibited memristive behavior, and were extremely uniform and tunable. Oxygen deficiencies were located at vertical interfaces between the nanocolumns and the matrix. The substrates may be single-layered or multilayered.

Abstract: Microelectronic device, comprising a substrate, a first electrode arranged above the substrate, a first resistive switch and a resistivity structure coupled with each other, wherein the first resistive switch and the resistivity structure are arranged in a single layer of the device, and a second electrode arranged above the layer that includes the first resistive switch and the resistivity structure, wherein the first resistive switch and the resistivity structure are coupled with the first and the second electrode.

Abstract: A memristor with a channel region in thermal equilibrium with a containing region. The channel region has a variable concentration of mobile ions. The containing region, formed of stoichiometric crystalline material, contains and is in thermal equilibrium with the channel region.

Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

Abstract: In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.

Abstract: Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode and a resistance change film. The resistance change film is connected between the first electrode and the second electrode. An ion metal is introduced in a matrix material in the resistance change film. A concentration of the ion metal in a first region on the first electrode side of the resistance change film is higher than a concentration of the ion metal in a second region on the second electrode side of the resistance change film A layer made of only the ion metal is not provided in the memory device.

Abstract: A phase-change memory device is provided. The memory device includes a lower electrode, a phase-change material layer formed on the lower electrode, an upper electrode formed on the phase-change material layer, and a stress insulation film formed to surround the phase-change material layer.

Abstract: A nonvolatile resistive switching memory (ReRAM) device having no selection device is provided. The ReRAM device includes a lower electrode that is formed on on a substrate; a metal oxide layer that is formed on the lower electrode, the metal oxide layer having a resistive switching characteristic; an upper electrode that is formed on the metal oxide layer; and a tunnel barrier oxide film that is formed between the lower electrode and the metal oxide layer, thereby forming a double oxide film structure, the tunnel barrier oxide film being made of a material, a band energy gap and a conduction band offset of which are lower than those of the metal oxide layer, and which does not cause interface switching.

Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.

Abstract: Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

Abstract: A memristor based on mixed-metal-valence compounds comprises: a first electrode; a second electrode; a layer of a mixed-metal-valence phase in physical contact with at least one layer of a fully oxidized phase. The mixed-metal-valence phase is essentially a condensed phase of dopants for the fully oxidized phase that drift into and out of the fully oxidized phase in response to an applied electric field. One of the first and second electrodes is in electrical contact with either the layer of the mixed-metal-valence phase or a layer of a fully oxidized phase and the other is in electrical contact with the layer (or other layer) of the fully oxidized phase. The memristor is prepared by forming in either order the layer of the mixed-metal-valence phase and the layer of the fully oxidized phase, one on the other. A reversible diode and an ON-switched diode are also provided. A method of operating the memristor is further provided.

Abstract: Provided is a method for manufacturing a variable resistance nonvolatile semiconductor memory element, and a nonvolatile semiconductor memory element which make it possible to operate at a low voltage and high speed when initial breakdown is caused, and exhibit favorable diode element characteristics. The method for manufacturing the nonvolatile semiconductor memory element includes, after forming a top electrode of a variable resistance element and at least before forming a top electrode of an MSM diode element, oxidizing to insulate a portion of a variable resistance film in a region around an end face of a variable resistance layer.

Abstract: A method of depositing a silver layer includes forming a plurality of openings in a dielectric layer to expose a top surface of a structure comprising a resistive memory layer on top of a p-doped silicon-containing layer on top of a conductive structure, depositing a first metal layer comprising a tungsten layer overlying the top surface of the structure, wherein a first metal material of the first metal layer contacts a resistive memory material of the resistive memory layer and exposing the first metal layer in a bath comprising a solution of silver species having an alkaline pH for a predetermined time to form a silver metal layer from the silver species from the solution overlying the resistive memory material, wherein the silver species is reduced by the first metal material, and wherein the first metal material is solubilized while forming the silver metal layer.

Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can be grown on the silicon bearing layer, and the growth of the interface layer can be regulated with N2O plasma.

Abstract: A semiconductor device includes: a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening.

Abstract: A memory device includes a stack of layers comprising a plurality of alternating layers of continuous electrically conductive material word line layers with layers of continuous electrically insulating material. A plurality of vias vertically extend through the stack of layers and a vertical bit line is disposed within each via. A layer of switching material separates the vertical bit line from the stack of layers, thereby forming an array of RRAM cells.

Abstract: An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.

Abstract: Systems and methods are disclosed to form a resistive random access memory (RRAM) by forming a first metal electrode layer; depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions; depositing a Pr1-X CaXMnO3 (PCMO) layer above the insulator and the metal portions, wherein X is between approximately 0.3 and approximately 0.5, to form one or more self-aligned RRAM cells above the first metal electrode; and depositing a second metal electrode layer above the PCMO layer.

Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.

Abstract: A method for forming a silver structure for a non-volatile memory device includes providing a silver layer material upon a underlying substrate, forming a diffusion barrier material overlying the silver layer material, forming a dielectric hard mask material overlying the diffusion barrier material, subjecting the dielectric hard mask material to a patterning and etching process to form a hard mask and to expose a portion of the diffusion barrier material, subjecting the portion of the diffusion barrier material to an etching process using one or more chlorine bearing species as an etchant material, wherein one or more chloride contaminant species is formed overlying at least a portion of the silver layer material, and reacting the one or more chloride contaminant species with a solution comprising an ammonia species to form a water soluble species, wherein the ammonia species is free from an oxidizing species.

Abstract: A variable resistance memory device includes: a pair of first electrodes and a second electrode interposed between the pair of first electrodes; a first variable resistance material layer interposed between one of the first electrodes and the second electrode; and a second variable resistance material layer interposed between the other of the first electrodes and the second electrode, wherein the pair of first electrodes are electrically connected to each other, and a first set voltage and a first reset voltage of the first variable resistance material layer are different from a second set voltage and a second reset voltage of the second variable resistance material layer, respectively.

Abstract: Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material.

Abstract: According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.

Abstract: A semiconductor memory device according to an embodiment has a memory cell array including: a plurality of lower wirings extending in the first direction; a plurality of upper wirings extending in the second direction, the upper wirings placed above the plurality of lower wirings; a plurality of memory cells provided at respective crossings of the plurality of lower wirings and the plurality of upper wirings; and an interlayer insulating film provided between the plurality of memory cells adjacent in the second direction, and the device is characterized in that the upper wiring includes: an upper firing first section deposited on the memory cell; and an upper wiring second section deposited on the interlayer insulating film, the upper wiring second section larger in crystal grain size than the upper wiring first section, and an upper surface of the memory cell is lower than an upper surface of the interlayer insulating film.

Abstract: The present invention is a method for forming a vertically oriented element having a narrower area near its center away from either end. The present invention will find applicability in other memory cell structures. The element will have a narrow portion towards its center such that current density will be higher away from the ends of the element. In this way, the heating will occur away from the ends of the storage element. Heating in a phase-change or resistive change element leads to end of life conditions, including the condition whereby contaminants from the end point contacts are enabled to migrate away from the end point and into the storage element thereby contaminating the storage element material and reducing its ability to be programmed, erased and/or read back.

Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

Abstract: A variable resistance memory device that includes a first electrode, a second electrode, a variable resistance layer interposed between the first electrode and a second electrode. A metal oxide electrode is interposed between the first electrode and the variable resistance layer, and the metal oxide electrode does not include a nitrogen constituent.

Abstract: Various embodiments of the present invention are direct to nanoscale, reconfigurable, memristor devices. In one aspect, a memristor device comprises an electrode (301,303) and an alloy electrode (502,602). The device also includes an active region (510,610) sandwiched between the electrode and the alloy electrode. The alloy electrode forms dopants in a sub-region of the active region adjacent to the alloy electrode. The active region can be operated by selectively positioning the dopants within the active region to control the flow of charge carriers between the electrode and the alloy electrode.

Abstract: A nonvolatile resistive memory element includes one or more novel oxygen isolation structures that protect the resistive switching material of the memory element from oxygen migration. One such oxygen isolation structure comprises an oxygen barrier layer that isolates the resistive switching material from other portions of the resistive memory device during fabrication and/or operation of the memory device. Another such oxygen isolation structure comprises a sacrificial layer that reacts with unwanted oxygen migrating toward the resistive switching material during fabrication and/or operation of the memory device.

Abstract: A nonvolatile resistive memory element includes a novel switching layer and methods of forming the same. The switching layer includes a material having bistable resistance properties and formed by bonding silicon to oxygen or nitrogen. The switching layer may include at least one of SiOx, SiOxNy, or SiNx. Advantageously, the SiOx, SiOxNy, and SiNx generally remain amorphous after thermal anneal processes are used to form the devices, such as ReRAM devices.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.

Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a bottom structure including a heating electrode, data storage materials, each of the data storage materials formed on the bottom structure in a confined structure perpendicular to the bottom structure, and having a lower diameter smaller than an upper diameter, an upper electrode formed on each of the data storage materials, and an insulation unit formed between adjacent data storage materials.

Abstract: Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a transitory structure which alters resistance through the memory cell. The data storage region includes two or more portions, with one of the portions supporting a higher resistance segment of the transitory structure than another of the portions. Some embodiments include a method of forming a memory cell. First oxide and second oxide regions are formed between a pair of conductive structures. The oxide regions are configured to support a transitory structure which alters resistance through the memory cell. The oxide regions are different from one another so that one of the oxide regions supports a higher resistance segment of the transitory structure than the other.