Abstract: A method for making a device is disclosed. One embodiment provides a substrate having a first element protruding from the substrate. A semiconductor chip has a first electrode on a first surface and a second electrode on a second surface opposite to the first surface. The semiconductor chip is placed over the first element of the substrate with the first surface of the semiconductor chip facing the substrate. The second electrode of the semiconductor chip is electrically coupled to the substrate, and the substrate is at least partially removed.

Abstract: A method of making a microelectronic assembly includes providing a conductive metal layer having a first surface and a second surface, and etching the first surface of the conductive metal layer to form conductive protrusions, whereby after the etching step, the second surface of the conductive metal layer defines a substantially flat, continuous surface. The method includes juxtaposing a layer of an insulating material with tips of the conductive protrusions, and pressing the conductive protrusions through the layer of an insulating material so that the tips of the conductive protrusions are accessible at a first surface of the layer of an insulating material.

Abstract: The method mainly contains the following steps. First, an UBM is formed on a top side of a semiconductor's I/O pad. An isolative layer and a metallic foil are sequentially arranged in this order on the UBM. Then, a via is formed to expose the top surface of the UBM. Subsequently, a thin metallic layer is formed in the via and a resist is formed on the metallic foil. Then, by using the metallic foil and the thin metallic layer as an electrode to conduct electrical current, a metallic bump is formed using electroplating in the via on the top side of the UBM. Finally, the resist and the metallic foil are removed and the formation of the metallic bump is completed. Optionally coating on bump may be needed for certain chosen bump materials.

Abstract: The method mainly contains the following steps. First, an UBM is formed on a top side of a semiconductor's I/O pad. An isolative layer and a metallic foil are sequentially arranged in this order on the UBM. Then, a via is formed to expose the top surface of the UBM. Subsequently, a thin metallic layer is formed in the via and a resist is formed on the metallic foil. Then, by using the metallic foil and the thin metallic layer as an electrode to conduct electrical current, a metallic bump is formed using electroplating in the via on the top side of the UBM. Finally, the resist and the metallic foil are removed and the formation of the metallic bump is completed.

Abstract: A method is provided for the making of interconnect solder bumps on a wafer or other electronic device. The method is particularly useful for the well-known C4NP interconnect technology and determines if any off-set resulted between the solder mold array and the wafer capture array during the transfer process. The amount of off-set enables the operator to adjust the transfer tool before solder transfer to compensate for the off-set caused by the transfer process and provides a more cost-effective and efficient solder transfer process. A solder reactive material surrounding the capture pads is used to determine where the solder reacts with the solder reactive material showing the off-set resulting from the transfer process. Copper is a preferred solder reactive material.

Abstract: A method for bonding a semiconductor device onto a substrate is provided which comprises the steps of picking up a solder ball with a pick head, placing the solder ball onto the substrate and melting the solder ball on the substrate and placing the semiconductor device on the molten solder ball. The molten solder ball is then allowed to cool to form a solder joint which bonds the semiconductor device to the substrate.

Abstract: A method of manufacturing a wiring substrate comprises: a first step of forming, on a support plate, an electrode pad made of metal; a second step of etching the support plate in such a manner that the support plate has a shape which includes a projection portion to be contacted with the electrode pad; a third step of forming, on the surface of the support plate, an insulating layer for covering the electrode pad; a fourth step of forming, on the surface of the insulating layer, a conductive pattern to be connected to the electrode pad; and, a fifth step of removing the support plate.

Abstract: A method and apparatus for attaching a module such as a semiconductor device, having an array of contacts arranged thereon in a given pattern to a substrate such as a printed circuit board comprises applying an array of solder blocks to the array of contacts on the module. The module is then positioned on the substrate so that the array of solder blocks contacts the array of contact pads on the substrate. Heat is then applied to reflow the solder blocks to provide mechanical and electrical connection of the module to the substrate.

Abstract: A method of making a microelectronic element includes making a connection component by providing a metal layer having a top surface and a bottom surface, providing a dielectric layer over the top surface of the metal layer and forming openings in the dielectric layer to expose portions of the top surface of the metal layer. The method includes providing conductive elements atop the dielectric layer, at least some of the conductive elements extending through the openings in the dielectric layer and being in contact with the metal layer, and plating first conductive protrusions atop the at least some of the conductive elements extending through the openings in the dielectric layer, the first conductive protrusions extending away from the metal layer. The method includes selectively removing portions of the metal layer from the bottom surface of the metal layer to form second conductive protrusions that extend away from the first conductive protrusions.

Abstract: A method and apparatus for underfilling a gap between a semiconductor die or device and a substrate, where the semiconductor die or device is electrically connected to the substrate so that an active surface of the semiconductor die is facing a top surface of the substrate with the gap therebetween. A silane layer is applied to the active surface of the semiconductor die, the upper surface of the substrate, and/or both to increase the surface tension thereon. The increased surface tension thereby allows the underfill material to fill the gap via capillary action in a lesser flow time more effectively, and therefore, is more efficient than conventional underfilling methods.

Abstract: A method of manufacturing a substrate joint body by mounting a TFT on a wiring substrate includes a step of arranging an electrode pad of the wiring substrate and an electrode pad of the TFT at a predetermined interval and mechanically coupling the wiring substrate and the TFT with a adhesive and a step of electrically coupling the wiring substrate and the TFT by growing a bump from the electrode pad of the wiring substrate and/or the electrode pad of the TFT.

Abstract: An integrated circuit includes active circuitry and at least one bond pad. The at least one bond pad, in turn, comprises a metallization layer and a capping layer having one or more grooves. The metallization layer is in electrical contact with at least a portion of the active circuitry. In addition, the capping layer is formed over at least a portion of the metallization layer and is in electrical contact with the metallization layer. The grooves in the capping layer may be located only proximate to the edges of the bond pad or may run throughout the bond pad depending on the application.

Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up, wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.

Abstract: A method for fabricating a solder transfer mold includes masking a substrate with a masking agent. A pattern is transferred to the substrate mask. The masked substrate is etched until cavities of a first volume are formed. The cavities of the first volume are selectively coated. The masked substrate is etched until cavities of a second volume are formed.

Abstract: A method of forming a high aspect ratio metal plate pattern or circuit board by multi-stage etching with a metal mask is disclosed. A resist (12) is coated on one or two surfaces of a copper plate (10) and patterned into a resist pattern. A tin plating layer (14) is formed using this resist pattern, and with this tin plating layer as a mask, the copper plate is half etched. By coating, exposing and developing the positive resist (18), the positive resist under the tin plating layer is protected. With the tin plating layer and the protective resist layer as a mask, the half etching is executed again. This process is repeated until the resist and the tin plating layer used as a masking are finally removed to produce a metal pattern (20).

Abstract: The present invention relates to a donor laminate for transfer of a conductive layer comprising at least one electronically conductive polymer on to a receiver, wherein the receiver is a component of a device. The present invention also relates to methods pertinent to such transfers.

Abstract: Disclosed are an integrated circuit component capable of simply mounting at low cost a chip part which adjusts impedance of wiring patterns as well as capable of effectively reducing switching noise from an integrated circuit, and a method for mounting the chip part. The integrated circuit component of the present invention has a constitution that a bypass capacitor is mounted on a wiring board side of a gap between the wiring board and an LSI chip. Therefore, as compared with a case where the capacitor is mounted on the LSI chip side, a transmission path through the capacitor can be extremely shortened. As a result, inductance components of the feeder line can be reduced, so that a response delay of power transmitted through the feeder line can be sufficiently suppressed.

Abstract: A method of manufacturing a semiconductor device substrate includes the steps of: arranging on a base a temporary fixing member for temporarily fixing an electronic component; temporarily fixing the electronic component on the base by the temporary fixing member; forming a substrate body on the base and the electronic component; removing a portion of the base which portion corresponds to the electronic component, thereby exposing the temporary fixing member; and removing the temporary fixing member, thereby enabling the electronic component to make an external connection.

Abstract: An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Abstract: Disclosed is a new process that permits the transfer and reflow of solder features produced by Injection Molded Solder (IMS) from a mold plate to a solder receiving substrate without the use of flux. Several embodiments produce solder transfer and reflow separately or together and use either formic acid vapor or partial concentration of hydrogen, both in nitrogen, as the oxide reducing atmosphere. A final embodiment produces fluxless transfer and reflow in only nitrogen through the use of ultrasonic vibration between the solder filled mold plate and solder receiving substrate.

Abstract: A method is provided including, after joining a wiring substrate and an element substrate, separating a second substrate of the element substrate from a semiconductor element, and electrically coupling an element-side terminal that has been exposed by the separation to a wiring-side terminal disposed outside the semiconductor element by electroless plating.

Abstract: Balls are sucked onto a carrier board so as to be temporarily arranged in a ball arrangement region of the board, and then the balls are transferred and bonded onto an objective substance with their positions being adjusted. Gas blow is applied to the temporarily arranged balls or alternatively the temporarily arranged balls are sucked, so as to remove excess balls other than balls that have been exactly sucked onto the ball arrangement region. Cooperation with application of fine vibration to the carrier board makes the removal of the excess balls more efficient.

Abstract: Vias (210, 210B) are formed in a surface of a substrate. At least portions of contact pads (139, 350) are located in the vias. Contact pads (150, 340) of an integrated circuit structure are inserted into the vias and attached to the contact pads (139, 350) of the substrate. The vias provide a strong, reliable mechanical and electrical connection. A via may expose not only a contact pad (350) in the substrate but also a surrounding region. Solder (930) wets the contact pad better than the surrounding region, resulting in a stronger solder joint and better electrical conductivity. Alternatively, the contact may include multiple conductive layers (910.1, 910.2), with the top layer (910.2) being more solder wettable than the bottom layer (910.1) and the top layer covering only a portion of the bottom layer.

Abstract: A front-and-back electrically conductive substrate includes a plurality of posts composed of a material that can be anisotropically etched and having an electrically conductive portion that has at least a first surface and a second surface that communicate with each other, and an insulative substrate that supports the plurality of posts.

Abstract: The present invention relates to an integrated device comprising an electronic circuit chip, a solder contact structure to provide contact to the electronic circuit chip and an elastic contact structure to provide contact to the electronic circuit chip, wherein the solder contact structure and the elastic contact structure are arranged on a contacting surface of the integrated device.

Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.

Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.

Abstract: A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.

Abstract: A method is provided for manufacturing a multi-layer wiring circuit substrate. A first metal layer is selectively etched in first areas to reduce a thickness of the metal layer in the first areas and to form protrusions in other areas which extend above the etched areas. An interlayer-insulating layer is formed to overlie the etched areas of the first metal layer. The interlayer-insulating layer has an inner surface which confronts the etched first areas and an outer surface remote from the inner surface, such that the protrusions extend through the interlayer-insulating layer and have ends exposed at the outer surface. A second metal layer is then provided in conductive communication with the exposed ends of the protrusions, and the first and second metal layers are selectively patterned from surfaces remote from the interlayer-insulating layer.

Abstract: A new method is provided for the interconnection of flip chips to a supporting substrate. The invention starts with a conventional first substrate, that serves as a semiconductor device support structure, over the surface of which a first pattern of contacts points has been provided. The invention then uses a second substrate, for instance a glass or quartz plate, and creates over the surface thereof a second pattern of solder bumps separated by solder non-wettable surfaces. The second pattern is a mirror image of the first pattern. By then overlying the first pattern of contact points with the second pattern of solder bumps, a step of reflow can be applied to the solder bumps, transferring the solder bumps from the second substrate to the contact points provided over the first substrate.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.

Abstract: The specification describes a contact printing technique for forming patterns of thin films with nanometer resolution over large areas. The procedure, termed here “nanotransfer printing (nTP)”, relies on tailored surface chemistries for transferring thin films, typically metal films, from the raised regions of a stamp to a substrate when these two elements are brought into intimate physical contact. This technique is purely additive, it is fast (<15 s contact times), and the printing occurs in a single processing step at room temperature in open air. nTP is capable of producing patterns with a wide range of features with sizes down to ˜100 nm, and edge resolution better than 25 nm. Electrical contacts and interconnects have been fabricated for high performance organic thin film transistors (TFTs) and complementary inverter circuits, to demonstrate one of the many potential applications for nTP.

Abstract: A no-flow underfill material and process suitable for underfilling a bumped circuit component. The underfill material initially comprises a dielectric polymer material in which is dispersed a precursor capable of reacting to form an inorganic filler. The underfill process generally entails dispensing the underfill material over terminals on a substrate, and then placing the component on the substrate so that the underfill material is penetrated by the bumps on the component and the bumps contact the terminals on the substrate. The bumps are then reflowed to form solid electrical interconnects that are encapsulated by the resulting underfill layer. The precursor may be reacted to form the inorganic filler either during or after reflow.

Abstract: The method for producing a solder bump transfer sheet of the invention includes the steps of: providing a sheet having a chromium oxide layer containing substantially no iron oxide as the outermost surface; and forming a plurality of solder bumps placed in a predetermined pattern on the chromium oxide layer.

Abstract: A plurality of bumps is formed on a substrate. At first, a hole having a bottom is formed in a sheet, and the hole is filled with a metallic paste. Then, the sheet is stacked and positioned on the substrate so that the hole of the sheet faces an electrode of the substrate. The substrate with the sheet is heated and pressurized so that the metallic paste is sintered and bonded to the electrode so as to form the bump. Then, the sheet is separated from the substrate having the bump, so that the bump is formed on the substrate. A part of each bump does not lack, and all of the bumps are formed surely. Therefore, the bump can be formed uniformly.

Abstract: Balls are sucked onto a carrier board so as to be temporarily arranged in a ball arrangement region of the board, and then the balls are transferred and bonded onto an objective substance with their positions being adjusted. Gas blow is applied to the temporarily arranged balls or alternatively the temporarily arranged balls are sucked, so as to remove excess balls other than balls that have been exactly sucked onto the ball arrangement region. Cooperation with application of fine vibration to the carrier board makes the removal of the excess balls more efficient.

Abstract: A semiconductor device is manufactured by forming a first insulating layer on a semiconductor substrate. First contact pads and second contact pads are formed that penetrate through the first insulating layer and are electrically connected to the semiconductor substrate. A second insulating layer is formed that has guide contact holes that expose upper surfaces of the first contact pads. An etch stopper is formed on bottoms and sidewalls of the guide contact holes of the second insulating layer. Bit lines are formed that are electrically connected to the semiconductor substrate by the second contact pads. The bit lines are electrically isolated from the first contact pads.

Abstract: A conductive pattern is obtained by forming concave-convex on a substrate by using a pattern substrate. A conductive thin layer is formed and then coated with a layer of a photosensitive resin. The photo sensitive resin is exposed and development by using the pattern substrate to bare the conductive thin layer on the convex portion and electrolytic plating. The conductive thin layer and the layer of the photosensitive resin on the concave portion may then be removed.

Abstract: A system may direct first energy to only a first interconnect element, the first interconnect element contacting a first conductive contact of a first device and a second conductive contact of a second device. A first electrical connection may be formed between the first conductive contact and the second conductive contact based at least in part on the first energy. Further, second energy may be directed to only a second interconnect element, the second interconnect element contacting a third conductive contact of the first device and a fourth conductive contact of the second device. A second electrical connection may be formed between the third conductive contact and the fourth conductive contact based at least in part on the second energy.

Abstract: The present invention provides for a method of interconnecting a bumped circuit having relatively fine traces to an overlying conductive layer of a laminated circuit assembly. The overlying conductive layer is laminated with a suitable insulating adhesive over a bumped relatively fine pitch circuit layer. In the general vicinity of the desired power connection, a window substantially larger than the width of the bump is etched away from the conductive material of the trace of the outer conductive layer and the adhesive is plasma etched to expose the elevated portion of the desired bump of the bumped circuit. A conductive media such as conductive polymer or solder is then applied at the etched window of the overlying relatively coarse trace, which ensures an electrical connection between the exposed portion of the bump and the overlying trace.

Abstract: A system for attaching a plurality of solder balls to an electronic device is disclosed. The system includes, in one embodiment, a heat-resistant tape having a first side comprising a plurality of recesses. The first side of the tape may form an adhesive surface. The recesses are located for registration with a plurality of connection points on the electronic device. The recesses are each adapted to receive and retain a solder ball therein. After placing a solder ball within two or more of the recesses, the first side of the tape may be adhered to the electronic device with the solder balls retained therein. Heating of the solder balls causes them to reflow and adhere to the connection points. After cooling, the tape may be removed, wherein the solder balls remain bonded to the connection points, forming a Ball Grid Array (BGA).

Abstract: The invention provides a transfer technique by which the dimensional precision of a thin-film device is not deteriorated, even if the device is produced by transferring a fine structure or a thin-film circuit layer onto a substrate with an inferior shape-stability. The method includes: forming a fine structure or a thin-film circuit layer on a first substrate using a photolithographic patterning process; shifting the fine structure or the thin-film circuit layer from the first substrate onto a second substrate, or shifting the fine structure or the thin-film circuit layer from the first substrate onto the second substrate via a third substrate; and forming a thin-film pattern on the fine structure or the thin-film circuit layer shifted onto the second substrate by a non-photolithographic method.

Abstract: The present invention prepares a member having a conductor-circuit-forming copper foil formed on a protrusion-forming copper layer via an etching-barrier layer formed of a different metal. Etching is selectively performed for the protrusion-forming copper foil by using etchant that does not etch the etching-barrier layer, and protrusions are thereby formed. Then, the etching-barrier layer is removed using etchant that does not etch the copper foil and using the protrusions as masks. An interlayer-insulating layer is formed on a surface of the copper foil, on which the protrusions are formed, so that the protrusions are connected to the conductor circuit. Thereby, heights of the protrusions are uniformed, and the reliability of connections can be improved.

Abstract: A method for connecting a chip to a leadframe includes forming bumps on a die by a Au stud-bumping technique, and attaching the chip to the leadframe by thermo-compression of the bumps onto bonding fingers of the leadframe. Also a flip chip-in-leadframe package is made according to the method. The package provides improved electrical performance particularly for devices used in RF applications.

Abstract: A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.

Abstract: An object of the present invention is to provide a technique for forming an ohmic connection between a semiconductor and a metal efficiently in a short period of time. The present invention provides a method of forming at least one electrode on a surface of a semiconductor, wherein a metal or alloy for the electrode is rubbed against a predetermined region of the semiconductor surface so as to be adhered by frictional force and frictional heat to the predetermined region of the semiconductor as an electrode and part of the adhered metal or a metal of the alloy is diffused into an inside of the semiconductor by the frictional heat thereby to be formed into an ohmic electrode substantially simultaneously when the metal or alloy is adhered by the frictional force and frictional heat to the predetermined region of the semiconductor.

Abstract: The present invention relates to improvements in forming and transferring solder bumps for use in mounting integrated circuit substrates on chip carrier packages. A mold having cavities for the solder bumps is held in contact with a substrate and a compressible device. As the temperature is increased to melt the solder in the cavities, at an appropriate time and temperature, the compressible device is caused to decompress resulting in the mold separating from the substrate and leaving formed solder bumps on the contacts on the substrate. Various mechanisms are described to cause the force holding the mold and substrate together to decrease.

Abstract: The invention provides a connection substrate, a method of manufacturing a connection substrate, a semiconductor device, a method of manufacturing a semiconductor device which can narrow a width and a pitch of wiring, enables a multi-layer wiring, and reduces an effect of radiation heat, such as a heating tool when a semiconductor chip is mounted so that a damage such as wire disconnection or the like due to an external force is not generated. First metal wires are formed on a surface of a first glass base. An insulating film is formed on the first metal wires, and second metal wires are formed on the insulating film. Thus, in a connection substrate, the first glass base has no flexibility, so deformation is not generated. Because of this, during interim processes wherein metal wires are formed, such as in an exposure process, a glass base does not move in a depth of field direction.

Abstract: A semiconductor device having area array bump electrodes suitable for flip chip packaging is disclosed. A semiconductor chip with wire bonding electrodes arranged along peripheral edges thereof is provided, then gold wire bump electrodes are formed over the wire bonding electrodes, and thereafter a wiring tape substrate is superimposed on the semiconductor chip and is bonded thereto with an adhesive. On a back surface of the wiring tape substrate are formed wiring connections correspondingly to the electrodes. Further, at the time of bonding with use of the adhesive, convex tips of the gold wire bump electrodes formed respectively on the electrodes of the semiconductor chip pierce through the adhesive to connect the gold wire bump electrodes and the connections electrically with each other. On a surface of the wiring tape substrate are formed area array bump electrodes, whose pitch is larger than the pitch of the electrodes formed on the semiconductor chip.

Abstract: A method for reducing the likelihood of damaging a semiconductor wafer (18) and the integrated circuit chips of the semiconductor wafer (18) during handling utilizes a wafer interposer (12) having a wafer receiving portion (28) and a handling portion (30). The wafer receiving portion (28) of the wafer interposer (12) has a plurality of contact pads (22) that are electrically and non-temporarily mechanically connected to the contact pads of the integrated circuit chips of the wafer (18). The handling portion (30) of the wafer interposer (12) extends outwardly from the wafer receiving portion (28) such that the handling portion (30) is accessible to handling equipment without the handling equipment contacting the attached wafer (18).