Abstract: Fixtures for attaching a semiconductor chip to a substrate. The semiconductor chip has an array of joining material bumps, such as C4 solder balls. The substrate has an array of conductive pads corresponding to the array of joining material bumps. In a first embodiment the fixture has a body having a first cavity for containing the semiconductor chip and a second cavity in communication with the first cavity for containing the substrate. Whereby the substrate is placed over the semiconductor chip with the conductive pads opposing and in contact with the joining material bumps, such that during reflow of the joining material bumps, the weight of the substrate acts against the joining material bumps and aids in the attachment of the semiconductor chip to the substrate to form electrical connections therebetween.

Abstract: A method for producing a semiconductor device, comprises the steps of: introducing a plurality of semiconductor element supporting substrates or semiconductor elements into a conductive-ball attaching system for collectively attaching conductive balls onto the supporting substrates or semiconductor elements; detecting the position of a defective substrate or defective semiconductor element of the introduced semiconductor element supporting substrates or semiconductor elements, or an undesired position, at which it is not necessary to load the conductive balls; vacuum holding a plurality of conductive balls, which are stored in the conductive-ball attaching system, by conductive-ball holding means; and selectively attaching the plurality of conductive balls, which are vacuum-held by the conductive-ball holding means, onto a desired supporting substrate or semiconductor element of the supporting substrates or semiconductor elements introduced into the conductive-ball attaching system, wherein the conductive-bal

Abstract: A method of forming an integrated circuit package at the wafer level. The integrated circuit package occupies a minimum amount of space on an end-use printed circuit board. Solder bumps, or conductive adhesive, is deposited on the metallized wirebond pads on the top surface of a silicon wafer. An underfill-flux material is deposited over the wafer and the solder bumps. A pre-fabricated interposer substrate, made of metal circuitry and a dielectric base, has a plurality of metallized through-holes which are aligned with the solder bumps. The wafer/interposer assembly is reflowed, or cured, to form the electrical connection between the circuitry on the interposer layer and the circuitry on the wafer. Solder balls are then placed on the metal pad openings on the interposer substrate and are reflowed to form a wafer-level BGA structure. The wafer-level BGA structure is then cut into individual BGA chip packages.

Abstract: The object of the present invention is to provide a free and precise control of the plating amount while easily determining a selected portion to be plated.

Abstract: Apparatus and methods for placing conductive spheres on prefluxed bond pads of a substrate using a stencil plate with a pattern of through-holes positioned over the bond pads. Conductive spheres are placed in the through-holes by a moving feed mechanism and the spheres drop through the through-holes onto the bond pads. In one embodiment, the feed mechanism is a sphere hopper which crosses the entire though-hole pattern. In another embodiment, a shuttle plate fed spheres from a reservoir and reversibly moves about one-half of the pitch, moving from a non-discharge position to a discharge position.

Abstract: A method of making a ball grid assembly and the assembly wherein a mask (1) is provided which is not wettable by solder and through which a pattern of parallel holes (3) is provided extending to at least one of a pair of opposing surfaces. A magnet (5), preferably an electromagnet, is disposed at the other one of the opposing surfaces. Solderable magnetic pins (7) are caused to enter the holes by magnetic attraction by positioning the one surface of the mask over the pins with a portion of each of the pins extending out of the hole into which it has entered. A layer of solder (11) is formed on the portion of each of the pins extending out of a hole in the mask and this layer of solder is reflowed over the pins and over a grid of solder adherable elements (13) on the package (15) and then allowed to set. The mask is removed from the pins when the solder is again set.

Abstract: A process of fabricating a tungsten bit line structure, capped with a composite insulator shape, has been developed. The process features the use of a silicon oxide component, used as part of the capping, composite shape, employed to reduce the coupling capacitance generated by the proximity of the tungsten bit line structure, to adjacent conductive structures. The silicon oxide component is formed on an underlying, thin silicon nitride shape, which in turn overlays the tungsten bit line structure, preventing oxidation of the tungsten surface during the silicon oxide deposition. A capping, silicon nitride shape is placed on the underlying silicon oxide component. The use of this sandwich, or composite insulator shape, allows a tungsten bit line structure, with a sheet resistance between about 1 to 3 ohms/square, to be realized, with a reduction in coupling capacitance, in turn realized via the use of the silicon oxide component.

Abstract: A method for attaching particles (12) to a substrate (14), comprising the steps of aligning particles (12) attached to an adhesive sheet (35) with contact pads (42) of a substrate (14), transferring thermal energy (38) to the adhesive sheet (35) by maintaining a temperature below the melting point of particles (12), and removing the adhesive sheet (35) prior to reflow, is disclosed. The adhesive sheet (35) may be composed of an adhesive coating (22) laminated to a film (24). The particles may be composed of a variety of compositions, including compounds such as solder or plastic, for example.

Abstract: A method of forming a plurality of bump electrodes en bloc on a bump electrode formation surface of a wafer from which chips are to be separated, or on an upper surface of a plurality of chips which are separated from a wafer and placed side by side, the upper surface constituting a bump electrode formation surface, is disclosed.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a conductive structure that couples a first substrate to a second substrate. The first substrate may include a chip or a module. The second substrate may include a chip carrier or a circuit card. Thus, the present invention encompasses such coupling as chip to chip carrier, chip to circuit card, and module to circuit card. The conductive structure includes a first conductive body and a second conductive body. The first conductive body is attached to the first substrate and the second conductive body is attached to the second substrate. The first conductive body may include a solder bump, while the second conductive body may include a eutectic alloy, such as a eutectic alloy lead and tin. Alternatively, the second conductive body may include a non-eutectic alloy whose melting point is below the melting point of the first conductive body.

Abstract: A semiconductor interconnect structure which includes a semiconductor substrate having a bottom surface. The printed circuit board also has a plurality of solder wettable pads disposed on the top surface of the printed circuit board. The printed circuit board and the semiconductor substrate are both comprised of material taken from the same group of materials. The interconnect structure also includes a plurality of balls formed of a first solder alloy disposed on the bottom surface of the semiconductor substrate and projecting downwardly therefrom. Each one of the plurality of balls are sized to support the weight of the semiconductor substrate. The interconnect structure also includes a plurality of solder joints formed of a second solder alloy connecting the plurality of balls to the corresponding plurality of wettable pads on the printed circuit board.

Abstract: The present invention is directed toward an apparatus and method for providing mechanically pre-formed conductive leads. In one embodiment of the invention, an apparatus includes a forming chuck engageable with a first surface of a conductive sheet, and a receiving chuck engageable with a second surface of the conductive sheet opposite from the forming chuck. The forming chuck has a raised forming portion alignable with one or more lead members formed in the conductive sheet, and the receiving chuck has a receiving portion alignable with the forming portion and shaped to closely conform to at least part of the forming portion. The conductive sheet is compressed between the forming chuck and the receiving chuck to mechanically pre-form the one or more lead members into one or more pre-formed conductive leads. In one embodiment, the raised forming portion includes a ridge having a polygonal cross-sectional shape and the receiving portion comprises a channel.

Abstract: Improved bonding pads in an integrated circuit are provided, each having a first bonding pad layer comprising a portion of a top metal layer, and a top bonding pad layer comprising a remaining portion of a deposited bonding pad metal fill layer. The thickness of the bonding pad is greater than the thickness of the top metal layer. The composition of the top bonding pad layer may be different from the top metal layer, so that the composition of each may be independently optimized. A method for forming the improved bonding pads includes deposition of a bonding pad metal fill layer to fill openings in a passivation layer over the first bonding pad layers, and removal of the bonding pad metal fill layer over the passivation layer. An alternative method removes the bonding pad metal fill layer only at areas immediately surrounding locations of the bonding pads, leaving top bonding pad layer and a metal radiation shield layer.

Abstract: An apparatus is provided for manufacturing a semiconductor package of the type in which a gap between a semiconductor chip and a mount board is filled with a resin. The apparatus includes resin supply means for supplying the resin along one side of the semiconductor chip, and resin supply control means for controlling the amount of resin supplied by the resin supply means such that more resin is supplied near the central portion of the semiconductor chip than near the end portions of the semiconductor chip. Also provided is a method that includes the steps of connecting the semiconductor chip and the mount board, and supplying the resin along one side of the semiconductor chip in such a manner that more resin is supplied near a central portion of the semiconductor chip than near the end portions of the semiconductor chip.

Abstract: An electronic component with solder ball connections is provided. A stencil is produced with holes passing through it in an arrangement corresponding to an arrangement of conductive pads on a substrate or integrated circuit. The stencil is made of a solder reflow compatible material. A layer of adhesive is applied to the stencil which is then positioned with the layer of adhesive adjacent the substrate or integrated circuit with the holes aligned with the conductive pads. Solder paste is deposited in the holes and is heated along with the conductive pads to form solder balls on the conductive pads.

Abstract: A method placing conductive elements, such as solder balls, over terminals on a microelectronic assembly includes providing a microelectronic element having a first surface and one or more terminals accessible at the first surface, and securing a spacer plate having a top surface, a bottom surface and at least one opening extending therethrough over the first surface of the microelectronic element so that the at least one opening is in substantial alignment with the terminals. After the spacer plate has been secured over the first surface of the microelectronic element, a stencil for placing conductive elements is then secured over the spacer plate. The stencil has a top surface and a bottom surface and a plurality of openings extending therethrough. When the stencil is secured over the spacer plate, the plurality of openings in the stencil are in substantial alignment with the terminals. As a result, the spacer plate maintains the stencil remote from the terminals.

Abstract: An improved interconnect structure for electrically connecting an infrared detector to external circuitry wherein thin film metal conductors are deposited on a thin, insulating tape. One end of the structure terminates at the detector at about 77.degree. Kelvin, the other end terminating at external electronics at about 300.degree. Kelvin. Due to the small cross section of the conductor, heat leak to the detector is minimized. In addition, the carrier film is only 15 microns thick, thus minimizing outgassing material. The use of epoxies is eliminated. The structure can be fabricated in a variety of configurations using standard semiconductor equipment.

Abstract: A method for performing rework test on integrated circuit (IC) packages is provided. By this method, the first step is to remove a selected part of the casing of the IC package to form an opening in the casing to expose the IC chip contained in the casing. Then, an adhesive layer, such as a double adhesive tape, is attached over the casing on the side where the opening is formed. Then, a heat-insulative cover, such as a ceramic cover, is adhered to the double adhesive tape. After this, the entire IC package is mounted by solder on a test circuit board, allowing a function test procedure to be performed on the internal circuitry of the IC chip contained in the casing. During the function test procedure, when necessary, the ceramic cover can be easily and effortlessly detached to allow the test engineer to visually inspect the inside IC chip for any structural problems.

Abstract: Multiplexed joining of solder bumps to various substrates for assembly of an integrated circuit package includes placing a semiconductor substrate (312) having solder bump structures (314) in contact with a ceramic substrate (320 having chip pads (322, 334), and placing this structure in contact with ball grid array spheres (352) in order to form a CBGA (360) in a single flow process.

Abstract: A method of electroplating a high density integrated circuit (IC) substrate using a conductive elastomer including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces with conductive trace lands formed on its surface. Covering only the traces (not the trace lands) with a plating resist and exposing portions of the conductive traces. Inserting the IC substrate into a electroplating fixture. Engaging a conductive elastomer to the IC substrate, covering the plurality of conductive traces and electrically connecting all of the traces together. Electroplating the trace lands on the IC substrate with conductive material (such as gold or nickel) by using the conductive elastomer as the electrical connection to the trace lands (via the exposed metal traces). Disengaging the conductive elastomer after electroplating is finished and removing the IC substrate from the electroplating fixture.

Abstract: A method of forming an interconnect bump structure (32, 33). Under Bumb Metalization 11 (UBM) comprising a chrome layer (16), a copper layer (36), and a tin layer (40) is disclosed. In one embodiment, eutectic solder (45) is then formed over the UBM (11) and reflowed in order to form the interconnect bump stucture. In another embodement, a lead standoff (46) is formed over the UBM (11) before the formation of the eutectic solder (48).

Abstract: A method of manufacturing a template having through-holes for attracting and supporting electrically conductive balls by vacuum suction is disclosed. The through-holes are formed by etching and the side walls of the through-holes are smoothed by irradiation, with laser beams, of the side walls of the through-holes. A template and metallic bumps can be formed using this method. Alternatively, the template can be formed in a two-layered structure.

Abstract: A method for aligning and bonding balls to substrates, such as semiconductor wafers, dice and packages, is provided. The method employs a ball retaining plate having a pattern of micromachined cavities and vacuum conduits for retaining the balls. In addition, a substrate alignment member attached to the ball retaining plate, aligns the substrate to the balls. Using the substrate alignment member, bonding sites on the substrate can be placed in physical contact with the balls which are held by vacuum on the ball retaining plate. Next, the ball alignment plate and substrate can be place in a furnace for reflowing and bonding the balls to the bonding sites. An apparatus for performing the method includes the ball retaining plate and the substrate alignment member. A system for performing the method includes a ball loader mechanism for loading balls onto the ball retaining plate, and a vacuum fixture for applying a vacuum to the ball retaining cavities.

Abstract: A method for fabricating a bump forming plate member by which bumps can be formed on an electronic component. A mask is formed on a surface of a crystalline plate, and the crystalline plate is subjected to anisotropic etching to form a plurality of grooves. The crystalline plate is also subjected to isotropic etching to deepen the grooves. The method can further includes additional anisotropic and isotropic etchings. Also, a method for fabricating a metallic bump forming plate member is disclosed. This method uses the above described crystalline plate having the grooves, and includes fabrication of a replica using the crystalline plate as an original, and fabrication of a metallic bump forming plate member using the replica as an original.

Abstract: A process for manufacturing a device for arranging conductive particles in a preselected pattern for the connection of electric circuit boards or electric parts is disclosed. Particularly, a device capable of surely and efficiently transferring, e.g., solder bumps to the electrode pads of a semiconductor chip or the leads of a TAB (Tape Automated Bonding) tape and a conductive particle transferring method using the same are disclosed.

Abstract: Improved bonding pads in an integrated circuit are provided, each having a first bonding pad layer comprising a portion of a top metal layer, and a top bonding pad layer comprising a remaining portion of a deposited bonding pad metal fill layer. The thickness of the bonding pad is greater than the thickness of the top metal layer. The composition of the top bonding pad layer may be different from the top metal layer, so that the composition of each may be independently optimized. A method for forming the improved bonding pads includes deposition of a bonding pad metal fill layer to fill openings in a passivation layer over the first bonding pad layers, and removal of the bonding pad metal fill layer over the passivation layer. An alternative method removes the bonding pad metal fill layer only at areas immediately surrounding locations of the bonding pads, leaving top bonding pad layer and a metal radiation shield layer.

Abstract: A semiconductor element/substrate mounting structure is formed by a first step of covering a resin film over the substrate together with a conductive portion; a second step of pressing and heating so that bumps penetrate through the resin film to come into contact with the conductive portion; and a third step of pressing and heating so that the bumps and the conductive portion become alloyed between the semiconductor element and the substrate.

Abstract: In a method of manufacturing an electronic component for forming a conductor pattern on an insulating substrate by transfer method employing intaglio printing technique, this manufacturing method comprises a step of fabricating an intaglio 20 made of flexible resin forming an insulating layer 23 on a groove 21, a step of filling the groove 21 with Ag paste 24 and drying, a step of overlaying the intaglio 20 on an insulating substrate 2 having a water-soluble resin 28 formed on the surface by pressing a pressing portion 26, freezing, peeling off the intaglio 20 and insulating substrate 2, and transferring the pattern of the Ag paste 24, and a step of firing it and forming a conductor pattern.

Abstract: The present invention provides a method of forming an opening an insulation layer over a substrate. A photo-resist film with at least an opening is formed over a substrate. A first spacer layer is selectively formed within the opening of the photo-resist film. The photo-resist film is removed to have the first spacer layer remain over the substrate. An insulation layer is formed which extends over the first spacer layer and the substrate so that the insulation layer over the first spacer layer is higher in level than the insulation layer over the substrate. A second spacer layer is formed which extends over the insulation layer over the substrate so that the insulation layer over the first spacer layer is shown. Both the insulation layer over the first spacer layer and the second spacer layer are selectively removed so that the insulation layer over the substrate and the first spacer layer are shown.

Abstract: Methods for forming solder bumps on terminal pads of a semiconductor substrate for an integrated circuit device employ a solder bump transfer plate and a mask to form solder deposits on the plate. One embodiment of the invention employs a metal mask having a plurality of through holes for forming solder deposits on the solder bump transfer plate by vapor phase deposition through the through holes each area of which increases in step wise from the first surface of the mask to the second surface opposite to the first surface, thereby preventing solder deposits in the through holes from being removed when the mask is separated from the plate. Another embodiment of the invention is a solder bump transfer plate having a plurality of solder deposits on the surface non-wettable to molten solder both diameter and spacing of which are both smaller than diameter and spacing of the terminal pads on the semiconductor substrate, whereby a single solder bump is accurately formed on each of the terminal pads.

Abstract: A method of fabricating a semiconductor device which includes providing a shaped bond pad, preferably rectangular or oval. A cavity followed by a hill are formed in the bond pad by performing a probe test at one end portion of the bond pad. Then a ball bond is formed on the bond pad remote and spaced from the cavity. The ball bond can extend onto the hill or be spaced from the hill. The bond pad preferably has a greater length than width and the cavity, hill and ball bond are disposed successively along the length of the bond pad. The length of the bond pad in the direction normal to the cavity, the hill and the ball bond is greater than the sum of the diameter of a probe tip with which a probe test will be made on the bond pad and the diameter of the ball bond.

Abstract: A method for arranging metallic balls to form an array of bump electrodes comprises the steps of immersing a silicon template in ethanol dropping metallic balls through the ethanol onto the template to receive the metallic balls in the holes of the template. The metallic balls are free from cohesion caused by electrostatic charge or moisture. The template may be inclined in the ethanol. The holes are formed by anisotropic etching a silicon plate.

Abstract: A plate used for fabricating metal bumps is made from a silicon having a <110> crystallographic plane. The plate has a flat surface arranged at an angle relative to the <110> crystallographic plane, and cavities are formed in the flat surface by anisotropic etching. Each of the cavities has a rhombic opening and two oblique bottom surfaces defining a deepest portion. The deepest portion is shorter than the diagonal line of the rhombus and positioned in the cavity near one end thereof. In the method for fabricating metal balls, the cavities are filled with a paste containing metal particles, and heated to form metal balls in the cavities. The metal balls are then transferred from the plate to an electronic device.

Abstract: A method for producing a semiconductor device includes steps of: a) a positioning board forming process in which concave portions, each of which is located at a position corresponding to a position of a respective projecting electrode of a semiconductor device, and first positioning portions, which are used for determining a position of a sealing resin with respect to the projecting electrode, are integrally formed on a flat-plate member so as to form a positioning board; b) a filling process in which an electrode material for forming the projecting electrode is filled in the concave portions formed on the positioning board; c) a bonding process in which a composite board is formed by mounting a circuit board on the positioning board so as to bond each of the electrode material filled in the concave portions to the circuit board; d) a sealing resin forming process in which a mold having a cavity for forming a sealing resin and second positioning portions for determining a position of the positioning board wit

Abstract: A hollow package manufacturing method includes the adhesive spreading step, the adhesive applying step, and the cap adhering step. In the adhesive spreading step, an adhesive is spread on a circular table to a uniform thickness. In the adhesive applying step, an open end face of a cylindrical cap having a bottom is urged against the circular table to apply the adhesive to the cap. In the cap adhering step, the cap applied with the adhesive is adhered to a case. A hollow package manufacturing apparatus is also disclosed.

Abstract: A process within substrate is provided with vias communicating with surface contacts or bumps. Joining material paste is forced through holes in a screen onto an area array of the contacts on the substrate then the screen is biased against the substrate as the paste is heated and cooled to transfer the joining material onto the contacts. Alternately, joining material paste is forced into the screen and then a substrate is placed onto the screen with an area array of bump contacts of the substrate in contact with the solder paste, and then the paste is heated and cooled to transfer the material onto the bumps. The joining material may be a solder paste, conductive adhesive paste, or transient liquid bond paste. The substrate may be a semiconductor chip substrate, flexible or rigid organic substrate, or a metal substrate coated to form a dielectric surface. Also, the substrate may be a computer chip, chip carrier substrate or a circuit board substrate.

Abstract: A first pattern of bumps and a second pattern of bumps are formed on a substrate (10) with bumps (14,15). During a transfer process, only the bumps (14) of the first pattern of bumps are transferred to pad extensions (20) of a device (17). The bumps (15) of the second pattern of bumps are not affected by this process and can be later transferred to a second device.

Abstract: A structure and a process for forming an improved bonding pad which allows better bonding between a bond wire and a metal bonding pad. Stripes are formed on a substrate. A conformal dielectric layer, a conformal barrier layer and a metal layer are formed over the stripes. A passivation layer with a window is formed defining a bonding pad area. The stripes promote an irregular surface in the barrier and metal layers which reduce stress between the dielectric layer, the barrier layer and the metal layer. Also, the irregular surfaces increase the barrier metal adhesion to the dielectric layer, reduce bond pad peel off, and increase bonding yields.

Abstract: A packaging method for a ball grid array (BGA) integrated circuit (IC) without utilizing a base plate as a supporting plate, and therefore reducing the thickness of the packaged BGA IC. In the method, a copper sheet is used as a supporting plate first. After resin is applied to coat a chip implanted on the copper sheet and connecting wires thereof has hardened, the hardened resin is sufficiently firm to support the IC, so the copper sheet can be etched. Accordingly, a base plate is not necessary.

Abstract: Solder paste (16) is dispensed onto a platen (12) that includes depressions (14) that are preferably conical or in an inverted pyramid shape. The solder paste (16) is formed of a plurality of particles composed of a solder alloy. Excess solder paste (16) is removed, and a predetermined solder paste volume fills the depressions (14). A substrate (18) is superposed onto platen (12) such that solder-wettable bond pads (20) on the substrate (18) register with the depressions (14). The platen (12) is heated to melt the solder alloy, and the solder alloy coalesces to form molten solder droplets (22). The solder droplets (22) are transferred onto the solder-wettable bond pads (20) to form solder bumps (24) bonded to the bond pads (20).

Abstract: The present invention relates generally to a new scheme of providing a seal for semi-conductor substrates and chip carriers. More particularly, the invention encompasses a structure and a method that uses a multi-layer metallic seal to provide protection to chips on a chip carrier. This multi-layer metal seal provides both enhanced hermeticity lifetime and environmental protection. For the preferred embodiment the multi-layer metallic seal is a two layer, solder structure which is used to create a low cost, high reliability, hermetic seal for the module. This solder structure has a thick high melting point temperature region that is attached to a cap, and a thin interconnecting region of lower melting point temperature region for sealing the substrate to the cap.

Abstract: A method of forming a semiconductor device having a semiconductor chip having electrodes on which electrode pins are formed includes the steps of forming a complex having the electrode pins fixed in a fixing member, an arrangement of the electrode pins corresponding to that of the electrodes, connecting the electrode pins with the electrodes by mounting the complex on the semiconductor chip, and removing the fixing member from the complex mounted on the semiconductor chip.