Abstract: An integrated electronic device having an electric connection between a first electrode of a semiconductor chip and a second electrode of a circuit board. One embodiment according to the present invention is a method for fabricating an integrated electronic device having an electric connection between a first electrode of a semiconductor chip and a second electrode of a circuit board, both surfaces of the first and second electrodes having an adhesive tendency to molten metal, the method comprising the steps of forming a metal bump on the first electrode, the metal bump being made of a soldering metal alloy consisting of a solid phase component and a liquid phase component at an operating temperature; and forming an electric connection between the first electrode and the second electrode by heating the soldering metal alloy so as to adhere to the surface of the second electrode.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.

Abstract: A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.

Abstract: Process operations are performed for subjecting target substrates (W) respectively to a semiconductor process, while a target substrate (W) is placed on a worktable (24) within a process chamber (14), and the worktable (24) is heated by a temperature control member (50) to heat the target substrate (W). The reflection coefficient within the process chamber (14) is changed depending on deposition of a by-product, which is generated during the semiconductor process on the target substrate (W), within the process chamber (14). A parameter representing the reflection coefficient within the process chamber (14) is measured, between the first and last ones of the process operations. The set temperature of the worktable (24) used in the semiconductor process is adjusted, based on a measured value of the parameter, during process operations performed after measuring the parameter. As a consequence, repeatability of the semiconductor process is improved.

Abstract: A semiconductor device comprising the bump containing magnetic body, magnetic body, the bump including non-magnetic body for at least partially covering the magnetic body, mixture of magnetic particles and non-magnetic particles and the bump including baked magnetic particles and baked non-magnetic particles.

Abstract: A ball electrode forming method comprises steps of: preparing a semiconductor apparatus having a plurality of electrode pads; arranging a mask having an upper surface and a lower surface, an area in the lower surface being larger than an area in the upper surface, and a plurality of openings extended from the upper surface to the lower surface, on a surface of the semiconductor apparatus having the electrode pads formed thereon so that the surface and the lower surface can face each other; arranging solder balls on the electrode pads arranged in the openings from the upper surface side of the mask; and electrically connecting the solder balls to the electrode pads to form ball electrodes. Thus, regarding a method for forming a ball electrode in a semiconductor apparatus having a BGA structure, an efficient ball electrode forming method is employed to prevent omission of a ball electrode.

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: The method for producing a solder bump transfer sheet of the invention includes the steps of: providing a sheet having a chromium oxide layer containing substantially no iron oxide as the outermost surface; and forming a plurality of solder bumps placed in a predetermined pattern on the chromium oxide layer.

Abstract: In a method of manufacturing bump electrodes, a solder paste material is filled in concave parts provided on one surface of a jig for forming bumps, and the solder paste material is melted under the condition in that the concave parts of the jig for forming bumps face electrode pads provided on one surface of a substrate (a semiconductor chip or a circuit board), to form bump electrodes on the electrode pads of the substrate, whereby the size of the bump electrodes formed on electrode pads can be uniform. Furthermore, a short circuit among the electrode pads of the substrate (a semiconductor chip or a circuit board) can be prevented. Furthermore, the yield in a production process of a semiconductor device having bump electrodes can be increased.

Abstract: Methods for forming substantially chip scale packages and the resulting structures. The methods comprise applying an adhesive on an active surface of a semiconductor chip to form a patterned adhesive layer on a portion of the active surface. A leadframe having leads with inner lead ends and outer lead ends is provided. The inner lead ends of the leads are aligned proximate to the adhesive-free area and the leads are attached to the adhesive layer on the active surface of the semiconductor chip. The outer lead ends are oriented to form a footprint which is not substantially larger than the dimensions of the semiconductor chip.

Abstract: Dielectric rings are configured to be disposed around contact pads on a surface of a semiconductor device or another substrate and methods of fabricating and disposing the rings on semiconductor devices and other substrates. The rings may be disposed around the contact pads before or after conductive structures, such as solder balls, are secured to the contact pads. Upon connecting the semiconductor device face-down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the rings prevent the material of solder balls protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof. The rings may be preformed structures or fabricated on the surface of the semiconductor device or other substrate. For example, stereolithographic techniques may be used to form the rings.

Abstract: A ball grid array for a flip-chip assembly. The ball grid array includes a plurality of bumps bonded between an active surface of a semiconductor die and a top surface of a printed circuit board or any type of substrate carrier. The plurality of balls include at least one bump having a core material and an outer layer. The rigidity of the core material is greater than that of the material of the outer layer. Additionally, the melting temperature of the core material is higher than the material of the outer layer. By this arrangement, the core material with an outer layer provides bumps that are substantially uniform in height. In addition, the balls only procure marks or deformation to the core material during burn-in testing and reflow.

Abstract: A hole metal-filling method, applied to hole filling and electroplating a printed circuit board which has been mechanical-drilled with holes. A plurality of holes is drilled in a substrate. The substrate is placed on a platform. A plurality of metal balls is disposed on a surface of the substrate. By vibrating the platform, a part of the metal balls roll into the holes, while the metal balls not rolling into the holes are removed. The substrate is then placed on a press down unit. The metal balls in the holes are pressed to level with surfaces of the substrate. The substrate is directly electroplated for forming a plating layer closely dovetail to the metal balls.

Abstract: A wiring pattern formation method for forming a wiring pattern on a wafer by using a transcribing operation includes a transcribing step of thermally pressing and adhering a transcribing original substrate 19 that contains a metallic wiring layer 15 to be transcribed and has a linear expansion coefficient in which a dimensional error from a wafer 10 is within a predetermined range in a heated condition, on the wafer 10, and then adhering and transcribing the metallic wiring layer 15.

Abstract: Apparatus and methods for placing conductive spheres on prefluxed bond pads of a substrate using a stencil plate with a pattern of through-holes positioned over the bond pads. Conductive spheres are placed in the through-holes by a moving feed mechanism and the spheres drop through the through-holes onto the bond pads. In one embodiment, the feed mechanism is a sphere hopper which crosses the entire through-hole pattern. In another embodiment, a shuttle plate fed spheres from a reservoir and reversibly moves about one-half of the pitch, moving from a non-discharge position to a discharge position.

Abstract: A method for forming a metal line of a semiconductor device is disclosed, in which a Cu thin film is deposited on a diffusion barrier film after a chemical enhancer and plasma are applied thereon, thereby improving fill characteristics of a contact hole having an ultra-fine structure. The method for forming a metal line in a semiconductor device includes the steps of forming an interlevel insulating film on a semiconductor substrate having a predetermined lower structure, forming a damascene pattern in the interlevel insulating film, forming a diffusion barrier film on a whole structure having the damascene pattern, applying a chemical enhancer on the diffusion barrier film to form a chemical enhancer film on the diffusion barrier film, performing plasma treatment, forming a Cu thin film on the whole structure to fill the damascene pattern, and performing a polishing process to expose an upper surface of the interlevel insulating film so that the Cu thin film only remains within the damascene pattern.

Abstract: A method for manufacturing a ball grid array semiconductor package includes the step of providing a substrate (103) having a first surface (103b) and a second surface (103a), in which the first surface (103b) or the second surface (103a) comprises a conductor pattern (104). The method also includes the steps of providing a plurality of conductive bump contact areas (not shown) on the first surface (103b) of the substrate (103), and substantially aligning each of the conductive bump contact areas (not shown) with at least one conductive bump (107). The method further includes the step of disposing at least one of the conductor bumps (107) on each of the conductive bump contact areas (not shown).

Abstract: Methods for forming substantially chip scale packages and the resulting structures. The methods comprise applying an adhesive on an active surface of a semiconductor chip to form a patterned adhesive layer on a portion of the active surface. A leadframe having leads with inner lead ends and outer lead ends is provided. The inner lead ends of the leads are aligned proximate to the adhesive-free area and the leads are attached to the adhesive layer on the active surface of the semiconductor chip. The outer lead ends are oriented to form a footprint which is not substantially larger than the dimensions of the semiconductor chip.

Abstract: A temporary attach article of a first component to a second component which includes a first component having a first volume of a fusible material; a second component having a second volume of fusible material; and the first and second components being joined together through the first and second volumes of fusible material, wherein the first volume of fusible material has a melting point higher than a melting point of the second volume of fusible material so that the first and second components may be joined together without melting of the first volume of fusible material and wherein the second volume of fusible material is 5 to 20% of the first volume of fusible material. Also disclosed is a method for temporary attach of devices to an electronic substrate.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A method of making a ball grid assembly and the assembly wherein a mask (1) is provided which is not wettable by solder and through which a pattern of parallel holes (3) is provided extending to at least one of a pair of opposing surfaces. A magnet (5), preferably an electromagnet, is disposed at the other one of the opposing surfaces. Solderable magnetic pins (7) are caused to enter the holes by magnetic attraction by positioning the one surface of the mask over the pins with a portion of each of the pins extending out of the hole into which it has entered. A layer of solder (11) is formed on the portion of each of the pins extending out of a hole in the mask and this layer of solder is reflowed over the pins and over a grid of solder adherable elements (13) on the package (15) and then allowed to set. The mask is removed from the pins when the solder is again set.

Abstract: A soldering ball fabrication method includes the steps of: (1) drawing a metal wire rod into the desired thickness, (2) cutting the metal wire thus obtained into pieces subject to the desired length, (3) washing the pieces of metal wire to remove dust, (4) processing the pieces of metal wire into balls, (5) washing the balls thus obtained, (6) using a screen to select the balls, (7) inspecting selected balls, and (8) obtaining approved soldering balls.

Abstract: A device and method for insuring the separation between a leadless chip carrier and printed wiring board, comprising aligning and attaching conductive pedestals to contact pads of either member and embedding the pedestals into the solder columns which are used to provide electrical connection. The conductive pedestals are comprised of an electrically conducting metal, solder, alloy or composite which will also provide thermal dissipation in selected designs.

Abstract: A flip chip type semiconductor device is provided with a semiconductor chip with a plurality of pad electrodes on one surface. A solder electrode is connected to each pad electrode and a metallic post is connected to each solder electrode. The surface of the semiconductor chip on a side on which the pad electrodes are provided is coated with an insulating resin layer and whole the pad electrode and solder electrode and part of the metallic post are buried in the insulating resin layer. The remaining portion of the metallic post is projected from the insulating resin layer to for a protrusion. Then, an outer solder electrode is formed so as to cover this protrusion. The outer solder electrodes are arranged in a matrix on the insulating resin layer. The height of the protrusion is made 7 to 50% of the distance between an end of the outer solder electrode and the surface of the insulating resin layer.

Abstract: A system for attaching a plurality of solder balls to an electronic device is disclosed. The system includes, in one embodiment, a heat-resistant tape having a first side comprising a plurality of recesses. The first side of the tape may form an adhesive surface. The recesses are located for registration with a plurality of connection points on the electronic device. The recesses are each adapted to receive and retain a solder ball therein. After placing a solder ball within two or more of the recesses, the first side of the tape may be adhered to the electronic device with the solder balls retained therein. Heating of the solder balls causes them to reflow and adhere to the connection points. After cooling, the tape may be removed, wherein the solder balls remain bonded to the connection points, forming a Ball Grid Array (BGA).

Abstract: A semiconductor device comprises a semiconductor element having electrodes and metal bumps are attached to the electrodes. The metal bumps include copper cores and gold surface layers covering the cores. In addition, the metal bumps may include gold bump elements and solder bump elements connected together.

Abstract: A semiconductor device and method for fabricating the same which improves reliability of the semiconductor device is disclosed. The semiconductor device includes: a first insulating film and a gate electrode sequentially formed on a part of a semiconductor substrate; a first insulating spacer formed at both sides above the gate electrode; a second insulating spacer formed at both sides below the gate electrode; and a cobalt silicide film formed on a surface of the gate electrode at a predetermined depth.

Abstract: An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.

Abstract: A bump formation plate is provided with a base and solder bumps formed on the base. The top portion of the solder bump inclines from the center thereof to the periphery thereof. A contact surface of the solder bump with the base may be flat. The base is made of, for example, aluminum or stainless steel.

Abstract: A method of manufacturing a template having through-holes for attracting and supporting electrically conductive balls by vacuum suction is disclosed. The through-holes are formed by etching and the side walls of the through-holes are smoothed by irradiation, with laser beams, of the side walls of the through-holes. A template and metallic bumps can be formed using this method. Alternatively, the template can be formed in a two-layered structure.

Abstract: A wafer-scale assembly apparatus for integrated circuits and method for forming the wafer-scale assembly. A semiconductor wafer including a plurality of circuits is provided with a plurality of metal contact pads as electrical entry and exit ports. A first wafer-scale patterned polymer film carrying solder balls for each of the contact pads on the wafer is positioned opposite the wafer, and the wafer and the film are aligned. The film is brought into contact with the wafer. Radiant energy in the near infrared spectrum is applied to the backside of the wafer, heating the wafer uniformly and rapidly without moving the semiconductor wafer. Thermal energy is transferred through the wafer to the surface of the wafer and into the solder balls, which reflow onto the contact pads, while the thermal stretching of the polymer film is mechanically compensated. The uniformity of the height of the liquid solder balls is controlled either by mechanical stoppers or by the precision linear motion of motors.

Abstract: A method of fabricating a multi-layer ceramic substrate for forming a first conductive pattern on a ceramic substrate. An intaglio plate is manufactured which has first and second grooves. The grooves are filled with an electroconductive paste. Conductivity of paths in the grooves is increased by deaerating and drying the paste. The intaglio plate is glued to and then separated from a ceramic substrate so that the pattern of the pattern of the electroconductive paste is transferred to the substrate. An insulation layer and a further conductive pattern are then applied.

Abstract: A semiconductor device comprises a semiconductor element having electrodes and metal bumps are attached to the electrodes. The metal bumps include copper cores and gold surface layers covering the cores. In addition, the metal bumps may include gold bump elements and solder bump elements connected together.

Abstract: A fabrication method for a dual damascene structure is provided. A barrier layer and a copper seed layer are formed on a substrate comprising a dual damascene opening, wherein the barrier layer and the copper seed layer cover the dual damascene opening. A sacrificial layer is then formed on the copper seed layer, filling the dual damascene opening. Using the copper seed layer as an etch stop layer, the sacrificial layer is etch back. The exposed copper seed layer is then removed, followed by completely removing the sacrificial layer. A metal copper layer is formed in the dual damascene opening by plating, filling the opening of the dual damascene opening.

Abstract: In a method of manufacturing bump electrodes, a solder paste material is filled in concave parts provided on one surface of a jig for forming bumps, and the solder paste material is melted under the condition in that the concave parts of the jig for forming bumps face electrode pads provided on one surface of a substrate (a semiconductor chip or a circuit board), to form bump electrodes on the electrode pads of the substrate, whereby the size of the bump electrodes formed on electrode pads can be uniform. Furthermore, a short circuit among the electrode pads of the substrate (a semiconductor chip or a circuit board) can be prevented. Furthermore, the yield in a production process of a semiconductor device having bump electrodes can be increased.

Abstract: The present invention provides a method of forming bumps capable of forming many bumps having an adequate volume and having a narrow range of variations in height and few limitations in selecting materials on an object such as a semiconductor device or the like at high production rates with high reliability and with ease, and a system therefor. The present invention uses a suction head using a porous plate and a stencil having many apertures. Solder balls are previously aligned and charged into the stencil. The solder balls and the stencil are sucked and retained by the suction head and then are positioned with respect to the surfaces of the pads of a semiconductor device and only the solder balls are dropped on the pads. The solder balls are fixed to the pads with an adhesive previously applied thereto and then are reflowed to form bumps.

Abstract: An integrated circuit mounting structure of this invention comprises an integrated circuit and a mounting substrate. The integrated circuit has electrodes on the lower surface thereof. The pieces of the conductive material are attached to the electrodes, respectively. Terminals are provided on the upper surface of the substrate. The positions of terminals correspond to these of the pieces of conductive material, respectively. The pieces of conductive material and the terminals are connected by connection members, respectively. At the time of mounting the integrated circuit on the mounting substrate, each electrode is connected to the one end of a lead. The lead is cut and a piece of the lead is left on the electrode on the integrated circuit.

Abstract: A method for providing an enhanced ball grid array attachment in low-temperature co-fired ceramic (LTCC) substrate is provided. A termination cup is formed in a substrate. The termination cup has a bottom formed by a termination pad over a via in a first tape layer and side walls formed by termination sides formed over side walls of a via in a second tape layer. A diffusion layer is formed over the termination cup. The diffusion layer helps to reduce the oxidation of the termination cup and to provide greater mechanical attachment strength. An electrically conductive adhesive may be used to connect a solder ball to the diffusion layer. Reflow then is used to complete the solder ball connection process.

Abstract: A semiconductor package and fabrication method of the semiconductor package are provided. The semiconductor package is highly reliable and has a construction that enables an improvement of fabrication yield and that can greatly reduce the number of steps and the amount of time required for steps. The semiconductor package has a construction in which wiring layer 14 is supported by insulating film 13 over a range corresponding to chip electrodes 12 of semiconductor chip 11.

Abstract: A method of making a microelectronic assembly includes juxtaposing a first element, such as a dielectric sheet having conductive leads thereon with a second element, such as a semiconductor chip, having contact thereon, and wire bonding the conductive leads on the first element to the contacts on the second element so that elongated bonding wires extend between the conductive leads and the contacts. After the wire bonding step, the first and second elements are moved through a pre-selected displacement relative to one another so as to deform the bonding wires. A flowable dielectric material may be introduced between the first and second elements and around the bonding wires during or after the moving step. The flowable material may be cured to form an encapsulant around at least a portion of the bonding wires.

Abstract: A method of making a chip scale package comprises the following steps: providing a semiconductor chip having a plurality of metal bumps formed on the active surface thereof; providing a metal plate having a plurality of flip-chip pads formed on a surface thereof; positioning the semiconductor chip on the surface of the metal plate with the metal bumps on the chip aligned with the flip-chip pads on the metal plate; connecting the metal bumps on the active surface of the semiconductor chip to the flip-chip pads on the surface of the metal plate; encapsulating the semiconductor chip against a portion of the surface of the metal plate; removing the metal plate while leaving the flip-chip pads intact; and forming a plurality of solder balls on the flip-chip pads. Using the technique of the present invention, it becomes possible that the manufacture of a molded chip scale package can be relatively simplified and economical, yet highly reliable.

Abstract: A method of forming interconnects on an electronic device that can be bonded to another electronic device at a low processing temperature can be carried out by depositing a first interconnect material on the electronic device forming protrusions and then depositing a second interconnect material to at least partially cover the protrusions, wherein the second interconnect material has a lower flow temperature than the first interconnect material. The method is carried out by flowing a molten solder into a mold having microcavities to fill the cavities and then allowed to solidify. The mold is then aligned with a silicon wafer containing chips deposited with high melting temperatures solder bumps such that each microcavity of the mold is aligned with each high melting temperature solder bump on the chip.

Abstract: In a method of manufacturing bump electrodes, a solder paste material is filled in concave parts provided on one surface of a jig for forming bumps, and the solder paste material is melted under the condition in that the concave parts of the jig for forming bumps face electrode pads provided on one surface of a substrate (a semiconductor chip or a circuit board), to form bump electrodes on the electrode pads of the substrate, whereby the size of the bump electrodes formed on electrode pads can be uniform. Furthermore, a short circuit among the electrode pads of the substrate (a semiconductor chip or a circuit board) can be prevented. Furthermore, the yield in a production process of a semiconductor device having bump electrodes can be increased.

Abstract: An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over the conductive traces proximate the semiconductor die periphery and directly attaches to and makes electrical contact with the conductive traces in a LOC arrangement. Alternately, a connector may contact a portion of the conductive trace to make contact therewith.

Abstract: A semiconductor device and a method of producing the same, the device including a semiconductor chip; balls which function as external connecting terminals; a substrate which electrically connects the semiconductor chip and the balls; a mold resin which seals at least a part of the semiconductor chip; and a connecting portion sealing resin which seals the connecting portion between the substrate and the semiconductor chip. The semiconductor device is mounted onto a printed circuit board via the balls. The thermal expansion coefficient of the mold resin is matched with the thermal expansion coefficient of the printed circuit board. A side surface holding portion for the holding the side surfaces of the semiconductor chip is formed in the mold resin to restrict thermal deformation of the semiconductor chip.

Abstract: An improved integrated circuit device that includes both bond pads and trim pads is disclosed. Electrically conductive, non-wettable and non-corrosive protective caps are formed over each of the trim pads. With this arrangement, the protective caps act as barriers between the trim pads and solder used to form solder bumps when the IC package is mounted onto a substrate. In one embodiment, the protective caps are formed from a material that is easily sputtered, such as titanium. In a method aspect of the invention, the protective caps are applied during wafer level processing before either the solder bumping or trimming operations.

Abstract: Method for forming solder bumps on a first member such as a semiconductor chip having electrode pads formed thereon. A flat plate having holes is prepared and the holes are filled with solder paste by squeezing. The flat plate is then overlapped with the first member with the flat plate above the first plate. The flat plate and the first member are heated to a temperature higher than the melting point of the solder alloy in the solder paste. Therefore, solder bumps having identical sizes and uniform structures can be obtained.

Abstract: A method of fabricating a dual damascene structure. The method forms a silicon oxide layer, a stop layer, a low k organic dielectric layer, and a cap layer are formed in sequence on a substrate. A trench is formed in the cap layer and the low k organic dielectric layer, while a via opening is formed in the stop layer and the silicon oxide layer. A part of the stop layer is removed to form a cavity below the low k organic dielectric layer, followed by forming fluorinated poly-arlyethers spacers on sidewalls of the trench and the via opening which fills the cavity. The trench and the via opening are then filled with a copper layer to form a dual damascene structure.

Abstract: A method of forming a solder film on a metallic surface such as a pad of a metallic circuit of a printed circuit board and a lead frame of electronic parts, which is capable of forming a precise and fine pattern and which comprises selectively imparting tackiness to only a predetermined part of the metallic surface by means of a tacky layer-forming solution containing at least one compound selected from benzotriazole derivatives, naphthotriazole derivatives, imidazole derivatives, benzoimidazole derivatives, mercaptobenzothiazole derivatives, benzothiazole thiofatty acid derivatives, and triazine derivatives, adhering a powdered solder to the resulting tacky part, and then melting the solder by heating to thereby form a solder film.

Abstract: A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.