Abstract: A method of fabricating a dual damascene structure includes etching a via through a first dielectric layer above a substrate, a barrier layer on the first dielectric layer, and a second dielectric layer on the barrier layer. The via is at least partially filled with a photoresist plug. The plug is etched back. A trench is etched through the second dielectric layer. The trench is aligned with the via. The substrate having the first and second dielectric layers thereon is wet with an acid for a sufficient length of time to remove a via fence formed in the trench. The via and the trench are filled with metal.

Abstract: A method for cleaning semiconductor substrates includes a DI water clean operation that uses a spin speed no greater than 350 rpm. The cleaning method may include additional cleaning operations such as an organic clean, an aqueous chemical clean or a DI water/ozone clean. The cleaning method may be used to clean substrates after the conclusion of an etching procedure which exposes a single film between a Cu-containing conductive material and the environment. The spin speed of the DI water clean operation prevents copper corrosion due to breakdown of the film that separates the Cu-containing conductive material from the environment.

Abstract: The present invention provides a method of preparing a surface of a silicon wafer for formation of HSG structures. The method contemplates providing a wafer having at least one HSG template comprising polysilicon formed in BPSG, the HSG template being covered by silicon dioxide. The wafer is treated with a cleaning agent to clean the surface of the wafer. Next, the wafer is treated with a conditioning agent. The conditioning agent removes native oxide from the HSG template without excessively etching structural BPSG. Preferably, the conditioning agent also removes a thin layer of polysilicon on the HSG template. The wafer is then transferred to a process chamber for HSG formation.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: A method of manufacturing an electronic device comprises forming a wiring material layer made of aluminum or an aluminum alloy on the surface of an insulating film on a substrate, patterning the wiring material layer by a reactive ion etching treatment with a resist pattern used as a mask so as to form a wiring, and treating the surface of the insulating film including the wiring with an aqueous solution for removing the etching residue, the aqueous solution containing a peroxosulfate, a fluorine-containing compound and an acid for adjusting the pH value and having a pH value of ?1 to 3.

Abstract: A method of fabricating final spacers having a target width comprises the following steps. Initial spacers, each having an initial width that is less than the target width, are formed over the opposing side walls of a gate electrode portion. The difference between the initial spacer width and the target width is determined. A second spacer layer having a thickness equal to the determined difference between the initial width of the initial spacers and the target width is formed upon the initial spacers and the structure. The second spacer layer is etched to leave second spacer layer portions extending from the initial spacers to form the final spacers.

Abstract: A method of planarizing a spin-on material layer is provided. A substrate having a plurality of openings thereon is provided. A spin-on material layer is formed on the substrate such that the openings are completely filled. A plasma etching process is carried out to remove a portion of the spin-on material layer and expose the substrate surface. During the plasma etching process, the substrate is cooled to maintain an etching selectivity between the spin-on material layer on the substrate surface and the spin-on material layer within the openings so that a planar spin-on material layer is ultimately obtained.

Abstract: A method of reworking an integrated circuit device is described. A substrate having a dielectric layer, a barrier layer, a conductive layer and an anti-reflective layer formed thereon, is provided. The method of reworking the barrier layer, the conductive layer and the anti-reflective layer comprises removing the anti-reflection layer by performing a dry etching process, removing the conductive layer by performing a wet etching process, and then removing the barrier layer by performing a chemical machine polishing process.

Abstract: Methods and apparatus for fabricating and cleaning in-process semi-conductor wafers are provided. An in-process wafer is placed within a closed chamber. A reactant gas is incorporated in a liquid solvent to form a “reactant mixture” that is capable of reacting with photoresist material (or other material) on a wafer surface to facilitate removal of the material from the wafer surface. The reactant mixture is condensed on one or more of the in-process wafer surfaces to form a thin film on the surface(s) of the wafer. The solvent in the reactant mixture acts as a transport medium to place the reactant gas on the wafer surface. The reactant gas is then able to react with the photoresist material (or other material) on the in-process wafer surface to effect removal the material. Following reaction of the reactant gas with the photoresist, the thin film of reactant mixture is removed from the wafer surface by flash heating, rinsing, draining, or other suitable means.

Abstract: A method is provided for eliminating a polish stop layer from a polishing process. In particular, a method is provided which may include polishing an upper layer of a semiconductor topography to form an upper surface at an elevation above an underlying layer, wherein the upper surface does not include a polish stop material. Preferably, the upper surface of the topography formed by polishing is spaced sufficiently above the underlying layer to avoid polishing the underlying layer. The entirety of the upper surface may be simultaneously etched to expose the underlying layer. In an embodiment, the underlying layer may comprise a lateral variation in polish characteristics. The method may include using fixed abrasive polishing of a dielectric layer for reducing a required thickness of an additional layer underlying the dielectric layer. Such a method may be useful when exposing an underlying layer is desirable by techniques other than polishing.

Abstract: A method for removing silicon dioxide residuals is disclosed. The method includes reacting a portion of a silicon dioxide layer (i.e., oxide) to form a reaction product layer, removing the reaction product layer and annealing in an environment to remove oxide residuals. The method finds application in a variety of semiconductor fabrication processes including, for example, fabrication of a vertical HBT or silicon-to-silicon interface without an oxide interface.

Abstract: A method of forming an electrically conductive via. A first electrically conductive layer is formed, and a second layer is formed on the first layer. The second layer has desired barrier layer properties. A third non electrically conductive layer is formed on the second layer. A via hole is etched through the third layer, thereby exposing a portion of the second layer at the bottom of the via hole. The exposed portion of the second layer at the bottom of the via hole is redistributed so that at least a portion of the second layer is removed from the bottom of the via hole and deposited on lower portions of the sidewalls of the via hole. A fourth electrically conductive layer is formed within the via hole to form the electrically conductive via.

Abstract: A method of fabricating a trench isolation with high aspect ratio. The method comprises the steps of: providing a substrate with a trench; depositing a first isolation layer filling the trench by low pressure chemical vapor deposition; etching the first isolation layer so that its surface is lowered to the opening of the trench; depositing a second isolation layer to fill the trench without voids by high density plasma chemical vapor deposition and achieving global planarization by chemical-mechanical polishing then providing a rapidly annealing procedure. Accordingly, the present invention achieves void-free trench isolation with high aspect ratio.

Abstract: A semiconductor deposition system in accordance with the present invention includes a CMP apparatus operative to planarize an active surface of a semiconductor wafer, and a wafer cleaner for cleaning wafer after the CMP process. The wafer cleaner preferably includes a wafer rotating mechanism, a steam inlet for applying steam to the active surface of the wafer as it is rotated and a liquid inlet for simultaneously applying a liquid to the back side surface of the wafer. A method for manufacturing an integrated circuit in accordance with the present invention includes subjecting an active surface of the wafer to a plurality of processes selected from a group including deposition, patterning, doping, planarization, ashing and etching, and steam cleaning the active surface at least once before, during, and after the plurality of processes. Preferably, an aqueous vapor phase is applied to the first surface of the wafer as an aqueous liquid phase is applied to the other surface of the wafer.

Abstract: An apparatus for manufacturing semiconductor devices includes a supporter portion on which a semiconductor substrate is placed, a nozzle portion for injecting a fluid to an edge of the substrate placed on the supporter portion, a shielding cover for preventing the fluid injected from the nozzle portion from flowing to a shielding portion among a pattern-formed portion, and a shielding cover moving portion device for moving the shielding cover up and down. The apparatus makes it possible to prevent a chemical solution injected to the edge of a wafer from flowing to a shielding portion of the wafer when the wafer edge is etched.

Abstract: This device, which is used to measure pressures or accelerations for example, comprises an isolation layer (32) that holds at least one piezoresistive gauge (29). The side tangents (T) of this gauge essentially make up over 90° angles with the surface (37) of the isolation layer. The device may be created using processes of wet isotropic etching, chemical anisotropic etching or isolation material growth processes.

Abstract: A split gate FET wordline electrode structure and method for forming the same including an improved polysilicon etching process including providing a semiconductor wafer process surface comprising first exposed polysilicon portions and adjacent oxide portions; forming a first oxide layer on the exposed polysilicon portions; blanket depositing a polysilicon layer on the first exposed polysilicon portions and adjacent oxide portions; forming a hardmask layer on the polysilicon layer; carrying out a multi-step reactive ion etching (RIE) process to etch through the hardmask layer and etch through a thickness portion of the polysilicon layer to form second polysilicon portions adjacent the oxide portions having upward protruding outer polysilicon fence portions; contacting the semiconductor wafer process surface with an aqueous HF solution; and, carrying out a downstream plasma etching process to remove polysilicon fence portions.

Abstract: A method for preparing a semiconductor wafer for whole wafer backside inspection is disclosed. The frontside of the wafer is covered with a protective frontside substrate and the backside portion of the wafer is thinned using conventional techniques. The whole wafer backside is then polished and a backside substrate, preferably of transparent material is juxtaposed to the backside of the wafer, such as with an adhesive or with a frame. The frontside substrate is then removed, exposing electronic devices for device inspection. The backside of the wafer is maintained open or available to backside inspection such as emission microscopy techniques used to detect defects which emit light.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: According to one embodiment (100), a method of forming borderless contacts may include forming a composite layer over a first insulating layer (102). A contact hole may be formed through a composite layer and a first insulating layer (104). A conducting layer may then be formed (106), including within a contact hole. Portions of a conducting layer may then be removed with a composite layer as a polish stop (108), and a contact structure may be formed. A first interconnect structure and a second insulating layer may then be formed over a first insulating layer (110 and 112). A borderless contact pattern may then be etched with a composite layer as an etch stop (114).

Abstract: The invention relates to a dual masked spacer etch for improved dark current performance in imagers. After deposition of spacer material such as oxide, N-channel regions are first opened for N+ source/drain implant and P-channel regions are then opened for P+ source/drain implant. Prior to the N+ source/drain implant, the wafer receives a patterned first spacer etch. During this first spacer etch, the photosensor region is covered with resist. Prior to the P+ source/drain implant, a masked second spacer etch is performed. Again the photosensor region is protected with photoresist. In such a manner, spacers are formed on the gates of both the N-channel and P-channel transistors but in the photodiode region the spacer insulator remains.

Abstract: A method of fabricating a MOSFET device featuring a raised source/drain structure on a heavily doped source/drain region as well as on a portion of a lightly doped source/drain (LDD), region, after removal of an insulator spacer component, has been developed. After formation of an LDD region a composite insulator spacer, comprised of an underlying silicon oxide spacer component and an overlying silicon nitride spacer component, is formed on the sides of a gate structure. Formation of a heavily doped source/drain is followed by removal of the silicon nitride spacer resulting in recessing of, and damage formation to, the heavily doped source/drain region, as well as recessing of the gate structure. Removal of a horizontal component of the silicon oxide spacer component results in additional recessing of the heavily doped source/drain region, and of the gate structure.

Abstract: A wafer processing station includes an air gap chuck and a light emitter/collector assembly configured to gather light when scattered or reflected by contaminants on the wafer. The light emitter/collector assembly is driven by an actuator so that it passes across a backside surface of a wafer when supported within the chuck during wafer inspection. The wafer processing station may also include a cleaning module configured to clean the backside surface of the wafer when contaminants are discovered during wafer inspection. A computer system may be coupled to receive one or more signals from the light emitter/collector assembly that are indicative of contaminants on the backside surface of the wafer and to provide one or more control signals to the cleaning module in accordance therewith. The cleaning module may be used independently of the light emitter/collector assembly and vice-versa.

Abstract: A method for handling a thin silicon wafer including the steps of successively forming on a surface of the wafer a first protection layer, a first etch stop layer, and an external layer; forming on a surface of a support wafer a gluing layer of the same material as the external layer of the wafer, the surface of the support wafer including a plurality of pads, the respective upper portions of which are substantially planar and coplanar; fastening, by direct gluing, the external layer of the wafer and the gluing layer of the support wafer; processing the wafer to form circuits therein; depositing a second protection layer on the wafer surface which is not glued to the support wafer; and removing by an etch process the material forming the external layer of the wafer and the gluing layer of the support wafer.

Abstract: Methods for manufacturing substrates with difficult to polish features using reverse mask etching and chemical mechanical planarization techniques.

Abstract: Disclosed is a method of fabricating a polysilicon line, comprising: forming a patterned hard mask layer over a polysilicon layer; patterning the polysilicon layer to provide a hard mask-capped polysilicon line having a first width; and isotropically removing portions of the polysilicon line to a second width.

Abstract: A method and system for reducing wafer edge residue following a chemical mechanical polishing operation. A semiconductor wafer can be polished utilizing a chemical mechanical polishing apparatus. Thereafter, an acid etch operation may be performed to remove a residue, such as tungsten (W), collected on the semiconductor wafer as a result of the chemical mechanical polishing operation. A spin etch operation removes residue from the edges of the semiconductor wafer following chemical mechanical polishing of the semiconductor wafer.

Abstract: A semiconductor device that includes cobalt-silicide based contacts is disclosed, as well as a process for making the same. Combinations of alloyed layers of Co—Ti— along with layers of Co— are arranged and heat treated so as to effectuate a silicide reaction on a silicon substrate. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor devices and processes.

Abstract: A method of processing a semiconductor device is disclosed and comprises patterning a multi-layer photoresist which comprises an imaging layer overlying an underlying layer. The patterning of the resist defines an exposed portion of an underlying process layer. The method further comprises inspecting the patterned multi-layer photoresist for defects and re-working the patterned multi-layer photoresist upon a failed inspection. The re-work process comprises depositing a protection layer over the patterned multi-layer photoresist and over the exposed portion of the underlying process layer. A portion of the protection layer and the imaging layer are then removed in a concurrent manner while leaving a remaining portion of the protection layer covering the exposed portion of the underlying process layer. A remaining portion of the protection layer and the underlying layer are then removed in a concurrent manner and such removal does not adversely impact the process layer.

Abstract: An etching process using germanium hard mask (25) includes forming a dielectric layer (15) over a major surface (11) of a semiconductor substrate (10) and depositing a metallic germanium layer (22) over the dielectric layer (15). The metallic germanium layer (22) is patterned through a photo resist (24) to form the germanium hard mask (25). The dielectric layer (15) is selectively etched through the germanium hard mask (25) to form a dielectric hard mask (35), through which the semiconductor substrate (10) is subsequently etched. After forming the dielectric hard mask (35), the germanium hard mask (25) is stripped away by oxidizing the metallic germanium hard mask (25) to transform it into a layer (27) of germanium oxide and rinsing the semiconductor substrate (10) in water to remove the germanium oxide layer (27). Preferably, the germanium hard mask (25) is removed before etching the semiconductor substrate (10).

Abstract: A fabrication method for forming a semiconductor device having COB (capacitor-over-bit line) structure is provided. A lower insulating film is formed on a substrate. Bit line patterns are formed on a portion of the lower insulating film. Each of the bit line patterns comprises a conductive bit line, a lower capping strip and an upper capping strip, which are sequentially stacked. Mask-defining layer is formed on the other portion of the lower insulating film. The upper capping strips are removed by wet etching technique to form a recess region. The lower capping strips and a portion of the mask-defining layer is etched isotropically to enlarge the recess region. An insulating mask is formed in the enlarged recess region. BC (buried contact) holes are formed substantially in self-aligned manner to the bit lines by using the mask as an etch mask. According to the present invention, the unfavorable electrical contact between the storage electrodes and the bit lines can be significantly relieved.

Abstract: A process for smoothing a rough surface on a substrate, such as a diamond or silicon carbide substrate, said rough surface including protruding peak portions separated by valleys, said smoothing comprising (a) depositing a coating on said rough surface so as to adhere to and to fill at least the valleys of said rough surface, (b) mechanically polishing the thus coated rough surface so as to achieve a smooth coated surface, and (c) dry etching the smooth coated surface, such as by PACE, so as to remove the remaining coating and at least protruding peak portions of the substrate so as to achieve a smooth surface on the substrate, wherein in the mechanical polishing step (b) the coating is removed at a rate of reduction of thickness greater than the rate at which the substrate is subject to reduction of thickness by the mechanical polishing, and in the dry etching step (c) the coating and substrate are removed at substantially the same or a similar rate of reduction of thickness, and, if necessary, steps (a), (b

Abstract: A method for forming a dielectric film in a PDP includes the steps of: reducing the ambient pressure of an insulating film including a dielectric material before the ambient temperature reaches the reaction temperature of the dielectric material; introducing heated gas to increase the ambient pressure up to the atmospheric pressure while maintaining the ambient temperature at the reaction temperature; and lowering the ambient temperature down to the solidifying temperature of the insulating film while maintaining the atmospheric ambient pressure.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of first plugs contacted to a substrate by passing through a first inter-layer insulation layer; forming a second inter-layer insulation layer on the first plugs; forming a conductive pattern contacted to a group of the first plugs by etching selectively the second inter-layer insulation layer; and forming a contact hole exposing a surface of the first plug that is not contacted to the conductive pattern by etching selectively the second insulation layer with use of a dry-type and wet-type etch process, wherein an attack barrier layer is formed on between the first inter-layer insulation layer and the second inter-layer insulation layer to thereby prevent an incidence of attack to the first interlayer insulation layer contacted to the first plug during the wet-type etch process for forming the contact hole.

Abstract: A method of making a semiconductor device 10 by forming a first dielectric layer 140 on a substrate, etching through the first dielectric layer to form a trench 150 having a channel region 135 on a sidewall 160 of the trench, and laterally removing a portion of the first dielectric layer adjacent to the sidewall of the trench above the channel region for defining a source region 280 of the semiconductor device.

Abstract: Methods are disclosed for selective deposition on desired materials. In particular, barrier materials are selectively formed on insulating surfaces, as compared to conductive surfaces. In the context of contact formation and trench fill, particularly damascene and dual damascene metallization, the method advantageously lines insulating surfaces with a barrier material. The selective formation allows the deposition to be “bottomless,” thus leaving the conductive material at a via bottom exposed for direct metal-to-metal contact when further conductive material is deposited into the opening after barrier formation on the insulating surfaces. Desirably, the selective deposition is accomplished by atomic layer deposition (ALD), resulting in highly conformal coverage of the insulating sidewalls in the opening.

Abstract: A method for manufacturing a semiconductor device that forms a connection hole with high electric reliability even when the semiconductor device is designed to be highly integrated. The semiconductor device includes a lower layer wiring and an interlayer insulation film, which is formed on the lower layer wiring and has a connection hole connected with the lower layer wiring. The method includes forming the connection hole by etching the interlayer insulation film. The connection hole is formed by etching part of the lower layer wiring under a first etching condition through physical reaction in at least the vicinity of the lower layer wiring, and by etching part of the interlayer insulation film under a second etching condition that guarantees a selective ratio relative to the lower layer wiring.

Abstract: According to the present invention, there is provided a method of manufacturing a semiconductor device, where a soluble thin film which is soluble in a dissolving liquid is used. According to the method of the present invention, when a soluble thin film is formed between a film to be processed which should be patterned and a mask pattern, it becomes possible to remove the mask pattern by lifting-off. On the other hand, when the thin film is used for a dummy layer for forming an air wiring structure, the dummy layer can be removed without performing ashing using oxygen plasma.

Abstract: A method for reducing the contact resistance using plasma process tries to solve the problem that the cleaning process could not remove both the residues and oxides on the etched surface effectively. A plasma treating process is performed after the cleaning process and before any following process. Herein, the plasma treating process uses the plasma(s) to physically and/or chemically react with the etched surface. For example, inert gas plasma is used to remove these residues and the oxides, and then hydrogen plasma is used to compensate the unsaturated bonds by inducing the ions bombardment of the inert gas plasma.

Abstract: A method is provided for forming a self-aligned, selectively etched, double recess high electron mobility transistor. The method includes providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer, a channel layer, a second relatively wide band gap Schottky layer, an etch stop layer; a III-V third wide band gap layer on etch stop layer; and an ohmic contact layer on the third relatively wide band gap layer. A mask is provided having a gate contact aperture to expose a gate region of the ohmic contact layer. A first wet chemical etch is brought into contact with portions of the ohmic contact layer exposed by the gate contact aperture. The first wet chemical selectively removes exposed portions of the ohmic contact layer and underlying portions of the third relatively wide band gap layer. The etch stop layer inhibits the first wet chemical etch from removing portions of such etch stop layer.

Abstract: This invention provides a method for manufacturing an electric capacitance type acceleration sensor capable of achieving high productivity in which a semiconductor manufacturing process is used.

Abstract: A method of patterning a thin film includes a step of forming at least one strippable conductive film on a surface of a thin film to be patterned, a step of forming a mask on the at least one strippable conductive film, a step of patterning the thin film to be patterned by dry etching using the mask, and a step of removing the at least one strippable conductive film.

Abstract: The present invention provides a method of preparing a surface of a silicon wafer for formation of HSG structures. The method contemplates providing a wafer having at least one HSG template comprising polysilicon formed in BPSG, the HSG template being covered by silicon dioxide. The wafer is treated with a cleaning agent to clean the surface of the wafer. Next, the wafer is treated with a conditioning agent. The conditioning agent removes native oxide from the HSG template without excessively etching structural BPSG. Preferably, the conditioning agent also removes a thin layer of polysilicon on the HSG template. The wafer is then transferred to a process chamber for HSG formation.

Abstract: A transistor having a gate electrode with a T-shaped cross section is fabricated from a single layer of conductive material using an etching process. A two process etch is performed to form side walls having a notched profile. The notches allow source and drain regions to be implanted in a substrate and thermally processed without creating excessive overlap capacitance with the gate electrode. The reduction of overlap capacitance increases the operating performance of the transistor, including drive current.

Abstract: The invention provides a method for forming a bottle-shaped trench. A semiconductor substrate having a pad stack layer and a trench formed thereon is provided. Sidewall protective layers are then formed on the upper sidewalls of the trench. A masking layer is formed at the bottom of the trench, followed by wet etching to remove the semiconductor substrate not covered by the sidewall protective layers thus forming a bottle-shaped trench. Finally, the masking layer is removed.

Abstract: There is provided a method for fabricating a semiconductor device involving the formation of two or more oxide films having different etching properties. A multilayer-film sidewall including a first oxide film such as an NSG film, a TEOS film, or a HTO film and a second oxide film such as a BPSG film or a PSG film is formed over the side surfaces of a gate electrode. After the multilayer-film sidewall is used as an implantation mask for forming the source and drain of a MIS transistor, wet etching is performed by using an aqueous solution mixture containing a hydrofluoric acid and an inorganic acid (a hydrochloric acid, a sulfuric acid, or the like) in selectively removing the second oxide film. This increases the etching selectivity between the individual oxide films and allows the removal of only the upper-layer second oxide film.

Abstract: The present invention provides a method of preparing a surface of a silicon wafer for formation of HSG structures. The method contemplates providing a wafer having at least one HSG template comprising polysilicon formed in BPSG, the HSG template being covered by silicon dioxide. The wafer is treated with a cleaning agent to clean the surface of the wafer. Next, the wafer is treated with a conditioning agent. The conditioning agent removes native oxide from the HSG template without excessively etching structural BPSG. Preferably, the conditioning agent also removes a thin layer of polysilicon on the HSG template. The wafer is then transferred to a process chamber for HSG formation.

Abstract: A provided method for manufacturing the semiconductor device includes the steps of: forming a trench in a silicon substrate on which a silicon oxide film and a silicon nitride film are sequentially stacked; oxidizing the silicon substrate by an oxidation method of not forming nearly at all a silicon oxide film on a surface of the silicon nitride film, to form a silicon oxide film on the surface of the trench and perform pullback etching on the silicon nitride film; and performing rounding oxidation by using radical oxidation to round an edge of the surface of the trench. Therefore, it is possible to perform pullback etching on the nitride film, even in case of performing rounding oxidation by using radical oxidation.

Abstract: A method of manufacturing a capacitor having increased capacitance using a single photo-lithographic step to form two holes of different sizes in the insulating layers, wherein a first insulating layer, an etching stop layer, and a second insulating layer are sequentially deposited on a semiconductor substrate, a preliminary hole is formed by etching a predetermined portion of the second insulating layer, the preliminary hole is expanded so as to form a first hole, a second hole is formed extending from the bottom of the first hole and having an etched area narrower than an etched area of the first hole, a first conductive layer pattern is formed on the sidewalls of the first and second holes and at the bottom surface of the second hole without burying the second hole, thereby increasing the storage capacitance of the capacitor while simplifying the manufacturing process.

Abstract: A substrate treatment method including the steps of: generating droplets of a treatment liquid by mixing the treatment liquid with a gas; and causing the treatment liquid droplets generated in the liquid droplet generating step to impinge on a surface of a substrate being treated. The treatment liquid droplets have a volume median diameter of 5 &mgr;m to 40 &mgr;m.