Abstract: Embodiments of the disclosure provided herein include an apparatus and method for the plasma processing of a substrate in a processing chamber. More specifically, embodiments of this disclosure describe a biasing scheme that is configured to provide a radio frequency (RF) generated RF waveform from an RF generator to one or more electrodes within a processing chamber and a pulsed-voltage (PV) waveform delivered from one or more pulsed-voltage (PV) generators to the one or more electrodes within the processing chamber. The plasma process(es) disclosed herein can be used to control the shape of an ion energy distribution function (IEDF) and the interaction of the plasma with a surface of a substrate during plasma processing.

Abstract: An etching method includes: (a) etching a substrate including an etching target film and a mask formed on the etching target film to form a recess that reaches the etching target film; (b) forming a protective film having a thickness corresponding to one molecular layer on a surface of the recess using a first gas; (c) etching the etching target film with plasma generated from a second gas while leaving the protective film on a side wall of the recess; and (d) repeating (b) and (c).

Abstract: Substrate processing techniques are described in which an etch protection layer that is formed as part of an etch process forms in a self-limiting nature. Thus, over deposition effects are minimized, particularly in the corners of etched polygonal holes. In one embodiment, the layer being etched contains silicon and the protective layer comprises a silicon oxide (SixOy). The process may include the use of a cyclical series of etch and protective layer formation steps. In the case of a silicon oxide based protective layer, a thin protective layer of silicon oxide may be formed in a limiting and controllable manner due to the nature of the oxygen atom interaction with silicon and newly formed silicon oxide protective layers. In this manner, a polygonal hole may be formed without detrimental over deposition of a protective layer in corners of the hole.

Abstract: A method for fabricating the organic light emitting diode includes providing a substrate, forming an anode electrode layer on the substrate, forming a passivation layer on the anode electrode layer, the passivation layer having an area smaller than that of the anode electrode layer, performing ion bombardment of the anode electrode layer and the passivation layer, and removing the passivation layer.

Abstract: Enhanced compositions and methods are provided for selectively etching silicon wafers, which is particularly useful in the context of silicon wafer manufacturing and processing applications. Optionally, a formulation is provided which selectively etches silicon dioxide in preference to aluminum oxide. Optionally, a formulation and method are provided that is substantially non-aqueous.

Abstract: A method for processing a polysilicon thin film and a method for fabricating a thin film transistor are provided. The method for processing a polysilicon thin film includes: etching the polysilicon thin film using etching particles. An angle between an incident direction of the etching particles and the polysilicon thin film is larger than 0° and less than 90°.

Abstract: A process of forming an electronic device includes providing a substrate having a major surface; etching a portion of a the substrate to define a trench extending from the major surface, wherein the portion of the trench has a first width, W1, along the major surface and a second width, W2, at a bottom of the portion of the trench, and wherein the first width is greater than the second width; depositing a protective layer along side surfaces of the portion of the trench; etching the substrate to extend a depth of the trench after depositing the protective layer; and removing the protective layer.

Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.

Abstract: Provided is a plasma etching method increasing the selectivity of a silicon nitride film in relation to the silicon oxide film or silicon functioning as a base. In a plasma etching method setting a pressure in a processing container as a predetermined level by exhausting a processing gas while supplying the processing gas into the processing container, generating plasma by supplying external energy to the processing container, and setting a bias applied to a holding stage holding a substrate in the processing container as predetermined value to selectively etch the silicon nitride film with respect to a silicon and/or silicon oxide film, the processing gas includes a plasma excitation gas, a CHxFy gas, and at least one oxidizing gas selected from the group consisting of O2, CO2, CO, and a flow rate of the oxidizing gas with respect to the CHxFy gas is set to be 4/9 or greater.

Abstract: In production of a mold having a deposited film on the surface thereof as a mold release layer, a quartz substrate plasma etched employing an etching gas that includes a sedimentary gas to form a pattern of protrusions and recesses having a desired shape in a structure constituted by the quartz substrate and a mask layer, while a deposited film constituted by sediment of the sedimentary gas is formed along the pattern of protrusions and recesses. The deposited film becomes the mold release layer. Thereby, throughput of mold production is improved in the production of molds having deposited films as mold release layers on the surfaces thereof.

Abstract: The present disclosure relates to a gas field ion source comprising a housing, an electrically conductive tip arranged within the housing, a gas supply for supplying one or more gases to the housing, wherein the one or more gases comprise neon or a noble gas with atoms having a mass larger than neon, and an extractor electrode having a hole to permit ions generated in the neighborhood of the tip to pass through the hole. A surface of the extractor electrode facing the tip can be made of a material having a negative secondary ion sputter rate of less than 10?5 per incident neon ion.

Abstract: The present invention is a method for producing a light-emitting body containing silicon fine particles that emit visible light, comprising: a baking step of baking a mixture containing a silicon source and a carbon source in an inert atmosphere; a rapid cooling step of rapidly cooling a gas generated by baking the mixture to obtain a composite powder; and a removing step of removing a portion of the composite powder, wherein in the removing step, a portion of silicon monoxide and a portion of silicon dioxide are removed from the composite powder containing silicon fine particles, silicon monoxide, and silicon dioxide.

Abstract: Disclosed is an ashing apparatus and its method of manufacture wherein decrease in processing efficiency is suppressed. Specifically, a shower plate is arranged to face a substrate stage on which a substrate is placed, and diffuses oxygen radicals supplied into a chamber. A metal blocking plate is arranged between the shower plate and the substrate stage and has a through hole through which oxygen radicals pass. In addition, the metal blocking plate has a first layer, which is made of a metal same as the one exposed in the substrate, on the surface facing the substrate.

Abstract: A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.

Abstract: Out-of-plane microneedle manufacturing process comprising the simultaneous creation of a network of microneedles and the creation of a polygonal shaped hat (2) above each microneedle (1) under formation, said process comprising the following steps: providing bridges (3) between the hats (3), maintaining the bridges (3) during the remaining microneedle manufacturing steps, removing the bridges (3), together with the hats (2), when the microneedles (1) are formed.

Abstract: A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device.

Abstract: A method of forming a slanted field plate including forming epitaxy for a FET on a substrate, forming a wall near a drain of the FET, the wall comprising a first negative tone electron-beam resist (NTEBR), depositing a dielectric over the epitaxy and the wall, the wall causing the dielectric to have a step near the drain of the FET, depositing a second NTEBR over the dielectric, wherein surface tension causes the deposited second NTEBR to have a slanted top surface between the step and a source of the FET, etching anisotropically vertically the second NTEBR and the dielectric to remove the second NTEBR and to transfer a shape of the slanted top surface to the dielectric, and forming a gatehead comprising metal on the dielectric between the step and the source of the FET, wherein the gatehead forms a slanted field plate.

Abstract: Disclosed is a method of forming a dummy gate in manufacturing a field effect transistor. The method includes a first process of exposing a workpiece having a polycrystalline silicon layer to plasma of HBr gas, and a second process of further exposing the workpiece to the plasma of HBr gas after the first process. The first process includes etching the polycrystalline silicon layer to form a dummy semiconductor part having a pair of side surfaces from the polycrystalline silicon layer, and forming a protection film based on a by-product of etching on the pair of side surfaces in such a manner that the thickness of the protection film becomes smaller toward a lower end of the dummy semiconductor part.

Abstract: Techniques for forming a three dimensional (3D) feature on a substrate are disclosed. In one exemplary embodiment, the technique may be realized as a method comprising: forming a resist structure on the substrate, the resist structure having a first resist portion with a first thickness, a second resist portion with a second thickness, and a third resist portion with a third thickness, where the first thickness may be less than the second thickness, and where the second thickness may be less than the third thickness; implanting charged particles into the substrate through the first and second resist portions and forming an implanted region in the substrate; and etching the substrate to form the 3D feature on the substrate.

Abstract: A method of taper-etching a layer to be etched that is made of a dielectric material and has a top surface. The method includes the steps of: forming an etching mask with an opening on the top surface of the layer to be etched; and taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces intersecting at a predetermined angle is formed in the layer to be etched. The step of taper-etching employs an etching gas containing a first gas contributing to the etching of the layer to be etched and a second gas contributing to the deposition of a sidewall protective film, and changes, during the step, the ratio of the flow rate of the second gas to the flow rate of the first gas so that the ratio increases.

Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias.

Abstract: A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side openings are formed in the substrate to different depths relative one another. Walls that are laterally between the side-by-side openings are removed to form a larger opening having a non-vertical sidewall surface where the walls were removed in at least one straight-line vertical cross-section that passes through the sidewall surface orthogonally to the removed walls.

Abstract: An integrated circuit structure includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. The integrated circuit structure further includes at least a conductive layer formed in the hard mask layer and a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall.

Abstract: Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) device are provided. In one embodiment, the MEMS device fabrication method includes forming a via opening extending through a sacrificial layer and into a substrate over which the sacrificial layer has been formed. A body of electrically-conductive material is deposited over the sacrificial layer and into the via opening to produce an unpatterned transducer layer and a filled via in ohmic contact with the unpatterned transducer layer. The unpatterned transducer layer is then patterned to define, at least in part, a primary transducer structure. At least a portion of the sacrificial layer is removed to release at least one movable component of the primary transducer structure. A backside conductor, such as a bond pad, is then produced over a bottom surface of the substrate and electrically coupled to the filled via.

Abstract: A method of manufacturing a waveguide eliminates a prior art reflow step and introduces certain new steps that permit fabricating of an ultra-low loss waveguide element on a silicon chip. The ultra-low loss waveguide element may be adapted to fabricate a number of devices, including a wedge resonator and a ultra-low loss optical delay line having an extended waveguide length.

Abstract: A seed layer comprises a bottom seed layer portion formed on the bottom of a via opening, a sidewall seed layer portion formed on an upper portion of the sidewall of the via opening and a corner seed layer portion formed between the bottom seed layer portion and the sidewall seed layer portion. The sidewall seed layer portion is of a first thickness. The corner seed layer portion is of a second thickness and the second thickness is greater than the first thickness.

Abstract: A method of etching silicon oxide from a multiple trenches is described which allows more homogeneous etch rates among trenches. The surfaces of the etched silicon oxide within the trench following the etch may also be smoother. The method includes two dry etch stages followed by a sublimation step. The first dry etch stage removes silicon oxide quickly and produces large solid residue granules. The second dry etch stage remove silicon oxide slowly and produces small solid residue granules in amongst the large solid residue granules. Both the small and large solid residue are removed in the ensuing sublimation step. There is no sublimation step between the two dry etch stages.

Abstract: A method of taper-etching a layer to be etched that is made of a dielectric material and has a top surface. The method includes the steps of: forming an etching mask with an opening on the top surface of the layer to be etched; and taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces intersecting at a predetermined angle is formed in the layer to be etched. The step of taper-etching employs an etching gas containing a first gas contributing to the etching of the layer to be etched and a second gas contributing to the deposition of a sidewall protective film, and changes, during the step, the ratio of the flow rate of the second gas to the flow rate of the first gas so that the ratio increases.

Abstract: A method of etching a substrate is described. In one embodiment, the method includes preparing a mask layer having a pattern formed therein on or above at least a portion of a substrate, etching a feature pattern into the substrate from the pattern in the mask layer using a gas cluster ion beam (GCIB), and controlling a sidewall profile of the feature pattern etched into the substrate by adjusting a beam divergence of the GCIB.

Abstract: A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed.

Abstract: The present invention discloses a method of fabricating a semiconductor device. In the present invention, after the formation of a photo-resist mask on a substrate, the photo-resist is subjected to a plasma pre-treatment, and then etch is conducted. With the plasma pre-treatment, a line width roughness of a linear pattern of the photo-resist can be improved, and thus much better linear patterns can be formed on the substrate during the subsequent etching steps.

Abstract: The present invention aims to prevent decreases in etching rate due to adhesion of an etched film to a substrate holder. A method of manufacturing a magnetic recording medium includes: forming a first film on a substrate holder not yet having a substrate mounted thereon; mounting a substrate on the substrate holder having the first film formed thereon, the substrate having a resist layer formed on a multilayer film including a magnetic film layer, the resist layer having a predetermined pattern; and processing the magnetic film layer into a shape based on the predetermined pattern by performing dry etching on the substrate. The first film is a film that is not etched as easily as the films in the multilayer film to be removed by the dry etching.

Abstract: A method of bevel edge etching a semiconductor substrate having exposed copper surfaces with a fluorine-containing plasma in a bevel etcher in which the semiconductor substrate is supported on a semiconductor substrate support comprises bevel edge etching the semiconductor substrate with the fluorine-containing plasma in the bevel etcher; evacuating the bevel etcher after the bevel edge etching is completed; flowing defluorinating gas into the bevel etcher; energizing the defluorinating gas into a defluorination plasma at a periphery of the semiconductor substrate; and processing the semiconductor substrate with the defluorination plasma under conditions to prevent discoloration of the exposed copper surfaces of the semiconductor substrate upon exposure, the discoloration occurring upon prolonged exposure to air.

Abstract: A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate.

Abstract: A method for etching a conductive layer through a mask with wider and narrower features is provided. A steady state etch gas is flowed. A steady state RF power is provided to form a plasma from the etch gas. A pulsed bias voltage is provided during the steady state etch gas flow, wherein the pulsed bias voltage has a frequency between 1 to 10,000 Hz. Wider and narrower features are etched into the conductive layer using the plasma formed from the etch gas.

Abstract: A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.

Abstract: A method for forming a fine pattern having a variable width by simultaneously using an optimal focused electron beam and a defocused electron beam in a light exposure process Includes, after forming a first film on a substrate, forming a first film pattern including a first level area and a second level area having different distances from the substrate by changing a profile of an upper surface of the first film. A photoresist film having a first area covering the first level area and a second area covering the second level area is formed. To simultaneously light-expose the first area and the second area with the same width, a light exposure condition, in which an optimal focused electron beam is eradiated on the first area and a defocused electron beam is eradiated on the second area, is applied.

Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias.

Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening.

Abstract: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.

Abstract: A method for manufacturing a component having a through-contact includes: providing a substrate; forming an insulating layer on the substrate; structuring the insulating layer, the insulating layer being removed at least in a predetermined trenching area surrounding a selected substrate area; performing an etching process in which the structured insulating layer functions as a mask to remove substrate material in the trenching area and to create a trench structure surrounding the selected substrate area; and forming a metallic layer on the insulating layer, the metallic layer sealing the trench structure.

Abstract: A method for manufacturing a multilayer printed wiring board including forming a multilayer printed wiring board structure comprising first and second buildup portions, the first buildup portion including insulating layers, conductor layers and first viaholes electrically connecting the conductor layers through the insulation layers such that the first viaholes are formed in the insulating layers, respectively, the second buildup portion including insulating layers, conductor layers and second viaholes electrically connecting the conductor layers through the insulation layers such that the first viaholes are tapered toward the second viaholes, and the second via holes are tapered toward the first viaholes. The viaholes are formed by plating openings formed after lamination of respective ones of the insulating layers of the buildup portions, and each insulating layer in the buildup portions is about 100 ?m or less in thickness.

Abstract: In a process for forming trenches having M different widths in a substrate, a passivation step and an etching step are alternately performed. The passivation step includes depositing a passivation layer on a bottom of the trenches by converting gas introduced in a chamber into plasma. The etching step includes removing the passivation layer on the bottom of the trenches and applying reactive ion etching to the bottom to increase a depth of the trenches. The etching step further includes setting energy for the reactive ion etching to a predetermined value when the passivation layer on the bottom of the trench having the Nth smallest width is removed. The value allows the etching amount of the trench having the Nth smallest width to be equal to or greater than the etching amount of the trench having the (N+1)th smallest width.

Abstract: In the manufacturing method of a GOLD structured TFT having a gate electrode of double-layered structure, in which, compared to a second layer gate electrode, the first layer gate electrode is thinner in film thickness and longer in dimension of the channel direction, by controlling the density of the photo-absorbent contained in a positive type resist such as diazonaphthoquinone (DNQ)-novolac resin series, the taper angle of the side wall is controlled to a desired angle range so that the angle thereof becomes smaller. Owing to this, it is possible to control the retreat amount of the resist when carrying out dry etching and the dimension of Lov, area to a desired dimensional range so that the dimension thereof becomes larger.

Abstract: A method for forming a fine pattern having a variable width by simultaneously using an optimal focused electron beam and a defocused electron beam in a light exposure process Includes, after forming a first film on a substrate, forming a first film pattern including a first level area and a second level area having different distances from the substrate by changing a profile of an upper surface of the first film. A photoresist film having a first area covering the first level area and a second area covering the second level area is formed. To simultaneously light-expose the first area and the second area with the same width, a light exposure condition, in which an optimal focused electron beam is eradiated on the first area and a defocused electron beam is eradiated on the second area, is applied.

Abstract: The present invention provides a method (80) for manufacturing a semiconductor tip. The method comprises obtaining (81) a substrate provided with a layer of tip material, providing (82) a doping profile in the layer of tip material, the doping profile comprising a tapered-shaped region of a first dopant concentration, undoped or lightly doped, e.g. having a dopant concentration of 1017 cm?3 or lower, surrounded by a region of a second dopant concentration, highly doped, e.g. having a dopant concentration above 1017 cm?3, the first dopant concentration being lower than the second dopant concentration, and isotropically etching (83) the layer of tip material by using an etch chemistry for which the etch rate of tip material with the second dopant concentration is substantially higher than the etch rate of the tip material with the first dopant concentration.

Abstract: A method for forming a deep trench in a semiconductor device includes: forming a hard mask over a substrate, forming a hard mask pattern over the substrate through etching the hard mask to thereby expose an upper portion of the substrate, forming a first trench through a first etching the exposed substrate using a gas containing bromide and a gas containing chloride and forming a second trench through a second etching the first trench using of a gas containing sulfur and fluorine, wherein a depth of the second trench is deeper than a depth of the first trench.

Abstract: A semiconductor light emitting device has a light emitting element, a first electrode layer, a second electrode layer, a seed electrode layer and a plated layer. The light emitting element has a nitride-based III-V compound semiconductor on a substrate. The light emitting element having a light extraction surface. The first electrode layer on the light extraction surface. The second electrode layer is provided on a surface opposite to the light extraction surface of the light emitting element. The seed electrode layer is configured to cover the entire surface of the second electrode layer. The plated layer is provided on the seed electrode layer. The light emitting element has a light emitting layer, a first conductive type semiconductor layer, and a second conductive type semiconductor layer.

Abstract: A thin film transistor includes a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region; a gate insulating layer disposed on the semiconductor layer and on the substrate; and a gate electrode disposed on the insulating layer over the channel region, wherein the semiconductor layer includes tapered edge portions with a taper angle defined between the tapered edge portions and a surface of the substrate is less than about 30 degrees.

Abstract: Many current micromachining devices are integrated with materials such as very thick layer of polyimide (10 to 100 um) to offer essential characteristics and properties for various applications; it is inherently difficult and complicated to provide reliable metal interconnections between different levels of the circuits. The present invention is generally related to a novel micromachining process and structure to form metal interconnections in integrated circuits or micromachining devices which are incorporated with thick polyimide films. More particularly, the embodiments of the current invention relates to formation of multi-step staircase structure with tapered angle on polyimide layer, which is therefore capable of offering superb and reliable step coverage for metallization among different levels of integrated circuits, and especially for very thick polyimide layer applications.