Abstract: A semiconductor film serving as an active region of a thin film transistor and an upper oxide film protecting the semiconductor film are dry etched to form the active region. In this case, a fluorine-based gas is used as the etching gas, and the etching gas is switched from the fluorine-based gas to a chlorine-based gas at a point of time when a lower oxide film as an underlying film of the semiconductor film is exposed. As the fluorine-based gas, a mixed gas of CF4 and O2 is used, and suitably, a gas ratio of CF4 and O2 in the mixture gas is set at 1:1, and the dry etching is performed therefor. By this etching, a side face of a two-layer structure of the semiconductor film and upper oxide film is optimally tapered, and a crack or a disconnection is prevented from being occurring in a film crossing over the two-layer structure.

Abstract: A method for forming a uniform bottom electrode in a trench of a trench capacitor. A semiconductor substrate has a dense trench area and a less dense trench area with a plurality of trenches formed in both areas respectively. A hard mask layer is formed on the semiconductor substrate, and the trenches are filled with the mask layer. The hard mask layer is etched at an angle until the dense trench area and the less dense trench area in the semiconductor substrate are exposed to leave the hard mask layer in the trenches. Finally, the hard mask layers in the trenches are etched, and a uniform thickness of the hard mask layer in each trench is achieved.

Abstract: A manufacturing method for an optical integrated circuit including a spatial reflection type structure having a perpendicular end surface and an inclined surface formed in an optical waveguide layer. The manufacturing method includes the steps of applying a first photoresist to the upper surface of the optical waveguide layer, removing the first photoresist except a portion corresponding to the inclined surface, and heating the first preferred embodiment to a given temperature to melt the first photoresist at least partially and deform the first photoresist by surface tension, thereby forming a first mask having an inclined shape.

Abstract: The present invention relates to a scribing method for wafers (11), wherein a defined beam (12) is directed onto the wafer (11) by means of a beam generator means (10) so as to remove some wafer material from a wafer region. The invention also relates to a wafer-scribing device including a wafer mount (31) and a beam generator means (10) by means of which at least one defined beam can be directed onto the wafer (11). The inventive method is distinguished by the by the further step of generating a first radiation pulse having a predeterminable energy density and used to create a comparatively deep pit (18) in the wafer (11). The inventive wafer scribing means is distinguished by the provision that a radiation pulse can be generated by means of which a comparatively deep pit (18) can be created in the wafer (11).

Abstract: Transistor gate linewidths can be made to be effectively smaller by etching a notch at the bottom of the gate to reduce the effective linewidth. This can be done by etching at a layer interface, such as a silicon-germanium interface in an over-etch step.

Abstract: A method for reducing RIE lag (reaction ion etching lag) in a deep silicon etching process forming trench openings is described. The method can be carried out by either a photolithographic means wherein trench openings of the same planar area are patterned on the silicon substrate, or by a pressure means in which the chamber pressure during the reactive ion etching process is increased to reduce or eliminate the RIE lag effect. By increasing the chamber pressure at least 50% from that normally incurred in a reactive ion etching process, and preferably at least 100%, the RIE lag effect can be completely eliminated resulting in an inversed RIE lag in which a larger etch depth is achieved for the trench openings that have the smallest width.

Abstract: This invention provides a directional ion etching process for making nano-scaled angled features such as may be used, for example, in liquid crystal displays and or nanoimprinting templates. In a particular embodiment a semiconductor wafer substrate is prepared with at least one layer of material. A photoresist is applied, masked, exposed and developed. Anisotropic ion etching at a high angle relative to the wafer is performed to remove portions of the non protected material layer. The remaining photoresist caps shadow at least a portion of the material layer, and as the ion etching is performed at an angle, the protected portions of the material layer also appear at an angle.

Abstract: A method of fabricating a device having a desired non-planar surface or profile and device produced thereby are provided. A silicon wafer is first coated with silicon nitride, patterned, and DRIE to obtain the desired etch profile. Silicon pillars between trenches are then etched using an isotropic wet etch, resulting in a curved well. The wafer is then oxidized to ?2 ?m to smooth the surface of the well, and to protect the well from an ensuing planarization process. The nitride is then selectively removed, and the wafer surface is planarized by removing the Si left in the field regions using either a maskless DRIE or CMP. Finally, the oxide is etched away to produce a wafer with a curved surface.

Abstract: A transistor can include an integrated circuit substrate including spaced apart isolation regions therein and an active region therebetween. A recess is formed in the active region and extends between the spaced apart isolation regions and has a bottom and opposing side wall ends that are defined by facing portions of the spaced apart isolation regions. An electrically insulating layer is formed on the bottom of the recess. A conductive material is formed in the recess on the electrically insulating layer to provide a gate electrode.

Abstract: A method is provided for manufacturing a semiconductor device on a semiconductor substrate using a dielectric as a bottom anti-reflective coating for formation of a photoresist contact opening which is used to enlarge the Final Inspection Critical Dimension (FICD) of the conductive contact. A high selectivity etch is used to form a tapered contact.

Abstract: A method of forming a polycrystalline silicon layer includes: disposing a mask over the amorphous silicon layer, the mask having a plurality of transmissive regions, the plurality of transmissive regions being disposed in a stairstep arrangement spaced apart from each other in a first direction and a second direction substantially perpendicular from the first direction, each transmissive region having a central portion and first and second side portions that are adjacent to opposite ends of the central portion along the first direction, and wherein each of the portions has a length along the first direction and a width along the second direction, and wherein the width of first and second portions decreases away from the central portion along the first direction; irradiating a laser beam onto the amorphous silicon layer a first time through the mask to form a plurality of first irradiated regions corresponding to the plurality of transmissive regions, each first irradiated region having a central portion, and

Abstract: A semiconductor wafer having a via test structure is provided which includes a semiconductor substrate having a plurality of semiconductor devices. A dielectric layer deposited over the semiconductor substrate has second and fourth channels unconnected to the plurality of semiconductor devices. A via dielectric layer deposited over the channel dielectric layer has first and second vias and third and fourth vias respectively open to opposite ends of the second channel and the fourth channel. A second dielectric layer over the via dielectric layer has first, third, and fifth channels respectively connected to the first via, the second and third vias, and the fourth via. The first channel, the first via, the second channel, the second via, the third channel, the third via, the fourth channel, the fourth via, and the fifth channel are connected in series and the first and fifth channel are probed to determine the presence or absence of voids in the vias.

Abstract: Disclosed herein is a method of etching deep trenches in a substrate which utilizes the overlying mask structure to achieve a trench having a positive tapered sidewall angle of less than about 88°. The method employs the successive etching of a lateral undercut in the substrate beneath a masking material, while at the same time etching vertically downward beneath the mask. The coordinated widening of the lateral undercut at the top of the trench, while vertically extending the depth of the trench, is designed to provide the desired trench sidewall taper angle.

Abstract: A semiconductor device is provided with a semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film and having a portion increasing upward in the length along a gate length direction, a side wall formed on a side surface of the gate electrode so as to be covered behind a top part of the gate electrode as seen in plan view, and an interlayer insulation film covering the gate electrode. The side wall is in contact with the interlayer insulation film.

Abstract: A method for forming a spacer layer adjoining a substantially vertical first sidewall of a topographic feature within a microelectronic product employs an anisotropic etching of a reentrant spacer material layer formed upon the topographic feature. The spacer layer is formed at least in part with a substantially vertical second sidewall laterally separated from the substantially vertical first sidewall. The method is useful for forming spacer layers within field effect transistor devices.

Abstract: Shallow trench isolation methods and corresponding structures are disclosed. According to one embodiment (900) a nitride layer (1006), having an opening (1014), is formed over a silicon substrate (1002). The portion of the substrate (1002) below the opening (1014) is oxidized to form a substrate consuming rounding oxide layer (1018). The formation of the rounding oxide layer (1018) results in rounded edges in the substrate (1002). An isotropic, or alternatively, an anisotropic rounding oxide etch removes the rounding oxide layer (1018) to expose the substrate (1002). A trench (1026) can be formed by applying a silicon etch using the nitride layer (1006) as an etch mask. The trench (1026) can be subsequently filled with a deposited trench isolation material (1030).

Abstract: A method for etching trenches in a substrate secures a wafer to an electrode in a plasma chamber and heats the wafer to a temperature of greater than 200 degrees Celsius. The wafer is exposed to a reactive plasma to etch trenches into the substrate of the wafer with minimal redeposition of etch by-products to avoid pinching off the trench and to promote further etching.

Abstract: A semiconductor wafer comprises an SOI comprising a device layer on an oxide layer supported on a handle layer. Micro-mirrors are formed in the device layer, and access bores extend through the handle layer and the oxide layer to the micro-mirrors for accommodating optical fibers to the micro-mirrors. The access bores are accurately aligned with the micro-mirrors, and the access bores are accurately formed of circular cross-section. Each access bore comprises a tapered lead-in portion extending to a parallel portion. The diameter of the parallel portion is selected so that the optical fibers are a tight fit therein for securing the optical fibers in alignment with the micro-mirrors. The tapered lead-in portions of the access bores are formed to a first depth by a first dry isotropic etch for accurately forming the taper and the circular cross-section of the tapered lead-in portions.

Abstract: The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, the process comprising the following steps: a) anisotropic etching of the top part of the gate material layer not masked by the gate mask, this etching step leaving the bottom part of the gate material layer and leading to the formation of a deposit composed of etching products on the etching sides resulting from the anisotropic etching, b) treatment of the deposit composed of etching products, to make a protection layer reinforced against subsequent etching of the gate material, c) etching of the bottom part of the gate material layer as far as the gate isolation layer, this etching comprising isotropic etching of the gate material layer to make the gate shorter at the bottom than at the top.

Abstract: In the manufacturing method of a GOLD structured TFT having a gate electrode of double-layered structure, in which, compared to a second layer gate electrode, the first layer gate electrode is thinner in film thickness and longer in dimension of the channel direction, by controlling the density of the photo-absorbent contained in a positive type resist, which contains a photo-absorbent of diazonaphthoquinone (DNQ)-novolac resin series, the taper angle of the side wall is controlled to a desired angle range so that the angle thereof becomes smaller. Owing to this, it is possible to control the retreat amount of the resist when carrying out dry etching and the dimension of Lov area to a desired dimensional range so that the dimension thereof becomes larger.

Abstract: A process for forming a shallow trench isolation (STI), region in a strained silicon layer and in a top portion of an underlying, relaxed silicon-germanium layer, has been developed. The process features definition of a first opening in a silicon nitride stop layer via an anisotropic RIE procedure, using a photoresist shape as an etch mask. A following RIE procedure using HBr—Cl2—O2 as an etchant is next performed, defining a second opening, or a shallow trench shape opening in a strained silicon layer and in a top portion of the underlying relaxed silicon-germanium layer.

Abstract: A method for forming a via in a damascene process. In one embodiment, the present method comprises depositing a material into a via formed using a damascene process. More particularly, in one embodiment, the material which is comprised of a substantially conformal material which has an etch selectivity with respect to the substrate into which the via is formed. Furthermore, in this embodiment, the material is deposited along the sidewalls and the base of the via. Next, the present embodiment etches material such that the via is formed having a profile conducive to the adherence of overlying material thereto. In this embodiment, the etching of the material is performed without substantially etching the substrate into which the via is formed. In so doing, the present embodiment creates a via in a damascene process which allows for the formation of a metallized interconnect which is substantially free of voids.

Abstract: A method for fabricating a semiconductor structure includes providing a semiconductor substrate and a sacrificial layer between a layer to be patterned and a resist layer, patterning the resist layer to form a patterned resist layer; selectively etching the sacrificial layer with a taper angle so as to reduce the dimensions within the sacrificial layer in the etching direction which are prescribed by depressions situated in the patterned resist layer, and selectively etching the layer to be patterned using the sacrificial layer etched with a taper angle as a mask. The present invention also relates to a method for fabricating a semiconductor structure in which two sacrificial layers are used.

Abstract: The degradation of deposited low dielectric constant interlayer dielectrics and gap fill layers, such as HSQ layers, during formation of contacts/vias is significantly reduced or prevented by employing a plasma containing CF4+H2O to remove the photoresist mask and cleaning the contact/via opening after anisotropic etching. The CF4+H2O plasma also enables rapid photoresist stripping at a rate of about 10 to about 20 KÅ/min. Embodiments include photoresist stripping and cleaning the contact/via opening with a CF4+H2O plasma to prevent reduction of the number of Si—H bonds of an as-deposited HSQ layer below about 70%.

Abstract: A method for making a semiconductor device is described. That method includes forming a sacrificial layer on a substrate, then forming a layer of photoresist on the sacrificial layer. After the photoresist layer is patterned, to form a patterned photoresist layer that has a first opening, a first part of the sacrificial layer is removed to generate an etched sacrificial layer that has a tapered etch profile. A second part of the sacrificial layer is then removed to generate an etched sacrificial layer that has a second opening that is substantially smaller than the first opening.

Abstract: In one illustrative embodiment, the method comprises forming a gate insulation layer above a substrate, forming a layer of polysilicon above the gate insulation layer, implanting a dopant material into the layer of polysilicon, forming an undoped layer of polysilicon above the doped layer of polysilicon and performing an etching process on the undoped layer of polysilicon and the doped layer of polysilicon to define a gate electrode having a width at an upper surface that is greater than a width of the gate electrode at a base of the gate electrode. In further embodiments, the method comprises forming a layer of refractory metal above the gate electrode and performing at least one heating process to form a metal silicide region on the gate electrode structure.

Abstract: A process for the fabrication of a ferrocapacitor comprising depositing a first mask element 7 over a structure having a bottom electrode 1, a ferroelectric layer 3 and a top electrode 5. RIE etching is performed to remove portions of the top electrode 5 and the ferroelectric layer 3. Then a second hard mask element 9 is deposited over the first hardmask element. The second hard mask element is rounded by an etch back process, and its taper angle is controlled to be in the range 75-87°. A second RIE etching process is performed to remove portions of the bottom electrode 1. Due to the rounding of the second hard mask elements 9 low residues are formed on the sides of the etched bottom electrode 1.

Abstract: We have developed a method of selectively etching silicon nitride relative to oxides in a high density plasma chamber of the kind presently known in the art. We have obtained selectivities for silicon nitride:silicon oxide in the range of about 15:1 to about 24:1. We have employed the method in the etching of silicon nitride spacers for sub 0.25 &mgr;m devices, where the spacers are adjacent to exposed oxides during the etch process. We have obtained silicon nitride spacers having rounded top corners and an extended “tail” toward the bottom outer edge of the nitride spacer. The method employs a plasma source gas which typically includes SF6, HBr, N2 and optionally, O2. Typically, the pressure in the etch chamber during etching is at least 35 mTorr and the substrate temperature is about 20° C. or less.

Abstract: A method of forming a trench in a semiconductor device includes forming a polish stop layer on a semiconductor substrate. The polish stop layer and the semiconductor substrate are then etched to form a trench. The semiconductor substrate is etched to a predetermined depth. Also, etching is performed such that ends of the polish stop layer adjacent to the trench are rounded. Next, an insulation layer that fills the trench is formed.

Abstract: In the manufacturing method of a GOLD structured TFT having a gate electrode of double-layered structure, in which, compared to a second layer gate electrode, the first layer gate electrode is thinner in film thickness and longer in dimension of the channel direction, by controlling the density of the photo-absorbent contained in a positive type resist, which contains a photo-absorbent of diazonaphthoquinone (DNQ)-novolac resin series, the taper angle of the side wall is controlled to a desired angle range so that the angle thereof becomes smaller. Owing to this, it is possible to control the retreat amount of the resist when carrying out dry etching and the dimension of Lov area to a desired dimensional range so that the dimension thereof becomes larger.

Abstract: A plasma processing method that makes it possible to remove a photoresist film and fence portion while maintaining a specific shape of the opening is provided. After a wafer W is placed on a lower electrode 106 provided inside a processing chamber 102 of an ashing apparatus 100, power with its frequency set at 60 MHz and its level set at 1 kW and power with its frequency set at 2 MHz and its level set at 250 W are respectively applied to an upper electrode 122 and the lower electrode 106. A processing gas induced into the processing chamber 102 is raised to plasma, a photoresist film 208 at the wafer W is ashed and, at the same time, fence portion 214 formed around the opening of a via hole 210 during the etching process is removed. The level of the power applied to the lower electrode 106 is set equal to or lower than 10 W before the photoresist film 208 is completely removed.

Abstract: A method for making a semiconductor device is described. That method includes forming a sacrificial layer on a substrate, then forming a layer of photoresist on the sacrificial layer. After the photoresist layer is patterned, to form a patterned photoresist layer that has a first opening, part of the sacrificial layer is removed to generate an etched sacrificial layer that has a second opening that is substantially smaller than the first opening.

Abstract: A lower portion of an interlayer insulating film is formed contiguous with a semiconductor wafer. The lower portion has a high impurity concentration and a high etching rate. An upper portion of an interlayer insulating film is formed over the lower portion apart from the semiconductor wafer. The upper portion has a low impurity concentration and a low etching rate. A plurality of contact holes are formed through the interlayer insulating film by anisotropic etching. The bottom portion of each contact hole is expanded by isotropic etching, and a contact is formed in the contact hole. Thus, a satisfactory contact is formed in a hole of a large aspect ratio.

Abstract: A method of fabricating a polysilicon film by an excimer laser annealing process is introduced. First, an amorphous silicon film is deposited on a substrate composed of glass. The amorphous silicon film includes a first region, which is located in the center, with a first thickness, and a second region, which is located in the periphery, with a slant sidewall. The thickness of the amorphous silicon film is measured so as to obtain the profile of the sidewall in the second region. According to the profile of the sidewall, a pre-cursor region is determined for performing an excimer laser annealing process wherein a second thickness in the boundary of the pre-curser regionis smaller than the first thickness so as to increase area of produced polysilicon film.

Abstract: The present invention provides improved controllability of the lateral etch encroachment of silicon under the spacer, in light of the fact that the exemplary method, in accordance with the present invention, comprises the step of implanting neutral ions such as Ge or Ar into the source/drain regions. The implantation creates an amorphous silicon surface, and leaves a laterally extended amorphous layer under the spacer and a well defined amorphous/crystalline interface. The etch of silicon then extends laterally underneath the spacer, due to the higher etch rate of amorphous silicon and abrupt interface between amorphous and crystalline silicon.

Abstract: A method for fabricating a pair of patterned target layers within a microelectronic product employs a pair of patterned etch mask layers of different thicknesses. The pair of patterned etch mask layers of different thicknesses provides that the pair of patterned target layers may be formed with individual linewidth control, absent fabrication or modification of a photomask to realize the same result. The method is particularly useful for fabricating pair of gate electrodes for use within CMOS devices.

Abstract: A masking material (14) is formed on a foundation layer (12) and a substrate (10). A mask (16) is disposed onto the masking material (14) where a trench (26) is desired to be formed. An etch step removes all of the masking material (14) except at regions where the mask (16) was formed leaving a protruding portion (18) with an opening (20) on either side. An epi layer (24), is grown on the foundation layer (12) adjacent to the protruding portion (18) in the opening (20). A wet oxide etch process is used to remove the protruding portion (18) leaving a trench (26) formed in the epi layer (24). To complete the process, a silicon wet etch process is used to round off the corners at an edge (28) of the trench (26).

Abstract: Structure and method for filling an opening in a semiconductor structure that is less susceptible to the formation of voids. A first layer of a first material is formed over the layer in which the opening is to be formed, and a faceted opening is formed in the first layer. The opening in the underlying layer is subsequently formed, and the material that is to fill the opening is deposited over the faceted opening and into the opening of the underlying layer.

Abstract: An active-matrix type organic EL display which uses transistors with less variation of characteristics (transistors in which active layer is a single crystal semiconductor) is made on a large area of a transparent base board at low cost. Plural unit of fine construction are formed on a silicon wafer in rows. This unit includes a driving element (switching transistor 34, driving transistor 37, capacity 36) of organic EL element (pixel) 35. Unit block 39 is produced by dividing this silicon wafer. This unit block 39 is disposed at a predetermined position of glass base board 52 (display base board). The driving element of each pixel 35 is connected by signal line 31, power supply line 32, scanning line 33, and capacity line 38.

Abstract: When a hole pattern is formed on a film to be processed, a matching deviation margin at a lithography step is reserved by making a diameter of a bottom of a hole substantially equal to a diameter of an aperture of the hole. The method for manufacturing the semiconductor apparatus includes the steps of: forming a (first) mask material film on a film to be processed; forming a tapered open pattern on the (first) mask material film; and etching the film to be processed by using the (first) mask material film as a mask.

Abstract: A method for fabricating field emitters from a conductive or semiconductive substrate. A layer of low work function material may be formed on the substrate. Emission tips that include such a low work function material may have improved performance. An etch mask appropriate for forming emission tips is patterned at desired locations over the substrate and any low work function material thereover. An anisotropic etch of at least the substrate is conducted to form vertical columns therefrom. A sacrificial layer may then be formed over the vertical columns. A facet etch of each vertical column forms an emission tip of the desired shape. If a sacrificial layer was formed over the vertical columns prior to formation of emission tips therefrom, the remaining material of the sacrificial layer may be utilized to facilitate the removal of any redeposition materials formed during the facet etch.

Abstract: A method of etching a trench in a substrate using a dry plasma etch technique that allows precise control of lateral undercut. The method includes optionally forming at least one on-chip device or micro-machined structure in a surface of a silicon substrate, and covering the surface with a masking layer. A trench pattern is then imaged in or transferred to the masking layer for subsequent etching of the substrate. Upper portions of the trench are anisotropically etched in the substrate. The trench is then semi-anisotropically etched and isotropically etched in the substrate. By modifying isotropic etching time, a controlled lateral undercut can be achieved as the trench is etched vertically in the substrate.

Abstract: In a semiconductor device, typically an active matrix display device, the structure of TFTs arranged in the respective circuits are made suitable in accordance with the function of the circuit, and along with improving the operating characteristics and the reliability of the semiconductor device, the manufacturing cost is reduced and the yield is increased by reducing the number of process steps.

Abstract: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

Abstract: Techniques for etching through a low capacitance dielectric layer in a plasma processing chamber are disclosed. The techniques uses an etch chemistry that includes N2, O2, and a hydrocarbon. By etching the low capacitance dielectric layer with a plasma created out of the etch chemistry, fast etch rates can be obtained while also maintaining profile control and preserving critical dimension of the resultant opening (e.g., via/trench) being etched in the low capacitance layer.

Abstract: In a bottom gate type semiconductor device made of a semiconductor layer with crystal structure, source/drain regions are constructed by a lamination layer structure including a first conductive layer (n+ layer), a second conductive layer (n− layer) having resistance higher than the first conductive layer, and an intrinsic or substantially intrinsic semiconductor layer (i layer). At this time, the n− layer acts as LDD region, and the i layer acts as an offset region is a film thickness direction.

Abstract: A plasma etching method includes forming polymer material over at least some internal surfaces of a plasma etch chamber and forming polymer material over at least some surfaces of a semiconductor wafer received within the plasma etch chamber. Substantially all polymer material is plasma etched from the chamber internal surfaces while at least some polymer material remains on the wafer. In another aspect, a semiconductor wafer is positioned on a wafer receiver within a plasma etch chamber. A photoresist layer has previously been formed thereon and has openings formed therethrough. First plasma etching is conducted through openings formed in the photoresist layer with a gas comprising carbon and a halogen to form openings in material on the wafer. A first polymer comprising carbon and the halogen forms over at least some internal surfaces of the plasma etch chamber during the first plasma etching.

Abstract: A method for forming a contact hole in a semiconductor device includes the steps of forming a polymer layer on an upper portion and a side wall of photo resist mask, while etching an oxide layer under the photoresist mask to form a contact hole that uses an etchant gas comprising CH2F2 gas; and etching the oxide layer while stopping the supply of CH2F2 gas to the etching process.

Abstract: A process for forming sub-lithographic features in an integrated circuit is disclosed herein. A process for enhancing the etch trimmability and the etch stability of features patterned on a photoresist layer is also disclosed herein. The process includes curing a photoresist layer after patterning and development but before an etch process is performed thereon. By controlling the formation of the cured portions of the features patterned on the photoresist layer, the features can be trimmed to sub-lithographic critical dimensions without pattern deformation or occurrence of other failure mechanisms.

Abstract: A new method of fabricating shallow trench isolations has been achieved. A pad oxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A protective layer is deposited overlying the silicon nitride layer. The protective layer, the silicon nitride layer, and the pad oxide layer are patterned to expose the semiconductor substrate where shallow trench isolations are planned. The semiconductor substrate is etched to form trenches for the planned shallow trench isolations. A large trench etching angle is used. The presence of the protective layer prevents loss of the silicon nitride layer during the etching. A trench filling layer is deposited overlying the protective layer and filling the trenches. The trench filling layer and the protective layer are polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.